JPH088341A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH088341A JPH088341A JP16268194A JP16268194A JPH088341A JP H088341 A JPH088341 A JP H088341A JP 16268194 A JP16268194 A JP 16268194A JP 16268194 A JP16268194 A JP 16268194A JP H088341 A JPH088341 A JP H088341A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- oxide film
- film
- oxide
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、段差を有する半導体基板を平坦にするた
めの酸化膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an oxide film for flattening a semiconductor substrate having a step.
【0002】[0002]
【従来の技術】従来、段差形状を有する半導体基板を平
坦化する方法として、図2に示した過程による方法が知
られている。この方法は、先ず、図2−aに示すよう
に、半導体基板1上に金属配線2を形成した上に、適宜
な膜厚(例えば300nm)の一層目の酸化膜3を化学
蒸着法によって形成する。ここで化学蒸着法による酸化
膜の形成は、段差被覆率が低いため、配線の段差を緩和
することができず、アルミ配線の形成時に配線切れを生
じるなどの問題があるので、次に図2−bに示すよう
に、SOG膜4を塗布法によって形成して段差部分を緩
和する。この後、図2−cに示すように、二層目の酸化
膜5を化学蒸着法により必要な膜圧(例えば600n
m)だけ形成し、平坦化を行う。2. Description of the Related Art Conventionally, as a method for flattening a semiconductor substrate having a step shape, a method according to the process shown in FIG. 2 is known. In this method, first, as shown in FIG. 2A, a metal wiring 2 is formed on a semiconductor substrate 1, and then a first oxide film 3 having an appropriate film thickness (for example, 300 nm) is formed by a chemical vapor deposition method. To do. Since the step coverage of the oxide film formed by the chemical vapor deposition is low, the step difference of the wiring cannot be alleviated, and there is a problem that the wiring is broken when the aluminum wiring is formed. As shown in -b, the SOG film 4 is formed by a coating method to reduce the step portion. Thereafter, as shown in FIG. 2C, the second oxide film 5 is formed by a chemical vapor deposition method at a required film pressure (for example, 600 n).
Only m) is formed and flattening is performed.
【0003】[0003]
【発明が解決しようとする課題】上記従来法で平坦化を
行った場合、図3−aに示すように、化学蒸着法で形成
した一層目の酸化膜3の段差被覆率が低いために、一層
目の酸化膜3の膜厚が段差底部で薄くなり、SOG膜4
を形成した際に、SOG膜4のストレスによって一層目
の酸化膜3に亀裂6が生じることがあり、信頼性を損な
うという問題があった。When the planarization is performed by the above-mentioned conventional method, as shown in FIG. 3A, the step coverage of the first oxide film 3 formed by the chemical vapor deposition method is low. The thickness of the oxide film 3 of the first layer becomes thin at the bottom of the step, and the SOG film 4
There is a problem that the stress of the SOG film 4 may cause cracks 6 in the oxide film 3 in the first layer when the film is formed, resulting in impaired reliability.
【0004】一層目の酸化膜3に亀裂6が生じないよう
にするためには、一層目の酸化膜3を厚くすれば良い
が、図3−bに示すように、一層目の酸化膜3を過度に
厚くすると、化学蒸着法の酸化膜は段差被覆性が悪いた
めに段差部分に空洞7を生じるという問題があった。In order to prevent cracks 6 from occurring in the oxide film 3 of the first layer, the oxide film 3 of the first layer may be thickened, but as shown in FIG. If the thickness is too thick, there is a problem in that the oxide film formed by the chemical vapor deposition method has a poor step coverage, so that the cavity 7 is formed in the step portion.
【0005】本発明は、このような従来技術の不都合を
改善するべく案出されたものであり、その主な目的は、
平坦性が良く、信頼性の高い酸化膜を形成することの可
能な半導体基板の製造方法を提供することにある。The present invention was devised in order to improve such disadvantages of the prior art, and its main purpose is to:
It is an object of the present invention to provide a method for manufacturing a semiconductor substrate, which is capable of forming an oxide film having good flatness and high reliability.
【0006】[0006]
【課題を解決するための手段】このような目的は、本発
明によれば、凹凸形状が形成された基板表面に保護膜を
備える半導体装置の製造方法であって、前記基板の表面
の少なくとも最も小さな凹部の開口が閉塞されるまで前
記基板上に第1の酸化膜を堆積させる過程と、該酸化膜
をエッチバックして前記基板の表面の凹部を再び開口さ
せる過程と、該開口を含む前記基板の表面にSOG膜を
塗布して前記開口を埋める過程と、前記基板の表面に第
2の酸化膜を堆積させる過程とを有することを特徴とす
る半導体装置の製造方法を提供することによって達成さ
れる。According to the present invention, such an object is a method of manufacturing a semiconductor device comprising a protective film on the surface of a substrate on which unevenness is formed, and at least the most of the surface of the substrate is provided. Depositing a first oxide film on the substrate until the opening of the small recess is closed; etching back the oxide film to reopen the recess on the surface of the substrate; and including the opening. Achieved by providing a method of manufacturing a semiconductor device, comprising: a step of applying an SOG film on a surface of a substrate to fill the opening; and a step of depositing a second oxide film on the surface of the substrate. To be done.
【0007】[0007]
【作用】本発明による方法で平坦化を行うと、段差底部
の絶縁膜を厚くすることが可能となるため、この絶縁膜
上に形成されSOG膜が原因で絶縁膜に亀裂を生じるこ
とがなくなる。When the flattening is performed by the method according to the present invention, the insulating film at the bottom of the step can be thickened, so that the SOG film formed on this insulating film will not cause cracks in the insulating film. .
【0008】[0008]
【実施例】以下に添付の図面に示した実施例を参照して
本発明について詳細に説明する。図1は本発明の好適実
施例を示す概略図である。まず、半導体基板1上に金属
配線層を形成した後、その金属配線層を図示しないフォ
トレジストパターンを用いて選択エッチングする。する
と、金属配線2による凹凸形状が半導体基板1の表面に
形成されるので、この状態で半導体基板1の表面が平坦
になるまで、化学蒸着法によって半導体基板1上に酸化
膜3を形成する。即ち、図1−aに示すように、半導体
基板1表面の最も小さい凹部の開口Cが閉塞されるま
で、半導体基板1上に酸化膜3を堆積させる。なお、こ
の状態で、酸化膜3で覆われなかった部分が空洞7とな
って段差部分に残っている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the accompanying drawings. FIG. 1 is a schematic diagram showing a preferred embodiment of the present invention. First, after forming a metal wiring layer on the semiconductor substrate 1, the metal wiring layer is selectively etched using a photoresist pattern (not shown). Then, since the uneven shape due to the metal wiring 2 is formed on the surface of the semiconductor substrate 1, the oxide film 3 is formed on the semiconductor substrate 1 by the chemical vapor deposition method until the surface of the semiconductor substrate 1 becomes flat in this state. That is, as shown in FIG. 1A, the oxide film 3 is deposited on the semiconductor substrate 1 until the opening C of the smallest recess on the surface of the semiconductor substrate 1 is closed. In this state, the portion not covered with the oxide film 3 becomes the cavity 7 and remains in the step portion.
【0009】次に、図1−bに示すように、層間絶縁膜
として必要な膜厚を残すためにエッチバックによって酸
化膜3の表面全体を削り、酸化膜3の表面に凹部を再び
開口させる。即ち、段差部分に生じていた空洞7の開口
Cが露出するまでエッチバックを行う。Next, as shown in FIG. 1B, the entire surface of the oxide film 3 is etched away by etching back in order to leave a film thickness required as an interlayer insulating film, and a concave portion is opened again on the surface of the oxide film 3. . That is, etching back is performed until the opening C of the cavity 7 that has occurred in the step portion is exposed.
【0010】次に、図1−cに示すように、酸化膜3の
表面を削ることによって現れたこの開口Cを、SOG膜
4を塗布することによって埋める。即ち、段差部分に生
じていた空洞7が、急峻な段差となっている状態で、S
OG膜で埋め尽くされる。Next, as shown in FIG. 1-c, the opening C, which has appeared by cutting the surface of the oxide film 3, is filled by applying the SOG film 4. That is, when the cavity 7 generated at the step portion has a steep step, S
It is filled with OG film.
【0011】しかる後、図1−dに示すように、必要な
膜厚の酸化膜5を化学蒸着法によって形成する。Thereafter, as shown in FIG. 1-d, an oxide film 5 having a required film thickness is formed by a chemical vapor deposition method.
【0012】以上の過程により、信頼性のある酸化膜3
による段差の緩和が行われた。Through the above process, the reliable oxide film 3
The steps were alleviated.
【0013】[0013]
【発明の効果】以上説明したように、本発明によれば、
SOG膜のストレスによる亀裂を生じることのない、信
頼性の高い段差緩和用の酸化膜を形成することができ
る。As described above, according to the present invention,
It is possible to form a highly reliable oxide film for step relief, which does not cause a crack due to stress in the SOG film.
【図1】本発明による段差緩和用の酸化膜の形成方法を
説明する過程図。FIG. 1 is a process diagram illustrating a method of forming an oxide film for reducing a step according to the present invention.
【図2】従来の平坦化方法を説明する過程図。FIG. 2 is a process diagram illustrating a conventional flattening method.
【図3】従来の平坦化方法の問題点の説明図。FIG. 3 is an explanatory view of problems of the conventional flattening method.
1 半導体基板 2 金属配線 3 酸化膜(一層目) 4 SOG膜 5 酸化膜(二層目) 6 亀裂 7 空洞 1 Semiconductor Substrate 2 Metal Wiring 3 Oxide Film (First Layer) 4 SOG Film 5 Oxide Film (Second Layer) 6 Crack 7 Cavity
Claims (1)
を備える半導体装置の製造方法であって、 前記基板の表面の少なくとも最も小さな凹部の開口が閉
塞されるまで前記基板上に第1の酸化膜を堆積させる過
程と、 該酸化膜をエッチバックして前記基板の表面の凹部を再
び開口させる過程と、 該開口を含む前記基板の表面にSOG膜を塗布して前記
開口を埋める過程と、 前記基板の表面に第2の酸化膜を堆積させる過程とを有
することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device comprising a protective film on a surface of a substrate on which unevenness is formed, the method comprising: first forming a protective film on the substrate until at least the smallest concave opening on the surface of the substrate is closed. A step of depositing an oxide film, a step of etching back the oxide film to reopen a concave portion on the surface of the substrate, and a step of applying an SOG film to the surface of the substrate including the opening to fill the opening. And a step of depositing a second oxide film on the surface of the substrate, the method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16268194A JPH088341A (en) | 1994-06-21 | 1994-06-21 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16268194A JPH088341A (en) | 1994-06-21 | 1994-06-21 | Fabrication of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH088341A true JPH088341A (en) | 1996-01-12 |
Family
ID=15759278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16268194A Withdrawn JPH088341A (en) | 1994-06-21 | 1994-06-21 | Fabrication of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH088341A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024053695A1 (en) * | 2022-09-08 | 2024-03-14 | ソニーセミコンダクタソリューションズ株式会社 | Light detection device |
-
1994
- 1994-06-21 JP JP16268194A patent/JPH088341A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024053695A1 (en) * | 2022-09-08 | 2024-03-14 | ソニーセミコンダクタソリューションズ株式会社 | Light detection device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010904 |