JPH0590203A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the step coverage of a contact hole, and to realize the flattening of an interlayer insulating layer by a method wherein a contact hole is selectively formed on the insulating film of a substrate, the contact hole is filled up, and an electrode wiring is formed by thinning the thickness of the surface a metal film. CONSTITUTION:After a Ti film 4 and a TiN film 5 have been successively deposited on the surface including the contact hole provided on a BPSG film 3, the contact hole is filled up by depositing a thick Al-Si-Cu film 6 using a high temperature sputtering method. Subsequently, the surface of the Al-Si-Cu film 6 is thinned off by etching, and an electrode wiring is formed by patterning the Al-Si-Cu film 6, the TiN film 5 and the Ti film 4 successively. As a result, the contact hole is filled up without generation of voids on the metal film in the contact hole, the difficulty of microscopic processing when patterning and the difficulty of flattening of an interlayer insulating film, caused by the large aspect ratio of wiring, are removed, and the reliability of the electrode wiring can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming electrode wiring.

[0002]

2. Description of the Related Art Electrode wiring connected to an element region provided on a semiconductor substrate is mainly formed by a sputtering method. However, as the wiring becomes finer, a shadowing effect causes a contact hole step Coverage has deteriorated and wiring reliability has become a problem.

As one method for solving this problem, high temperature sputtering (a technique of performing sputter deposition while heating the substrate to a temperature close to the melting point of the material for sputtering) is applied by applying a conventional sputtering method. In this method, the sputtered particles move on the surface of the substrate so that the contact hole can be completely filled.

FIGS. 4A to 4C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method for manufacturing a semiconductor device.

As shown in FIG. 4A, a silica glass film (hereinafter referred to as a BPSG film) 3 containing boron and phosphorus is deposited on the surface of the semiconductor substrate 1 including the diffusion layer 2 and selectively. A hole is formed and a contact hole is formed.

Next, as shown in FIG. 4B, a Ti film 4 and a TiN film 5 are sequentially deposited on the surface including the contact holes by a sputtering method, and Si and Cu are deposited on the TiN film 5.
An Al film (hereinafter referred to as an Al—Si—Cu film) 6 containing is deposited to a thickness of 1 μm by a high temperature sputtering method.

Next, as shown in FIG. 4C, Al--Si--C is formed by photolithography and etching.
The u film 6 is patterned to form electrode wiring.

[0008]

In this conventional method of manufacturing a semiconductor device, since the supply amount of the metal film for forming the electrode wiring into the contact hole is insufficient, as shown in FIG. The conductive film may not be deposited on the side wall.

Further, if the film thickness is made considerably large in order to completely fill the contact hole and realize flattening of the metal film, fine processing in patterning the metal film for forming the electrode wiring is considerably difficult. Figure 5 (b)
As shown in FIG. 3, the aspect ratio of the electrode wiring (ratio between the film thickness of the wiring and the wiring width) is considerably large, which hinders the flattening of the interlayer insulating film 7 provided on the electrode wiring. There was a problem that it became difficult to make it.

[0010]

A method of manufacturing a semiconductor device according to the present invention comprises a step of selectively forming a contact hole in an insulating film provided on a semiconductor substrate, and a step of forming a metal film to be deposited on the semiconductor substrate. A step of thickly depositing a metal film on a surface including a contact hole while heating the semiconductor substrate to a temperature near a melting point to fill the inside of the contact hole, and a step of etching the surface of the metal film to reduce the thickness. And a step of selectively etching and patterning the metal film to form an electrode wiring.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (c) and FIG. 2 (a),
(B) is sectional drawing of the semiconductor chip shown in order of process for demonstrating the 1st Example of this invention.

First, as shown in FIG. 1A, a BPSG film 3 having a thickness of 1 μm is formed on a surface of a semiconductor substrate 1 including a diffusion layer 2.
Deposit to a thickness of m.

Next, as shown in FIG. 1B, the diffusion layer 2
A contact hole is formed by selectively anisotropically etching the BPSG film 3 on the substrate.

Next, as shown in FIG. 1C, a Ti film 4 having a thickness of 30 nm and a TiN film 5 having a thickness of 100 nm are sequentially deposited on the surface including the contact holes by a sputtering method.

Next, the Al—Si—Cu film 6 is deposited on the TiN film 5 by the high temperature sputtering method to a thickness of 2.0 μm by the high temperature sputtering method to fill the inside of the contact hole. Here, the semiconductor substrate 1 is maintained at a temperature near the melting point of the Al-Si-Cu film 6.

Next, as shown in FIG. 2 (a), Al--S
The surface of the i-Cu film 6 is anisotropically etched by a thickness of 1.5 μm to planarize the surface, and the film thickness for electrode wiring is adjusted.

Next, as shown in FIG. 2 (b), Al--S
The i-Cu film 6, the TiN film 5, and the Ti film 4 are sequentially patterned to form electrode wirings connected to the diffusion layer 2.

3 (a) and 3 (b) are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

As shown in FIG. 3A, the BPSG film 3 is formed on the surface of the semiconductor substrate 1 including the diffusion layer 2 by the same process as that of the first embodiment, and the anisotropic etching gas type, By controlling the pressure, the substrate temperature, the plasma output, etc., a contact hole whose side wall has an inclination of about 80 degrees is formed.

Next, as shown in FIG. 3B, a Ti film 4 having a thickness of 30 nm and a TiN film 5 having a thickness of 100 nm are sequentially deposited by the sputtering method by the same process as in the first embodiment. After that, the Al—Si—Cu film 6 is deposited to a thickness of 1.5 μm by the high temperature sputtering method. Next, Al-Si-
The surface of the Cu film 6 is etched to a thickness of 1.0 μm to reduce the thickness, and then the Al—Si—Cu film 6, the TiN film 5, and the Ti film 4 are sequentially patterned to form an electrode wiring.

As a peculiar effect of the second embodiment, by providing the side wall of the contact hole with an inclination, flattening after film formation can be achieved with a metal film having a small film thickness, so that the amount of etch back is small. I'm done. Therefore, the uniformity of the film thickness is improved, and the reliability of the post process is improved.

[0023]

As described above, according to the present invention, while heating the substrate at a high temperature, the metal film is deposited to a film thickness where the contact portion is completely buried, and then the metal film is left with a film thickness necessary for wiring formation. By etching back the film and then patterning it to form the electrode wiring, the contact hole is filled without forming a void in the metal film, and it is difficult to perform fine processing during patterning and the wiring aspect ratio (wiring thickness And the wiring width ratio) are large, the difficulty of flattening the interlayer insulating film is eliminated, the reliability of the electrode wiring is improved, and the multilayered wiring can be sufficiently coped with.

[Brief description of drawings]

1A to 1C are cross-sectional views of a semiconductor chip showing the order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip showing the order of steps for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.

FIG. 5 is a cross-sectional view of a semiconductor chip for explaining problems of a conventional semiconductor device.

[Explanation of symbols]

 1 semiconductor substrate 2 diffusion layer 3 BPSG film 4 Ti film 5 TiN film 6 Al-Si-Cu film 7 interlayer insulating film

Claims (1)

[Claims] 1. A step of selectively forming a contact hole in an insulating film provided on a semiconductor substrate, and a step of heating the semiconductor substrate to a temperature near the melting point of a metal film to be deposited on the semiconductor substrate. Including a step of depositing a metal film thickly on the surface to fill the inside of the contact hole, a step of etching the surface of the metal film to reduce the thickness, and a step of selectively etching and patterning the metal film. And a step of forming an electrode wiring.