JPS5874037A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5874037A JPS5874037A JP56174310A JP17431081A JPS5874037A JP S5874037 A JPS5874037 A JP S5874037A JP 56174310 A JP56174310 A JP 56174310A JP 17431081 A JP17431081 A JP 17431081A JP S5874037 A JPS5874037 A JP S5874037A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- resist
- wiring layer
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- 229910052782 aluminium Inorganic materials 0.000 description 15
- 238000005530 etching Methods 0.000 description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法、特にコンタクト開孔
部での配線電極のオーミック接続に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to ohmic connection of wiring electrodes at a contact opening.
最近の集積回路の集積度の向上につれて配線幅の微細化
、配線を接続するためのコンタクト孔の縮小化が必須と
なっている。したがって、コンタクト開孔部での配線間
の接触する面積が小さくなシ配線間めオーミック接続が
困難になシうつある。2. Description of the Related Art As the degree of integration of integrated circuits has increased in recent years, it has become essential to miniaturize wiring widths and reduce the size of contact holes for connecting wirings. Therefore, it becomes difficult to establish an ohmic connection between wiring lines in which the contact area between the wiring lines is small at the contact opening.
まだ、プロセスの自動化、パターンの微細化などのため
に、従来の７ツ酸を緩和して用い友エツチング□液によ
るエツチング法（等方性エッチイブ）から、スパッター
現像を利用した、特に平行平板型のプラズマエツチング
法（異方性エツチング）を川伝るようになってきた。し
かしながら岬方性エツチングに比べ、異方性エツチング
は、コンタクト段部でのサイドエッチシフが極めて少な
いので、コンタクト段部でのテーパーがきびしくなる事
が知もれてい′る−
そこで、形成するパターンの最小寸法を１μｍが限界で
あるとする、つまシコンタクトサイズを１２ｍＸ１μｍ
にし、絶縁膜厚を１μｍとした場合、等方性エツチング
法では、当然のことながら、サイドエツチングが片＃Ｊ
１μｍとなるため両側で２μｍとなり、コンタクトサ
イズ１μｍと両側のサイドエツチング量２μｍとで最低
３μｍの余裕度が必要となｐ高集積化を制限するもので
ある。したがって３μｍ、以下のコンタクト孔を形成す
るにはサイドエツチングが極めて少ない異方性エツチン
グ法（４１に平行平板型エツチング）でコンタクト孔を
ほぼマスク通シのサイズに形成する必要がある。In order to automate processes and make patterns finer, the conventional etching method (isotropic etch) using a diluted hexafluoride solution (isotropic etch) has been replaced by a method using sputter development, especially the parallel plate type. The plasma etching method (anisotropic etching) has become popular. However, compared to cape-oriented etching, anisotropic etching has extremely little side etch shift at the contact step, so it is known that the taper at the contact step becomes severe. 1μm is the limit for the minimum dimension of
When the insulating film thickness is 1 μm, the isotropic etching method naturally causes side etching to occur on one side #J.
Since the contact size is 1 .mu.m, it becomes 2 .mu.m on both sides, which limits the high integration of p, which requires a margin of at least 3 .mu.m between the contact size of 1 .mu.m and the side etching amount of 2 .mu.m on both sides. Therefore, in order to form a contact hole of 3 .mu.m or less, it is necessary to form the contact hole approximately in size through the mask using an anisotropic etching method (parallel plate type etching 41) with very little side etching.
次に金属配線層（特にアルミニウム層）を蒸着するわけ
であるが、ここで蒸着の機構として高真空中で蒸発物（
アルミニウム）が加熱され蒸発原子（アルミニウム原子
）が基体へ付着するが仁の蒸発原子（アルミニウム原子
）は基体に対して方向性を特りているためＪ第１図（ａ
） 、 （ｂ）のようなコンタクト段部のくほみの部分
は、陰になりてしまいアル１＝ウム原子が付着されにく
い事が知られている。したがりて結果的には、コンタク
ト段部でのテーパーがきびしい場合第１図（ｂ）のよう
に最悪の場合、アルミニウム配線層は段切れが生じてし
まうという欠点があった。この事は半導体製品の製造歩
留シ、しいてはその信頼性を損う要因となっていた。Next, a metal wiring layer (particularly an aluminum layer) is deposited, and the deposition mechanism is that of evaporated material (
When the aluminum (aluminum) is heated, the evaporated atoms (aluminum atoms) adhere to the substrate, but since the evaporated atoms (aluminum atoms) have a specific direction with respect to the substrate,
), (b) It is known that the hollow part of the contact step is shaded and it is difficult for Al1=Uium atoms to adhere thereto. Therefore, as a result, if the taper at the contact step is severe, in the worst case, as shown in FIG. 1(b), the aluminum wiring layer has the disadvantage that a break occurs in the step. This has become a factor that impairs the manufacturing yield of semiconductor products and, in turn, their reliability.
本発明は、配線電極が必要とする全てのコンタクト開孔
部でコンタクト段部でのテーパーがきびしい形状でも配
線電極をオーミックに接続でき、しかもその段切れを少
なくできる事を目的とする半導体装置の製造方法を提供
することにある０本発明をよシ具体的に説明すると、半
導体基体の一部とオーミックコンタクトを有する金属配
線層ヲ有し１３μｍ以下のコンタクト孔を有する半導体
装置の製法において、電極をとシ出すコンタクトの開孔
後金面に多結晶シリコン層を成長する工程と、配線電極
と、して全面に第１の金属配線層を成長する工程と、門
１の金属配線層の厚さよシも厚くホトレジストを全面に
塗布し前記ホトレジストの膜厚分だけを全面除去させて
コンタクト孔にホトレジストの一部を残留せしめる工程
と、前記金属配線層を前記ホトレジストをマスクとして
除去する工程と、前記コンタクト開孔部に残留した前記
ホトレジストを除去し、全面に配！！！電極として第２
の金属配線層を成長して前記コンタクト開孔部に残留し
良前記金属配線層と接続し、十分オーミックなコンタク
トを得る工程とを有する半導体装置の製造方法である。The present invention is directed to a semiconductor device which is capable of ohmically connecting wiring electrodes in all contact openings required by the wiring electrodes, even if the contact steps have a severely tapered shape, and also reducing the number of step breaks. The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which includes a metal wiring layer having ohmic contact with a part of a semiconductor substrate and a contact hole of 13 μm or less. A step of growing a polycrystalline silicon layer on the gold surface after forming a contact hole to remove the contact, a step of growing a first metal wiring layer on the entire surface as a wiring electrode, and a step of growing a first metal wiring layer on the entire surface as a wiring electrode, and determining the thickness of the metal wiring layer of gate 1. a step of applying a thick photoresist over the entire surface and removing only the thickness of the photoresist to leave a portion of the photoresist in the contact hole; a step of removing the metal wiring layer using the photoresist as a mask; The photoresist remaining in the contact opening is removed and distributed over the entire surface! ! ! Second electrode
The method of manufacturing a semiconductor device includes the step of growing a metal wiring layer remaining in the contact opening and connecting it to the metal wiring layer to obtain a sufficiently ohmic contact.
次に本発明の実施例につき図を用いて説明する＠まず、
公知の半導体装置の製造プロセスで、電極部１上および
層間ＰＥＧ層２上に多結晶シリコン層４′ｔ−設け、そ
の上に配線材料として全面にアルミニウム層３を蒸着し
ホトレジスト５ｔ−塗布するまでを行ない、第２図（ａ
）を得る。この時前述した理由によシ、コンタクト段部
でのテーパーがきひしいためアルミ隼つム層３は段切れ
してしまう。Next, examples of the present invention will be explained using figures.@First,
In a known semiconductor device manufacturing process, a polycrystalline silicon layer 4't- is provided on the electrode portion 1 and the interlayer PEG layer 2, and then an aluminum layer 3 is deposited on the entire surface as a wiring material, and a photoresist 5t- is applied thereon. Figure 2 (a)
). At this time, for the reason mentioned above, the taper at the step of the contact is severe, so that the aluminum layer 3 is broken.
またホトレジスト５はその流動性のためコンタクト段部
でａｒｔは平坦になる。つｔ〕、結果的に〈埋みの部分
のホトレジスト５の膜厚は厚くなる・次に全面に塗布し
九ホトレジス）Ｓｔ塗布した膜厚分のみを全面に０２プ
ラス！でエツチングし第２図（ｂ）を得る。この時ホト
レジスト膜厚で決められる時間でエツチングを終了させ
ればコンタクト孔のくぼみにホトレジスト５は、残存す
ることは理解されることである。次に全面に蒸着したア
ルミニウム層３を膜厚分のみを異方性エツチング、特に
平行平板型でエツチングし、第３図（ａ）を得る。Further, due to the fluidity of the photoresist 5, art becomes flat at the contact step portion. As a result, the thickness of the photoresist 5 in the buried area becomes thicker.Next, apply it to the entire surface and add 02 to the entire surface only by the thickness of the photoresist applied! 2(b) is obtained. It is understood that the photoresist 5 will remain in the recess of the contact hole if the etching is completed within a time determined by the photoresist film thickness. Next, the aluminum layer 3 deposited on the entire surface is etched by anisotropic etching, particularly by a parallel plate type, only by the film thickness, to obtain the result shown in FIG. 3(a).
この時、ホトレジスト５は選択比の関係から多少エツチ
ングされるが残存する・しかし必すしも異方性エツチン
グを用いる必要もない事は明白である。また、当然のこ
ととして、ホトレジスト５の下のアルミニウム層３も残
存する・次に残存しているホトレジスト５を公知の方法
にて除去し再びアルミニウム層６を蒸着し、第３図（ｂ
）ｔ−得て本発明は達成される。本発明は、コンタクト
孔にアルミニウム層を残し、基体表面を平坦化して、ア
ルミニウム層の断線を防ごうとすることが目的で、At this time, the photoresist 5 is etched to some extent due to selectivity, but remains; however, it is clear that it is not necessary to use anisotropic etching. Also, as a matter of course, the aluminum layer 3 under the photoresist 5 also remains.Next, the remaining photoresist 5 is removed by a known method, and the aluminum layer 6 is deposited again.
) t-The present invention is achieved. The purpose of the present invention is to leave an aluminum layer in the contact hole and flatten the substrate surface to prevent disconnection of the aluminum layer.
第１図は、従来の配線層の成長後の断面図であり、（ａ
）はコンタクト開孔法を等方性エツチングで行なり九も
ので、（ｂ）は異方性エツチングで行なったものである
。
尚、第１図において、１・・・・・・アルミニウム配線
層と接続される電極部、２・・・・・・層間Ｐ２Ｏ層、
３・・・・・・アル１＝ウム配線層。第２図および第３
図は本発明による半導体装置の製造工程の断面図を示す
。
尚、第２図および第３図において、１・・・・・・アル
ミニウム配線層と接続される電極部、２・・・・・・層
間Ｐ２Ｏ層、３・・・・・・第１アルミニウム配線層、
４・・・多結晶シリコン層、５・・・・・・ホトレジス
ト、６・・・・・・第２アルミニウム配線層。
代理人 弄、−士 内 原 晋
第 ｌ 図
第 ２ 図
第３ 図FIG. 1 is a cross-sectional view of a conventional wiring layer after growth, and (a
) is a contact hole-opening method performed by isotropic etching, and (b) is a contact hole method performed by anisotropic etching. In FIG. 1, 1... electrode portion connected to the aluminum wiring layer, 2... interlayer P2O layer,
3...Al1=Um wiring layer. Figures 2 and 3
The figure shows a cross-sectional view of the manufacturing process of a semiconductor device according to the present invention. In addition, in FIG. 2 and FIG. 3, 1... electrode portion connected to the aluminum wiring layer, 2... interlayer P2O layer, 3... first aluminum wiring layer,
4... Polycrystalline silicon layer, 5... Photoresist, 6... Second aluminum wiring layer. Figure 2 Figure 3
Claims (1)
記絶縁層上の多結晶シリコン層の上および前記開孔内の
多結晶シリコン層上に第１の金属配線層を形成する工程
と、前記開孔内の第１の金属配線層の部分上にホトレジ
ストを残余せしめ、前記絶縁層上の第１の金属配線層上
のホトレジストを残去せしめる工程と、前記絶縁層上の
第１の金属配線層を除去する工程と、前記残余せるホト
レジストを除去する工程と、第２の金属配線層を形成し
て、前配開孔内に残留した前記第１の金属配線層との部
分と該第２の金属配線層とを接続する工程とを有する事
を特徴とする半導体装置の製造方法。forming an opening in the insulating layer, and forming a first metal wiring layer on the insulating layer and within the opening, over the polycrystalline silicon layer on the insulating layer and on the polycrystalline silicon layer within the opening; a step of leaving photoresist on a portion of the first metal interconnection layer within the opening, a step of leaving photoresist on the first metal interconnection layer on the insulating layer; A step of removing the first metal wiring layer, a step of removing the remaining photoresist, and a step of forming a second metal wiring layer to remove the first metal wiring layer remaining in the pre-opening hole. 1. A method for manufacturing a semiconductor device, comprising the step of connecting the second metal wiring layer to the second metal wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56174310A JPS5874037A (en) | 1981-10-29 | 1981-10-29 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56174310A JPS5874037A (en) | 1981-10-29 | 1981-10-29 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5874037A true JPS5874037A (en) | 1983-05-04 |
Family
ID=15976414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56174310A Pending JPS5874037A (en) | 1981-10-29 | 1981-10-29 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5874037A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010718A (en) * | 1983-06-30 | 1985-01-19 | Nec Corp | Manufacture of semiconductor device |
| JPS62281468A (en) * | 1986-05-30 | 1987-12-07 | Fujitsu Ltd | Semiconductor device |
| US5266521A (en) * | 1991-03-20 | 1993-11-30 | Samsung Electronics Co., Ltd. | Method for forming a planarized composite metal layer in a semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4533365Y1 (en) * | 1967-12-27 | 1970-12-19 | ||
| JPS4722361U (en) * | 1971-03-26 | 1972-11-13 | ||
| JPS5435967U (en) * | 1977-08-16 | 1979-03-09 | ||
| JPS5518610U (en) * | 1978-07-20 | 1980-02-06 | ||
| JPS5660812U (en) * | 1979-10-18 | 1981-05-23 |
-
1981
- 1981-10-29 JP JP56174310A patent/JPS5874037A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4533365Y1 (en) * | 1967-12-27 | 1970-12-19 | ||
| JPS4722361U (en) * | 1971-03-26 | 1972-11-13 | ||
| JPS5435967U (en) * | 1977-08-16 | 1979-03-09 | ||
| JPS5518610U (en) * | 1978-07-20 | 1980-02-06 | ||
| JPS5660812U (en) * | 1979-10-18 | 1981-05-23 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010718A (en) * | 1983-06-30 | 1985-01-19 | Nec Corp | Manufacture of semiconductor device |
| JPS62281468A (en) * | 1986-05-30 | 1987-12-07 | Fujitsu Ltd | Semiconductor device |
| US5266521A (en) * | 1991-03-20 | 1993-11-30 | Samsung Electronics Co., Ltd. | Method for forming a planarized composite metal layer in a semiconductor device |
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