JP3033839B2 - Method for forming contact hole in semiconductor device - Google Patents
Method for forming contact hole in semiconductor deviceInfo
- Publication number
- JP3033839B2 JP3033839B2 JP2293695A JP29369590A JP3033839B2 JP 3033839 B2 JP3033839 B2 JP 3033839B2 JP 2293695 A JP2293695 A JP 2293695A JP 29369590 A JP29369590 A JP 29369590A JP 3033839 B2 JP3033839 B2 JP 3033839B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- insulating film
- contact hole
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は多層配線構造を有する半導体装置のコンタク
トホールの形成方法に関し、特にコンタクトホールの微
細な開孔縁部の傾斜の緩和および凹部の平坦度の向上を
可能にする方法に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a method for forming a contact hole in a semiconductor device having a multilayer wiring structure, and more particularly, to alleviating the inclination of a fine opening edge of the contact hole and flattening a concave portion. To a method that can improve the degree.
（従来技術） 従来、多層配線構造を有する半導体装置では、半導体
基板上の拡散層や多結晶シリコン等の、導電層上に開孔
（例えば、コンタクトホール，スルーホール）を有する
層間絶縁膜を形成したのちに、層間絶縁膜の上に金属配
線層を形成し、これら導電層と金属配線層をこれら開孔
を通じて電気的に接続する構造が一般に用いられてい
る。ところが、近年、素子の微細化が著しく、上記の開
孔も必然的に小さくなり、それにとなもいコンタクトホ
ールの深さに対する開孔寸法の割合、いわゆるアスペク
ト比が増大している。またこのような開孔には一般にRI
E法を用いた異方性エッチングが行われるため、開孔の
側壁はほぼ垂直な角度に形成され、極めて急峻なものと
なる。(Prior Art) Conventionally, in a semiconductor device having a multilayer wiring structure, an interlayer insulating film having openings (for example, contact holes and through holes) is formed on a conductive layer such as a diffusion layer on a semiconductor substrate or polycrystalline silicon. After that, a structure is generally used in which a metal wiring layer is formed on the interlayer insulating film, and these conductive layers and the metal wiring layer are electrically connected through these openings. However, in recent years, the size of the element has been remarkably miniaturized, and the above-described opening has been inevitably reduced. As a result, the ratio of the opening size to the depth of the contact hole, that is, the so-called aspect ratio has increased. In addition, such holes are generally RI
Since the anisotropic etching using the E method is performed, the side wall of the opening is formed at a substantially vertical angle, and becomes extremely steep.
したがって、このような開孔に上層としての金属配線
層のような導電性膜を形成した場合、開孔エッジ部にお
けるステップカバレージ性を向上させることは難しく、
開孔側壁部および底部で極端にその膜厚が薄くなり、配
線抵抗の増大、断線等、製品の歩留の低下や、信頼性の
低下を生じる原因となっている。Therefore, when a conductive film such as a metal wiring layer as an upper layer is formed in such an opening, it is difficult to improve the step coverage at the opening edge portion,
The film thickness becomes extremely thin at the side wall and the bottom of the opening, which causes a decrease in product yield and a decrease in reliability such as an increase in wiring resistance and disconnection.
（発明が解決しようとする課題） 従来技術のこれら問題を解決するため、開孔部の側壁
の傾斜を緩和するテーパー形状を有する開孔を形成か試
みられているが、テーパー角度の制御性が悪く、寸法制
御性を悪化させる問題等があり、素子，加工寸法の微細
化に対して実際にこれを適用することが困難である。(Problems to be Solved by the Invention) In order to solve these problems in the prior art, an attempt has been made to form an opening having a tapered shape to alleviate the inclination of the side wall of the opening, but the controllability of the taper angle has been reduced. However, there is a problem that the dimensional controllability is deteriorated, and it is difficult to actually apply this to miniaturization of elements and processing dimensions.
本発明は以上述べた微細な開孔部での導電性膜のステ
ップカバレージの悪化による抵抗増大や、断線等の問題
およびテーパー形状を有する開孔の加工精度の低下にと
もなう問題点を除去するため、加工寸法より小さな寸法
のテーパー形状を有する開孔の開設を可能とする半導体
装置の製造方法を提供することを目的とする。The present invention is to eliminate the problems described above, such as the increase in resistance due to the deterioration of the step coverage of the conductive film in the fine opening, the problems such as disconnection, and the reduction in the processing accuracy of the opening having a tapered shape. It is another object of the present invention to provide a method of manufacturing a semiconductor device, which can form an opening having a tapered shape smaller than a processing size.
（課題を解決するための手段） 上記課題を解決するため、本発明は、半導体基板の主
表面上に絶縁膜を形成し、この絶縁膜上に所定の幅の開
孔パターンを有するフォトレジストマスクを形成し、こ
の開孔パターンに露出した上記絶縁膜に対して異方性エ
ッチングを施すことにより、上記所定の幅に応じた凹部
を形成し、次に上記フォトレジストマスクを除去して、
上記凹部の側壁に塗布焼成膜を形成し、その後、上記半
導体基板の表面が露出するまで、上記塗布焼成膜及び上
記絶縁膜に対して異方性エッチングを施すことにより半
導体装置のコンタクトホールを形成したものである。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a photoresist mask having an insulating film formed on a main surface of a semiconductor substrate and having an opening pattern of a predetermined width on the insulating film. Is formed, by performing anisotropic etching on the insulating film exposed to the opening pattern, forming a concave portion corresponding to the predetermined width, and then removing the photoresist mask,
Forming a coated and fired film on the side wall of the concave portion, and thereafter forming a contact hole of the semiconductor device by performing anisotropic etching on the coated and fired film and the insulating film until the surface of the semiconductor substrate is exposed. It was done.
（作 用） 低濃度のシリコンを主成分とする溶液の回転塗布およ
び熱処理により、鋭角をもって形成される開孔の側壁と
底とのコーナー部に集中し開孔のエッジからその底へと
なだらかに下がるSOG膜が選択的に形成される。このSOG
膜の傾斜を利用してエッチバックすることにより、面積
が小さく且つステップカバレージの良好なコンタクトが
得られる。(Operation) By spin coating and heat treatment of a solution containing low-concentration silicon as a main component, it is concentrated at the corner between the side wall and the bottom of the opening formed at an acute angle, and smoothly from the edge of the opening to the bottom. A lower SOG film is selectively formed. This SOG
By performing the etch-back using the inclination of the film, a contact having a small area and good step coverage can be obtained.
（実施例） 第１図（ａ）〜（ｄ）に従って本発明の一実施例を説
明する。Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (d).
第１図（ａ）に示すように半導体基板１（例えばＰ型
シリコン）上に層間絶縁膜２をCVD法により形成する。As shown in FIG. 1A, an interlayer insulating film 2 is formed on a semiconductor substrate 1 (for example, P-type silicon) by a CVD method.
次に第１図（ｂ）に示すように例えばフォスフォシリ
ケートガラス（PSG）あるいはボロフォスフォシリケー
トガラス（BPSG）膜を例えば10000Å程度形成したの
ち、所定の位置にコンタクト部分面積より大きな（例え
ば約２倍）開孔面積をもつ、幅Ｗのサイズのフォトレジ
ストマスク３をフォトリソグラフィー工程により形成す
る。Next, as shown in FIG. 1 (b), for example, a phosphor silicate glass (PSG) or borophospho silicate glass (BPSG) film is formed at, for example, about 10,000 °, and then, at a predetermined position, the contact area is larger than the contact area (for example, about (2 times) A photoresist mask 3 having a hole area and a width W is formed by a photolithography process.
次に、第１図（ｃ）に示すように絶縁膜２を約半分の
深さ（例えば約5000Å）までRIE法等のドライエッチン
グ技術を用いて異方性エッチングを行って開孔４を形成
し、そしてフォトレジストマスク３を除去したのち、低
濃度のシリコンを主成分とする溶液（スピン・オン ガ
ラス,SOG）を全面に例えば約2000Åの膜厚で回転塗布
し、かつ、これを200〜400℃の熱処理を加え焼成する。
この工程により開孔４の底部・コーナー部分に選択的に
塗布焼成膜であるSOG膜５が形成する。Next, as shown in FIG. 1C, the insulating film 2 is anisotropically etched to a depth of about half (for example, about 5000 °) using a dry etching technique such as the RIE method to form an opening 4. After the photoresist mask 3 is removed, a solution (spin-on-glass, SOG) containing low-concentration silicon as a main component is spin-coated on the entire surface to a thickness of, for example, about 2,000 mm, and this is applied to a thickness of 200 to 200 μm. Bake by applying a heat treatment at 400 ° C.
By this step, the SOG film 5 which is a coating and sintering film is selectively formed on the bottom and corner portions of the opening 4.
次に第１図（ｄ）に示すように、再びRIE法により絶
縁膜２とSOG膜５を同じエッチ速度で約5000ÅのBPSG膜
厚分全面エッチバック処理を施し、半導体基板上に幅Ｗ
よりも小さい幅Ｗ′の45〜60度のテーパー形状を有する
コンタクトホール６を形成し、導電性配線材料、例えば
アルミニウム層７をスパッタ蒸着法により形成し、電気
的に接続する。Next, as shown in FIG. 1 (d), the entire surface of the insulating film 2 and the SOG film 5 is etched back by the RIE method at the same etching rate for a BPSG film thickness of about 5000.degree.
A contact hole 6 having a smaller width W 'and a tapered shape of 45 to 60 degrees is formed, and a conductive wiring material, for example, an aluminum layer 7 is formed by a sputter deposition method and electrically connected.
本発明では、第１図（ｄ）に示す、全面エッチバック
する工程で、SOG膜は、半導体基板上の凹部には厚く、
凸部には薄く平坦化されるため、コンタクトホール以外
の平坦化処理を同時に行うことかできる。また本発明
は、層間絶縁膜２の形成、平坦化等400℃以下の低温で
行うことにより、アルミニウム多層配線形成工程へも適
用が可能である。In the present invention, in the step of etching back the entire surface shown in FIG. 1 (d), the SOG film is thick in the concave portion on the semiconductor substrate,
Since the protrusions are thinly flattened, the flattening process other than the contact holes can be performed simultaneously. Further, the present invention can be applied to an aluminum multilayer wiring forming step by performing the formation and planarization of the interlayer insulating film 2 at a low temperature of 400 ° C. or less.
（発明の効果） 以上のように本発明の製造方法によれば、加工寸法幅
Ｗよりも小さいＷ′のテーパー形状を有するコンタクト
ホールの形成を可能としたのでコンタクトホールエッジ
部や半導体基板上の凹凸部での配線層のステップカバレ
ージが改善され、コンタクトホールエッジ部、基板段差
部での配線抵抗の増大、断線等の問題や、配線パターン
形成時のエッチング残り等の問題がなくなり、したがっ
て、半導体装置の歩留りや信頼性の向上が期待できる。(Effects of the Invention) As described above, according to the manufacturing method of the present invention, it is possible to form a contact hole having a tapered shape of W 'smaller than the processing dimension width W. The step coverage of the wiring layer in the uneven portion is improved, and problems such as an increase in the wiring resistance at the contact hole edge portion, the step portion of the substrate, disconnection, etc., and problems such as remaining etching when forming a wiring pattern are eliminated. An improvement in the yield and reliability of the device can be expected.
第１図は本発明の方法の実施例を示す概略的工程図であ
る。 １……半導体基板、２……層間絶縁膜、３……フォトレ
ジストマスク、４……コンタクトホール、５……SOG
膜、６……コンタクトホール、７……アルミニウム配線
層。FIG. 1 is a schematic flow chart showing an embodiment of the method of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Interlayer insulating film, 3 ... Photoresist mask, 4 ... Contact hole, 5 ... SOG
Film 6, contact hole 7, aluminum wiring layer.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−257822（ＪＰ，Ａ) 特開 平３−126219（ＪＰ，Ａ) 特開 昭64−39040（ＪＰ，Ａ) 特開 昭63−261837（ＪＰ，Ａ) 特開 昭61−226926（ＪＰ，Ａ) 特開 昭57−15423（ＪＰ，Ａ) 特開 昭61−283119（ＪＰ，Ａ) 特開 昭52−69274（ＪＰ，Ａ) 特開 平２−185024（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/28 H01L 21/768 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-257822 (JP, A) JP-A-3-126219 (JP, A) JP-A-64-39040 (JP, A) JP-A-63-63 261837 (JP, A) JP-A-61-226926 (JP, A) JP-A-57-15423 (JP, A) JP-A-61-283119 (JP, A) JP-A-52-69274 (JP, A) JP-A-2-185024 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/28 H01L 21/768
Claims (2)
工程と、 前記絶縁膜上に所定の幅の開孔パターンを有するフォト
レジストマスクを形成する工程と、 前記開孔パターンに露出した前記絶縁膜に対して異方性
エッチングを施すことにより、前記所定の幅に応じた凹
部を形成する工程と、 前記フォトレジストマスクを除去した後、前記凹部の側
壁に塗布焼成膜を形成する工程と、 前記半導体基板の表面が露出するまで、前記塗布焼成膜
及び前記絶縁膜に対して異方性エッチングを施す工程
と、 を含むことを特徴とする半導体装置のコンタクトホール
形成方法。A step of forming an insulating film on the main surface of the semiconductor substrate; a step of forming a photoresist mask having an opening pattern of a predetermined width on the insulating film; Forming a concave portion corresponding to the predetermined width by performing anisotropic etching on the insulating film; and forming a coated and fired film on a side wall of the concave portion after removing the photoresist mask. And a step of performing anisotropic etching on the applied and fired film and the insulating film until a surface of the semiconductor substrate is exposed.
溶液からなる膜であることを特徴とする請求項１記載の
半導体装置のコンタクトホール形成方法。2. The method for forming a contact hole in a semiconductor device according to claim 1, wherein said applied and fired film is a film made of a solution containing silicon as a main component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2293695A JP3033839B2 (en) | 1990-11-01 | 1990-11-01 | Method for forming contact hole in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2293695A JP3033839B2 (en) | 1990-11-01 | 1990-11-01 | Method for forming contact hole in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04168723A JPH04168723A (en) | 1992-06-16 |
| JP3033839B2 true JP3033839B2 (en) | 2000-04-17 |
Family
ID=17798044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2293695A Expired - Fee Related JP3033839B2 (en) | 1990-11-01 | 1990-11-01 | Method for forming contact hole in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033839B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2630542B2 (en) * | 1992-12-21 | 1997-07-16 | 日本プレシジョン・サーキッツ株式会社 | Method for manufacturing semiconductor device |
| US5567270A (en) * | 1995-10-16 | 1996-10-22 | Winbond Electronics Corp. | Process of forming contacts and vias having tapered sidewall |
-
1990
- 1990-11-01 JP JP2293695A patent/JP3033839B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04168723A (en) | 1992-06-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |