JPH04280455A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04280455A JPH04280455A JP4339191A JP4339191A JPH04280455A JP H04280455 A JPH04280455 A JP H04280455A JP 4339191 A JP4339191 A JP 4339191A JP 4339191 A JP4339191 A JP 4339191A JP H04280455 A JPH04280455 A JP H04280455A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- contact
- semiconductor
- contact pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000009429 electrical wiring Methods 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 9
- 239000000956 alloy Substances 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910000676 Si alloy Inorganic materials 0.000 description 9
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C38/00—Ferrous alloys, e.g. steel alloys
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Rolling Contact Bearings (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、特にアスペクト比の高
い半導体素子が形成されている半導体基板を用いる場合
に効果的な、優れた導電接続特性を有する半導体装置の
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having excellent conductive connection characteristics, which is particularly effective when using a semiconductor substrate on which a semiconductor element with a high aspect ratio is formed.
【０００２】0002
【従来の技術】図２（ａ） は従来の半導体装置の断面
を例示したもので、その製造方法の１例を説明すると、
半導体素子の形成されたシリコン基板１１上に絶縁膜１
２を形成した後、この絶縁膜上にフォトリソグラフ工程
によってレジスト膜を堆積し、このレジスト膜をマスク
としてエッチングによってコンタクト孔１３を形成した
後にレジスト膜を除去する。2. Description of the Related Art FIG. 2(a) shows a cross section of a conventional semiconductor device, and an example of its manufacturing method is as follows.
An insulating film 1 is formed on a silicon substrate 11 on which a semiconductor element is formed.
After forming 2, a resist film is deposited on this insulating film by a photolithography process, a contact hole 13 is formed by etching using this resist film as a mask, and then the resist film is removed.
【０００３】なお、本願の明細書において「半導体基板
」あるいは「シリコン基板」とは、シリコン基盤などの
半導体基盤に半導体素子を形成した状態、あるいは半導
体素子が形成された半導体基板上に絶縁膜などを堆積し
た状態などの、製造過程の状態ある半導体装置をいう。[0003] In the specification of this application, the term "semiconductor substrate" or "silicon substrate" refers to a state in which a semiconductor element is formed on a semiconductor substrate such as a silicon substrate, or a state in which an insulating film or the like is formed on a semiconductor substrate on which a semiconductor element is formed. Refers to a semiconductor device that is in the manufacturing process state, such as the state in which it has been deposited.
【０００４】次に、例えばアルミ−シリコン合金膜を導
電性膜１４としてスパッタ法により堆積するが、このと
きコンタクト孔１３内にもこのアルミ−シリコン合金膜
が堆積することを利用し、熱処理によってこのアルミ−
シリコン合金膜を介して導電性膜１４と前記シリコン基
板１１上の半導体素子との電気的接続を行う。[0004] Next, for example, an aluminum-silicon alloy film is deposited as the conductive film 14 by sputtering, but at this time, taking advantage of the fact that this aluminum-silicon alloy film is also deposited inside the contact hole 13, this film is heated by heat treatment. Aluminum
Electrical connection is made between the conductive film 14 and the semiconductor element on the silicon substrate 11 via the silicon alloy film.
【０００５】その後、上記導電性膜１４上にフォトリソ
グラフ工程によりレジスト膜を塗布して、このレジスト
膜をマスクとして導電性膜１４をエッチングして不必要
な部を除去してから上記レジスト膜を除去することによ
り所要の配線パターンを有する導電性膜を形成する。[0005] After that, a resist film is applied on the conductive film 14 by a photolithography process, and the conductive film 14 is etched using the resist film as a mask to remove unnecessary portions, and then the resist film is removed. By removing it, a conductive film having a desired wiring pattern is formed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、半導体
装置の微細化に伴って配線の段差（アスベクト比）が著
しく増加しており、コンタクト孔１３内に堆積するアル
ミ−シリコン合金膜の量が充分でないために図２（ａ）
に１５で示したように薄肉な部分が生じて抵抗が増加
することがあり、これが著しいときには図２（ｂ） に
１６で示したようにアルミ−シリコン合金膜が切れてし
まって半導体素子への電気的な接続が行われないことが
あった。[Problems to be Solved by the Invention] However, with the miniaturization of semiconductor devices, the level difference (aspect ratio) of wiring has increased significantly, and the amount of aluminum-silicon alloy film deposited in the contact hole 13 is not sufficient. For Figure 2(a)
As shown at 15 in Figure 2(b), a thin part may occur and the resistance may increase, and if this is significant, the aluminum-silicon alloy film may break as shown at 16 in Figure 2(b), causing damage to the semiconductor element. Electrical connections were sometimes not made.
【０００７】この問題を解決するための従来の方法とし
ては、コンタクト孔形成時にコンタクト孔上部を等方性
エッチングにより削るラウンドエッチングやコンタクト
孔に金属性のサイドウォールを形成するなどの手段が検
討されているが、いずれの方法においてもコンタクト孔
内の導電材料は絶縁層上部の導電性膜の堆積と同時に形
成されるものであるから、アルミシリコン合金などの導
電材料のステップカバリッジ（埋め込み性）の限界によ
って微細化の限界が左右されるので、今後の微細化によ
るアスペクト比の増大を考慮すれば不充分である。Conventional methods to solve this problem include round etching in which the upper part of the contact hole is removed by isotropic etching when forming the contact hole, and measures such as forming a metal sidewall in the contact hole. However, in either method, the conductive material in the contact hole is formed simultaneously with the deposition of the conductive film on the top of the insulating layer, so step coverage (embedding) of the conductive material such as aluminum silicon alloy is required. Since the limit of miniaturization is influenced by the limit of , it is insufficient to consider the increase in aspect ratio due to future miniaturization.
【０００８】また、コンタクト孔内に選択的にタングス
テンなどの金属を堆積する方法も検討されているが、金
属の選択的堆積反応の制御が難しいことなどから選択性
のある金属の成膜技術を開発する必要がある。[0008]Also, a method of selectively depositing a metal such as tungsten in the contact hole is being considered, but it is difficult to control the selective deposition reaction of the metal, so it is difficult to use selective metal film formation technology. need to be developed.
【０００９】本発明は、今後さらに微細化することが予
想されている半導体装置におけるコンタクト孔のアスペ
クト比の増大にも適用でき、現用されている合金堆積技
術を用いて実施可能な、コンタクト孔内における合金膜
の断線や薄膜化によるコンタクト抵抗の増大を生ぜずに
半導体素子と配線層との導電接続を得るようにした半導
体装置の製造方法を提供することを目的とする。The present invention can also be applied to increasing the aspect ratio of contact holes in semiconductor devices, which are expected to become even smaller in the future. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain a conductive connection between a semiconductor element and a wiring layer without causing an increase in contact resistance due to disconnection or thinning of the alloy film.
【００１０】0010
【課題を解決するための手段】半導体素子が形成された
半導体基板上に導電性膜を設ける工程と、マスクを用い
たエッチングによってコンタクトを形成すべき部分に残
された上記導電性膜によってコンタクトパッドを形成す
る工程と、このコンタクトパッドの一部が露出した状態
で絶縁膜を設ける工程と、このコンタクトパッドに電気
的な配線を行う工程とを行うようにした。[Means for Solving the Problem] Contact pads are formed by forming a conductive film on a semiconductor substrate on which a semiconductor element is formed, and by etching the conductive film left in the area where a contact is to be formed by etching using a mask. A step of forming an insulating film with a part of this contact pad exposed, and a step of providing electrical wiring to this contact pad are performed.
【００１１】[0011]
【作用】上記した本発明による半導体装置の製造方法に
おいては、コンタクト孔内の導電要素となる金属素子を
、シリコン基板と導電性膜との間の絶縁膜形成前にこの
導電性膜の形成とは独立に形成することによって、前記
課題を解決するようにした。[Function] In the method for manufacturing a semiconductor device according to the present invention described above, a metal element serving as a conductive element in a contact hole is formed before forming an insulating film between a silicon substrate and a conductive film. The above-mentioned problem was solved by forming the two independently.
【００１２】これによって、微細化にともなうコンタク
ト孔のアスペクト比の増大があっても断線や薄膜化によ
るコンタクト抵抗の増大を生じることなく、例えばアル
ミ−シリコン合金についてのような従来の合金堆積技術
を用いて、コンタクト孔内の導電接続を達成することが
できるばかりでなく、さらにゲートポリシリコンとシリ
コン基板との間などの表面に大きな段差を持つ半導体素
子についてもその表面の平坦化を実現し得るので、半導
体装置の歩留まりを高めることができる。[0012] As a result, even if the aspect ratio of the contact hole increases due to miniaturization, there is no increase in contact resistance due to disconnection or thinning of the film, and conventional alloy deposition techniques such as those for aluminum-silicon alloys can be used. By using this method, it is possible not only to achieve conductive connection within the contact hole, but also to flatten the surface of semiconductor devices that have a large step on the surface, such as between a gate polysilicon and a silicon substrate. Therefore, the yield of semiconductor devices can be increased.
【００１３】[0013]
【実施例】図１は本発明の一実施例における半導体装置
の製造工程を順次模式的に示したもので、先ず、半導体
素子が形成されたシリコン基盤１上にアルミシリコン合
金膜をスパッタリング法により堆積してから熱処理を行
ってこの合金膜とシリコン基盤１との電気的導通を改善
した後、フォトリソ工程によりレジスト膜３を形成し異
方性エッチングにより不要な部分の合金膜を除去して半
導体素子への導電接続が必要な部分に図１（ａ） に示
すようなコンタクトパッド２を形成する。[Embodiment] FIG. 1 schematically shows the manufacturing process of a semiconductor device according to an embodiment of the present invention. First, an aluminum-silicon alloy film is formed by sputtering on a silicon substrate 1 on which a semiconductor element is formed. After the alloy film is deposited and heat-treated to improve electrical conduction between the alloy film and the silicon substrate 1, a resist film 3 is formed by a photolithography process, and unnecessary parts of the alloy film are removed by anisotropic etching to form a semiconductor. Contact pads 2 as shown in FIG. 1(a) are formed in areas where conductive connections to the elements are required.
【００１４】次に、上記レジスト膜３を除去した後、同
図（ｂ） に示すように、コンタクトパツド２の一部が
露出した前記シリコン基板１上にＰ−ＣＶＤ法によりＳ
ｉＯ２膜４を２，０００ Å堆積し、さらに、例えばシ
リカフィルムやメトキシ系のシラノールなどをエタノー
ルなどのアルコール溶媒に溶かした滴下材料を滴下しな
がらスピンコーティングすることによって、このＳｉＯ
２膜４上にＳＯＧ（ｓｐｉｎ ｏｎ ｇｌａｓｓ） 膜
５を５，０００ Å堆積してから、窒素雰囲気下４２０
℃で熱処理を行う。Next, after removing the resist film 3, as shown in FIG. 3(b), S is deposited on the silicon substrate 1 with a part of the contact pad 2 exposed by the P-CVD method.
The iO2 film 4 is deposited to a thickness of 2,000 Å, and this SiO
After depositing a SOG (spin on glass) film 5 to a thickness of 5,000 Å on the 2 film 4, it was deposited for 420 Å in a nitrogen atmosphere.
Perform heat treatment at ℃.
【００１５】次いで、異方性エッチングによってこのＳ
ＯＧ膜５をエッチバックすることによって、同図（ｃ）
に示すように、ＳＯＧ膜５’による半導体基板の平坦
化を行った後に、Ｐ−ＣＶＤ法によりＳｉＯ２膜を ３
，０００Å堆積してから、このＳｉＯ２膜を異方性エッ
チングによりエッチバックして、同図（ｄ） に示すよ
うに層間絶縁膜６を形成するとともに前記コンタクトパ
ッド２の一部が露出するようにする。Next, this S is removed by anisotropic etching.
By etching back the OG film 5, as shown in FIG.
As shown in Figure 3, after planarizing the semiconductor substrate with the SOG film 5', a SiO2 film is formed using the P-CVD method.
, 000 Å is deposited, and then this SiO2 film is etched back by anisotropic etching to form an interlayer insulating film 6 and expose a part of the contact pad 2, as shown in FIG. do.
【００１６】しかる後、同図（ｅ） に示したように、
上記コンタクトパッド２の一部が露出した層間絶縁膜６
上にアルミ−シリコン合金膜７を堆積してから熱処理を
行なうことによってシリコン基板１とこの合金膜７との
間の導通を確保し、その後、この合金膜７上にフォトリ
ソ工程によりレジスト膜８を形成してから異方性エッチ
ングを行うことによって所要の配線パターンを有する導
電性膜７’を作成した後、このレジスト膜８を除去する
ことによって、同図（ｆ） に示すような半導体装置が
得られる。After that, as shown in the same figure (e),
Interlayer insulating film 6 where a part of the contact pad 2 is exposed
Conductivity between the silicon substrate 1 and this alloy film 7 is ensured by depositing an aluminum-silicon alloy film 7 on top and performing heat treatment, and then a resist film 8 is formed on this alloy film 7 by a photolithography process. After forming a conductive film 7' having a desired wiring pattern by anisotropic etching, the resist film 8 is removed to form a semiconductor device as shown in FIG. can get.
【００１７】[0017]
【発明の効果】以上説明したように、本発明によれば、
既存の導電性膜および絶縁膜の形成技術を用いながら、
予め設けられたコンタクト孔に依存することなく任意の
大きさのコンタクトパッドを形成することができるので
、断線や薄膜化によるコンタクト抵抗の増大を生じる事
なく、また、大きなアスペクト比を有するコンタクトも
容易に作成することができるため、半導体装置の微細化
が容易になるばかりではなく、半導体装置製造時の歩留
まりをも向上させることができるという格別の効果が達
成される。[Effects of the Invention] As explained above, according to the present invention,
While using existing conductive film and insulating film formation technology,
Since contact pads of any size can be formed without relying on pre-prepared contact holes, there is no increase in contact resistance due to disconnection or thinning of the film, and contacts with large aspect ratios can also be easily formed. As a result, it is possible to achieve the special effect of not only facilitating the miniaturization of semiconductor devices but also improving the yield during manufacturing of semiconductor devices.
【図１】本発明による半導体装置の製造工程の一実施例
を示すための半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device for illustrating an embodiment of a semiconductor device manufacturing process according to the present invention.
【図２】従来の半導体装置を説明するための断面図であ
る。
１ 半導体基板（シリコン基板）２
コンタクトパッド
３，８ レジスト
４，６ ＳｉＯ２膜
５，５’ ＳＯＧ膜
７ 導電性膜FIG. 2 is a cross-sectional view for explaining a conventional semiconductor device. 1 Semiconductor substrate (silicon substrate) 2
Contact pads 3, 8 Resist 4, 6 SiO2 film 5, 5' SOG film 7 Conductive film
Claims (1)
に導電性膜を設ける工程と、マスクを用いたエッチング
によってコンタクトを形成すべき部分に残された上記導
電性膜によってコンタクトパッドを形成する工程と、こ
のコンタクトパッドの一部が露出した状態で絶縁膜を設
ける工程と、このコンタクトパッドに電気的な配線を行
う工程とを含むことを特徴とする半導体装置の製造方法
。1. A step of providing a conductive film on a semiconductor substrate on which a semiconductor element is formed, and a step of forming a contact pad using the conductive film left in a portion where a contact is to be formed by etching using a mask. A method for manufacturing a semiconductor device, comprising: a step of providing an insulating film with a portion of the contact pad exposed; and a step of providing electrical wiring to the contact pad.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4339191A JPH04280455A (en) | 1991-03-08 | 1991-03-08 | Manufacture of semiconductor device |
| GB9204975A GB2256201B (en) | 1991-03-08 | 1992-03-06 | Rolling part steel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4339191A JPH04280455A (en) | 1991-03-08 | 1991-03-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04280455A true JPH04280455A (en) | 1992-10-06 |
Family
ID=12662497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4339191A Pending JPH04280455A (en) | 1991-03-08 | 1991-03-08 | Manufacture of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH04280455A (en) |
| GB (1) | GB2256201B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3338761B2 (en) * | 1996-02-29 | 2002-10-28 | 川崎製鉄株式会社 | Bearing material |
| WO2013077328A1 (en) * | 2011-11-21 | 2013-05-30 | 株式会社神戸製鋼所 | Paste for inhibiting fatigue crack growth |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5831560A (en) * | 1981-08-19 | 1983-02-24 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5848438A (en) * | 1981-09-17 | 1983-03-22 | Nec Corp | Semiconductor integrated circuit device |
| JPS61116834A (en) * | 1984-08-31 | 1986-06-04 | テキサス インスツルメンツ インコ−ポレイテツド | Formation of contact on semiconductor substrate |
| JPH03270168A (en) * | 1990-03-20 | 1991-12-02 | Fujitsu Ltd | Semiconductor device and its manufacture |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4042381A (en) * | 1976-07-06 | 1977-08-16 | Republic Steel Corporation | Control of inclusion morphology in steel |
| JPS54126622A (en) * | 1978-03-27 | 1979-10-02 | Daido Steel Co Ltd | Freeecutting steel for high performance gear and method of making same |
| JPS5585658A (en) * | 1978-12-25 | 1980-06-27 | Daido Steel Co Ltd | Free cutting steel |
| US4255188A (en) * | 1979-08-29 | 1981-03-10 | Inland Steel Company | Free machining steel with bismuth and manganese sulfide |
| US4806304A (en) * | 1983-05-09 | 1989-02-21 | Daido Tokushuko Kabushiki Kaisha | Free cutting steel |
-
1991
- 1991-03-08 JP JP4339191A patent/JPH04280455A/en active Pending
-
1992
- 1992-03-06 GB GB9204975A patent/GB2256201B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5831560A (en) * | 1981-08-19 | 1983-02-24 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5848438A (en) * | 1981-09-17 | 1983-03-22 | Nec Corp | Semiconductor integrated circuit device |
| JPS61116834A (en) * | 1984-08-31 | 1986-06-04 | テキサス インスツルメンツ インコ−ポレイテツド | Formation of contact on semiconductor substrate |
| JPH03270168A (en) * | 1990-03-20 | 1991-12-02 | Fujitsu Ltd | Semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9204975D0 (en) | 1992-04-22 |
| GB2256201B (en) | 1995-01-04 |
| GB2256201A (en) | 1992-12-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
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