JPS5848438A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive improvement of humidity resistance property of the titled device by a method wherein a conductive layer, which is buried in an insulating layer in such a manner that the layer comes in contact with a reverse conductive region, is provided with its upper end positioned on the same level or above of the upper surface of the insulating layer in the constitution wherein the conductive layer is connected to a wiring layer. CONSTITUTION:The second insulating layer is formed by depositing a phosphor glass layer 34 containing low density of phosphorus in such a manner that the thickness of which will be in excess of that of a polycrystalline silicon layer 34. Then, photoresist 35 is applied in the thickness which exceeds that of the phosphur glass layer 34. The upper surface 36 of said photoresist layer 35 can be made close to a single plane by selecting a proper photoresist. Through these procedures, the structure wherein said conductive layers 32 and 33 are buried in the phosphorus glass layer 34, which is the second insulating layer, can be obtained. The upper ends 37 and 38 of the conductor layers 32 and 33 are made in such a structure that they are positioned on the same plane or upper of the surface 39 of the phosphorus glass layer, which is the second insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and in particular to a connection portion between elements in a semiconductor integrated circuit device with an i-edge gate recovery effect. A typical method for connecting elements in an insulated gate lid field effect semiconductor (hereinafter referred to as MOS type) integrated circuit device is to increase the length of an interlayer insulating film and to make holes in the interlayer insulating film. “The metal wiring layer is then produced.

The conventional structure and manufacturing method for the apertures in each case are shown below. First, as shown in IWJ (a), a phosphor glass layer 2 is grown on a semiconductor substrate l by a vapor phase method. One edge portion 3, 4 is formed on the phosphor glass layer 2 using an etching technique.
-0 and high temperature heat treatment in an inert atmosphere, for example heat treatment in a high temperature nitrogen atmosphere t
- As shown in the first WJ (b), the phosphor glass layer of the edge portions ``3, 4'' is fixed by standing the edge portion ``6'' with a gentle slope. An opening 8 having a diameter of 7 is then obtained by depositing an aluminum layer 9 using an E-gun method to obtain the structure shown in FIG. 1(b).

However, in order to obtain sufficient coverage of the aluminum wiring layer 9' in the opening BIC, it is necessary to form the edge portions 6 and 7 with a sufficiently gentle slope. Therefore, it is necessary to use a phosphorus glass layer with a high phosphorus content as the phosphorus glass layer 2. However, when a silicon dioxide IC layer with a high phosphorus content is used as the phosphorus glass layer 2, phosphorus oxidation occurs when moisture enters from the outside of the device, which causes corrosion of the aluminum layer, causing problems in terms of moisture resistance. .

In order to avoid these eight problems, the phosphorus glass layer has a low phosphorus content. Alternatively, it is desirable to use silicon dioxide which does not contain phosphorus. However, as mentioned above, if a silicon dioxide layer with a low phosphorus concentration is used as the insulating film between the eyebrows,
As shown in FIG. 1(c), the edge 1 of the phosphor glass layer 2
Since 70- at 0 and 11 is insufficient, the edge portion 10.
11 upper end 12.13 and said edge slo, lower end 1 of 11
There was a drawback that the aluminum wiring 1Ii1 layer 9 broke at 4°15.

The present invention aims to solve this structural drawback.

The features of the present invention include a - conductivity type semiconductor substrate, an opposite conductivity type region formed on the semiconductor substrate, an insulating layer deposited on the semiconductor substrate, and a wiring deposited on the insulating layer. In a semiconductor integrated circuit device comprising a layer, in order to make contact between the wiring layer and the region of the opposite conductivity type, the wiring layer is buried in the insulating layer and is formed in contact with the region of the opposite conductivity type. A semiconductor integrated circuit device having a structure in which a conductive layer is provided, an upper end of the conductive layer is located on the same plane as or above the upper surface of the insulating layer, and an upper end of the conductive layer is connected to the wiring layer. be.

Next, the structure of the present invention will be explained with reference to Kj12m. A conductive layer is connected to the semiconductor substrate 16 on the semiconductor substrate 16 and the conductive region 41 into which a pure substance of the opposite conductivity is introduced through the opening 17, and is buried in the insulating layer 1B grown on the semiconductor substrate 16. It has 19. The upper end 20 of the conductive layer 19 is located on the same plane as or above the upper end 21 of the insulating layer 18, and the upper end 20 of the conductive layer 19O is connected to the wiring layer 22.

Structurally, there is no need to provide an opening in the insulating layer 18,
Therefore, a silicon dioxide layer with a low phosphorus concentration can be used as the material for the insulating layer, and sufficient moisture resistance can be obtained.
becomes.

Furthermore, according to the present invention, a contact material between elements is formed in the pU conductive layer 19.
And groan wiring layer 2? Shu Tong (to do it, traditionally.

7 of the phosphorus glass layer at the edge M3.4 of the ljH opening (Fig. 1(a)), which was indispensable.
0- becomes unnecessary. Therefore, since high-temperature heat treatment is not required, there is no need to consider structurally the coverage of the wiring layer 22. ~below,#! Figure 3 (a) to (d)
Accordingly, one embodiment of the present invention will be described. In this example, MO8g
The present invention is applied to an O8-path device, and the cross-sectional view in the direction A of the plan view shown in FIG. 4 corresponds to FIG. 3 (Φ). 23, an insulating isolation region 24 of an NO8 type electrophoresis effect transistor is formed by a selective fermentation method using a silicon nitride layer as a mask.Then, the mask silicon nitride layer is removed and the semiconductor substrate 23 is exposed to high temperature oxygen! Then, a thin gate insulating film is formed by thermal oxidation.Next, a polycrystalline silicon layer constituting the gate electrode is grown by a vapor phase method.

After impurities are introduced into the polycrystalline silicon layer by diffusion at high temperature, a gate electrode 25 of a rainbow 08 type field effect transistor is formed using a photolithography technique. Next, the silicon dioxide film serving as the gate insulating film is removed from the entire surface using an HF-based chemical. Further oxidation forms a thin first silicon dioxide layer 46, 27 around the gate electrode and on the exposed surface of the semiconductor substrate. After ±, impurity doping by sulfur implantation (1M08 type electric
The source and drain regions 28 of the field effect transistor are formed. The impurities introduced by the ion implantation are of a conductivity type opposite to those introduced into the semiconductor substrate. In order to activate the impurities, heat treatment is performed in a high humidity phosphorus atmosphere. Through the above steps, the gate electrode 25 and source/drain regions 28 of the MO8 type 1% conductive transistor were formed. Next, using the photo-etching technique, the silicon dioxide layer 2 is
6. Form an opening 29.30 at a desired location on 27.

Thereafter, a polycrystalline silicon layer 31 for forming a conductive layer is deposited over the entire surface by a vapor phase method. The film thickness is selected so that the height at the lowest saddle portion of the surface 420 of the polycrystalline silicon layer 310 exceeds the height at which the gate 25 of the MO8 field effect transistor formed on the semiconductor substrate 23 is located. In order to obtain appropriate conductivity, impurities are introduced into the polycrystalline silicon layer 31 for forming the conductive layer by thermal diffusion. Next, as shown in FIG. 3b, a polycrystalline silicon layer 3 for forming the conductive layer is formed using a photolithography technique.
1- is separated into suitable columnar conductive regions F2, 33 that completely cover the openings 29, 30 made on the first silicon dioxide layer 26, 27 to form a conductive layer. The etching method is a black directional reactive sputter etching technique. Thereafter, as shown in FIG. 3c, a phosphorus glass layer 34 containing a low concentration of phosphorus is deposited as a second insulating layer.

The film thickness is selected so as to exceed the thickness of the polycrystalline silicon layer 34.

Further, the photoresist layer 35 is applied to the phosphorus glass layer 34.
Apply to a thickness greater than . By selecting an appropriate photoresist F, the upper surface 36 of the photoresist layer 35 can be
can have a shape close to a single plane. Next, the entire surface is etched using a non-directional reactive sputter etching technique in which conditions are set so that the etching rates of the photoresist layer 35 and the phosphor glass layer are approximately the same. After the above steps, the conductive layer 32, 33
is buried in the phosphorus glass layer 34 which is the second insulating layer. The upper end 37.38 of the conductive layer 32.33 is connected to the surface 39 of the phosphor glass layer 34 which is the insulating layer of the jl12.
The structure is located on the same plane or above.

As the etching method after coating the photoresist layer 35, it is also preferable to use ion silling, which is an anisotropic etching method in which the etching rate is less dependent on the material to be etched.

Furthermore, a wiring layer of 4° was formed on the surface using aluminum vapor deposition technology using an E-gun and photolithography.

(Fig. jI31(d)) By applying the structure related to the connection between elements realized using the above manufacturing method to an MO8 type integrated circuit device, etc., the phosphor glass layer which is the second insulating layer It is possible to achieve a lower phosphorus temperature of 34 degrees, and it is possible to improve moisture resistance. Furthermore, Fig. 1(a), which cannot be avoided structurally in the past,
The consideration given to the coverage of the aluminum wiring layer 9 at the portion of the gate 5 provided in the phosphor glass layer 2 has considerable effects, such as making it suitable for armor.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) show the conventional structure and manufacturing method for the connecting part between elements, and FIG. 2 shows the structure and edge s of the connecting part between elements according to the present invention. -(d) show the structure and implementation method when the present invention is applied to an MO8 type integrated circuit device, and FIG. 4 is a plan view corresponding to FIG. 3(d). In the figure, 1 is the semiconductor substrate, 2 is the phosphor glass layer, 3° 4 is the opening made in the phosphor glass layer 2, the flame edge of the hole, 5 is the opening made in the phosphor glass layer 2, and 6.7 is the slope. 8 is an aperture with an edge 6°7; 9 is an aluminum layer; 10.11 is an edge of an aperture with a steep slope; 12. 13 is the upper end of the edge parts 10 and 11, 14 and 15 are the lower ends of the edge parts 10 and 11, 16 is a semiconductor substrate, 17 is an expanded hole, 18 is an insulating layer, and 19 is a conductive layer buried in the insulating layer 18. 20 is the upper end of the conductive layer 19; 21 is the upper end of the insulating layer 18;
22 is a wiring layer, 23 is a semiconductor substrate, 24 is an insulation isolation region of an MO8 field effect transistor, 25 is a polycrystalline silicon gate electrode of an MO8 field effect transistor, 26.27 is a thermally cured film, and 28 is an insulation layer of an MO8 field effect transistor. Impurity introduced regions forming sources and drains, 29.30 are openings made in the thermal oxide films 26 and 27, 31 is a polycrystalline silicon layer deposited to form a conductive layer, 32.33 is polycrystalline silicon. 34 is a phosphor glass layer which is a second insulating layer, 35 is a photoresist layer, 36 is the upper surface of the photoresist layer 35, 37° 38 is a conductive layer 32.33
39 is the surface of the phosphorus glass layer 34; 40 is the aluminum layer as a wiring layer; 41 is a conductive region doped with an impurity of the opposite conductivity type to that of the semiconductor substrate 16; 42 is the surface of the polycrystalline silicon layer 31; , respectively. jPtI! 1 ((1) ′(b) (C) ? ~ Fist, Figure #3

Claims (1)

[Claims] It includes a semiconductor substrate of one conductivity type, a region of the opposite conductivity type formed on the semiconductor substrate, an insulating layer completely deposited on the semiconductor substrate, and a wiring layer deposited on the insulating layer. In a semiconductor integrated circuit device comprising: A base is provided with a conductive layer, the upper end of the conductive layer is located on the same plane as or above the upper surface of the insulating layer, and the upper end of the conductive layer is connected to the wiring layer. This is a patented "Cow*Body Integrated" circuit device that has a structure that
Pa, =