WO2024053695A1 - Light detection device - Google Patents

Light detection device Download PDF

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Publication number
WO2024053695A1
WO2024053695A1 PCT/JP2023/032601 JP2023032601W WO2024053695A1 WO 2024053695 A1 WO2024053695 A1 WO 2024053695A1 JP 2023032601 W JP2023032601 W JP 2023032601W WO 2024053695 A1 WO2024053695 A1 WO 2024053695A1
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WO
WIPO (PCT)
Prior art keywords
chip
layer
photodetection device
seam
buried layer
Prior art date
Application number
PCT/JP2023/032601
Other languages
French (fr)
Japanese (ja)
Inventor
巧 小野寺
貴弘 亀井
明久 坂本
勝哉 秋山
直樹 小川
徹 大迫
義之 石井
弘康 松谷
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024053695A1 publication Critical patent/WO2024053695A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present disclosure relates to a photodetection device.
  • Patent Document 1 discloses a technique for suppressing communication of the seam portions to the outside by making the seam portions of two stacked layers discontinuous.
  • photodetection device that has a structure in which a layer is provided so as to cover a chip provided on a substrate containing a photodetection element. Seams may occur due to the step provided by the chip. There is still room to consider ways to suppress communication of the seam portion to the outside.
  • One aspect of the present disclosure suppresses communication of the seam portion to the outside.
  • a photodetection device includes a substrate including a photodetection element, a chip provided to the substrate, an embedded layer provided to cover the chip, and a photodetector generated in the embedded layer. It includes a seam portion extending to the surface of the layer, and a sealing layer provided so as to cover the buried layer and the seam portion.
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a first embodiment.
  • FIG. 3 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a second embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 4th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 5th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 6th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 6th embodiment.
  • FIG. 7 It is a figure showing an example of a schematic structure of a photodetection device concerning a 7th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning an 8th embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device.
  • FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example.
  • FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example.
  • FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example.
  • FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example.
  • FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example.
  • FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 2 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection section and an imaging section. It is a figure showing an example of a schematic structure of a photodetection device concerning a 9th embodiment.
  • FIG. 9 It is a figure showing an example of a schematic structure of a photodetection device concerning a 9th embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure showing a modification. It is a figure showing a modification.
  • FIG. 10 It is a figure showing an example of a schematic structure of a photodetection device concerning a 10th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 10th embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device.
  • FIG. 3 is a diagram showing an example of a schematic configuration of a sealing layer. It is a figure showing an example of a schematic structure of a photodetection device concerning a 13th embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device.
  • FIG. 3 is a diagram showing a first arrangement example of dummy chips.
  • FIG. 3 is a diagram showing a first arrangement example of dummy chips. It is a figure showing the effect of a dummy chip.
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer.
  • FIG. 7 is a diagram showing a second example of arrangement of dummy chips. It is a figure showing the effect of a dummy chip.
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer.
  • FIG. 7 is a diagram showing a third arrangement example of dummy chips. It is a figure showing the effect of a dummy chip.
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. It is a figure which shows the 4th example of arrangement
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. It is a figure which shows the 5th example of arrangement
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer.
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. It is a figure showing the effect of a dummy chip.
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. It is a figure which shows the 7th example of arrangement
  • FIG. 1 is a diagram showing an example of a schematic configuration of a wafer. It is a figure which shows the 5th example of arrangement
  • FIG. 2
  • FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. It is a figure showing a modification. It is a figure showing a modification. It is a figure showing a modification. It is a figure showing an example of a schematic structure of a photodetection device concerning a 16th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 17th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning an 18th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 19th embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 20th embodiment.
  • FIG. 7 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a twenty-first embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 22nd embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 23rd embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device.
  • FIG. 7 is a diagram showing an example of a schematic configuration of a photodetection device according to a twenty-fourth embodiment. It is a figure showing an example of a schematic structure of a photodetection device concerning a 24th embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device.
  • FIG. 3 is a diagram showing an example of CMP.
  • FIG. 3 is a diagram showing an example of CMP.
  • FIG. 25 It is a figure showing an example of a schematic structure of a photodetection device concerning a 25th embodiment. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device. It is a figure which shows the example of the manufacturing method of a photodetection device.
  • FIG. 1 is a diagram showing an example of a schematic configuration of a photodetection device according to a first embodiment.
  • a cross section of a photodetector 100 is schematically shown.
  • the photodetecting device 100 includes a substrate 1 , a chip 2 , a buried layer 3 , a seam portion 4 , a sealing layer 5 , an auxiliary layer 6 , and a support substrate 7 .
  • “layer” may be read as “film”, “member”, etc. as appropriate.
  • “provide” may be read as “form”, “arrange”, etc. as appropriate.
  • an XYZ coordinate system is also illustrated.
  • the Z-axis direction corresponds to the thickness direction of the substrate or layer.
  • the X-axis direction and the Y-axis direction correspond to the plane direction of the substrate or layer.
  • the substrate 1 and the support substrate 7 are opposed to each other. In this example, of the substrate 1 and the support substrate 7, the substrate 1 is located on the negative side of the Z-axis, and the support substrate 7 is located on the positive side of the Z-axis.
  • the chip 2 , the buried layer 3 , the seam 4 , the sealing layer 5 and the auxiliary layer 6 are located between the substrate 1 and the support substrate 7 .
  • the photodetector 100 includes a wiring layer. All wiring provided in the wiring layer is referred to as wiring L and illustrated. An example of the material of the wiring L is copper (Cu) or the like. Note that some vias connecting the wirings L in different wiring layers are also shown with the same hatching as the wirings L.
  • the substrate 1 is a semiconductor substrate such as a silicon (Si) semiconductor substrate, and includes a photodetector element 1p.
  • An example of the photodetection element is a photoelectric conversion element such as a PD (Photo Diode).
  • a plurality of photoelectric conversion elements arranged in an array in the XY plane direction may correspond to the photodetection element 1p.
  • the substrate 1 also includes circuit elements such as transistors for driving each photoelectric conversion element and extracting an electric signal according to the amount of light received by each photoelectric conversion element.
  • a circuit including such a circuit element is also referred to as a pixel circuit.
  • the illustrated photodetector 100 is a backside illumination type photodetector that detects light incident on the backside 1b of the substrate 1.
  • the substrate 1 has a wiring layer on the front surface 1a side.
  • the wiring L in the wiring layer of the substrate 1 may constitute a part of a pixel circuit.
  • the wiring layer of the illustrated substrate 1 is a multilayer wiring layer, and some wirings L are exposed on the surface 1a.
  • the chip 2 is provided on the substrate 1. Being provided on the substrate 1 may be understood to include not only being provided directly on the substrate 1, but also being provided via another element (for example, an additional substrate 12 in FIG. 21, which will be described later). In the example shown in FIG. 1, the chip 2 is provided directly on the substrate 1, more specifically on the surface 1a of the substrate 1.
  • the mounting surface of the chip 2 is shown as a mounting surface 2b.
  • the chip 2 has a wiring layer on the mounting surface 2b side.
  • the wiring layer of the illustrated chip 2 is a multilayer wiring layer, and some wirings L are exposed on the mounting surface 2b.
  • the chip 2 is provided on the substrate 1 so that the mounting surface 2b of the chip 2 is in contact with the surface 1a of the substrate 1. More specifically, the chip 2 is mounted on the substrate 1 such that the wiring L of the chip 2 and the wiring L of the substrate 1 are in contact with each other and electrically connected. Such a connection is also called a Cu--Cu bond or the like when the material of the wiring L is Cu.
  • the mounting surface 2b of the chip 2 and the surface 1a of the substrate 1 define a bonding surface between the chip 2 and the substrate 1 (chip bonding surface).
  • the chip 2 may be any chip (IC, etc.) that can be used in the photodetector 100.
  • An example of the chip 2 is a logic chip, which drives, for example, a transistor of a pixel circuit or processes an electric signal taken out from the pixel circuit.
  • Another example of the chip 2 is a memory chip, which stores, for example, data used in processing by a logic chip or data obtained by processing.
  • Yet another example of chip 2 is an AI (Artificial Intelligence) chip, which is specifically designed to perform high-speed arithmetic processing using a trained model (for example, a trained DNN (Deep Neural Network)). .
  • AI Artificial Intelligence
  • the chip 2 provided on the substrate 1 provides a step.
  • the chip 2 is a stepped portion having a convex shape protruding toward the positive direction of the Z-axis with respect to the surface 1a of the substrate 1 as a reference.
  • the number of chips 2 included in the photodetector 100 is not limited to the example shown in FIG. 1.
  • the photodetection device 100 may include any number of chips 2, one or more.
  • the buried layer 3 is provided so as to cover the chip 2, and more specifically, to cover the substrate 1 and the chip 2 in this example.
  • the buried layer 3 can function as a protective layer that protects the chip 2. For example, entry of moisture, chemicals, undesired gases, etc. into the chip 2 is suppressed.
  • Examples of the material of the buried layer 3 are SiN, SiO2 , etc.
  • the surface on the Z-axis positive direction side is referred to as a surface 3a and illustrated.
  • the surface on the negative side of the Z-axis is referred to as a back surface 3b in the drawing.
  • the seam portion 4 occurs within the buried layer 3 due to the step provided by the chip 2.
  • the seam portion 4 starts from, for example, the rising portion of the step or its surrounding portion, and extends to the surface 3a of the buried layer 3.
  • At least a portion of the seam portion 4 may be a void.
  • the void that the seam portion 4 has is shown as a void 4a.
  • the entire seam portion 4 is a void 4a.
  • a portion of the surface 3a of the buried layer 3 where the seam portion 4 is located is open.
  • the sealing layer 5 is provided so as to cover the buried layer 3 and the seam portion 4.
  • the opening formed in the surface 3a of the buried layer 3 by the seam portion 4 is also closed by the sealing layer 5.
  • the sealing layer 5 prevents the seam portion 4 from communicating with the outside.
  • the material of the sealing layer 5 may be the same as the material of the buried layer 3, or may be different. Some examples of materials for the sealing layer 5 will be described later.
  • the auxiliary layer 6 is provided to cover the sealing layer 5.
  • the auxiliary layer 6 includes, for example, a material suitable for bonding to the support substrate 7. Examples of materials for the auxiliary layer 6 are mainly SiOx (SiNx, SiON, SiCN, SiOC). Among the surfaces of the auxiliary layer 6, the surface on the Z-axis positive direction side is referred to as a surface 6a and illustrated.
  • the support substrate 7 is located on the opposite side of the substrate 1 with the sealing layer 5 in between, and supports the sealing layer 5 directly or indirectly.
  • the support substrate 7 may be, for example, a silicon (Si) semiconductor substrate. In the example shown in FIG. It is bonded to the auxiliary layer 6 so as to indirectly support 5).
  • a silicon (Si) semiconductor substrate In the example shown in FIG. It is bonded to the auxiliary layer 6 so as to indirectly support 5).
  • the surface on the negative side of the Z-axis is referred to as a back surface 7b.
  • the back surface 7b of the support substrate 7 and the front surface 6a of the auxiliary layer 6 define a bonding surface between the support substrate 7 and the auxiliary layer 6 (support substrate bonding surface).
  • the photodetecting device 100 may not include the auxiliary layer 6, and in that case, the support substrate 7 is bonded to the sealing layer 5 so
  • the sealing layer 5 that covers the embedded layer 3 and the seam portion 4
  • communication of the seam portion 4 to the outside can be suppressed.
  • the sealing layer 5 that covers the embedded layer 3 and the seam portion 4
  • FIG. 2 is a diagram showing an example of a schematic configuration of a photodetection device according to a second embodiment.
  • the sealing layer 5 includes an extension portion 5 a that extends into the seam portion 4 .
  • the extending portion 5a extends so as to fill at least a portion of the seam portion 4, and in the example shown in FIG. 2, extends so as to fill the entire seam portion 4.
  • the seam portion 4 does not have a void 4a (FIG. 1).
  • the material of the sealing layer 5 includes a low permeability material. Examples of low permeability materials include SiN-based materials. Examples of SiN-based materials are SiNx, SiCN, SiON, etc.
  • the material of the sealing layer 5 includes a low Young's modulus material.
  • low Young's modulus materials are low-k materials, organic materials, etc.
  • An example of a low-k material is porous SiO2, etc.
  • organic materials are silicones, siloxanes, polyimides, etc.
  • FIG. 3 is a diagram showing an example of a schematic configuration of a photodetection device according to a fourth embodiment.
  • the extending portion 5a of the sealing layer 5 extends so as to fill only a portion of the seam portion 4.
  • the remainder of the seam portion 4 is a void 4a. By leaving the void 4a, inter-chip stress can also be alleviated.
  • FIG. 4 is a diagram showing an example of a schematic configuration of a photodetection device according to a fifth embodiment.
  • Photodetection device 100 further includes a side wall portion 8 .
  • the side wall portion 8 is provided so as to cover the side surface (side wall) of the chip 2 .
  • the buried layer 3 is provided so as to cover the substrate 1 , the chip 2 , and the sidewall portion 8 .
  • An example of the material of the side wall portion 8 is an inorganic material. Examples of inorganic materials are mainly SiNx (SiOx, SiON, SiCN, SiOC).
  • FIGS. 5 and 6 are diagrams showing an example of a schematic configuration of a photodetecting device according to a sixth embodiment. Seam portions 4 caused by two different chips 2 are connected to each other. Among the two chips 2, the first chip is shown as a chip 2-1. The second chip is designated and illustrated as chip 2-2.
  • the seam portion 4 includes a seam portion 4-1 and a seam portion 4-2.
  • the seam portion 4-1 is a first seam portion caused by the chip 2-1.
  • the seam portion 4-2 is a second seam portion caused by the chip 2-2.
  • the seam portion 4-1 and the seam portion 4-2 are connected to each other on the way to the surface 3a of the buried layer 3, and extend to the surface 3a of the buried layer 3.
  • the step provided by the seam portion 4-1 and the seam portion 4-2 are connected to each other from the beginning and extend together to the surface 3a of the buried layer 3. For example, even if there are a seam portion 4-1 and a seam portion 4-2 that are connected to each other in this manner, communication between them to the outside can be suppressed.
  • FIG. 7 is a diagram showing an example of a schematic configuration of a photodetection device according to a seventh embodiment.
  • Photodetection device 100 further includes an additional layer 9 .
  • An additional layer 9 is provided between the substrate 1 and the chip 2 and the buried layer 3.
  • the additional layer 9 is provided so as to cover the substrate 1 and the chip 2
  • the buried layer 3 is provided so as to cover the additional layer 9 .
  • the material of the additional layer 9 may be the same as the material of the buried layer 3 or may be different. Examples of materials for the additional layer 9 are mainly SiNx (SiOx, SiON, SiCN, SiOC).
  • the additional layer 9 may have a single layer structure or a laminated structure. By providing the additional layer 9, reliability can be further improved.
  • FIG. 8 is a diagram showing an example of a schematic configuration of a photodetection device according to an eighth embodiment.
  • the auxiliary layer 6 has a laminated structure.
  • the auxiliary layer 6 has a three-layer structure and includes a layer 61, a layer 62, and a layer 63 in this order in the positive Z-axis direction.
  • the layers 61, 62, and 63 may be made of different materials or the same material. Depending on the number of layers and material design, it is possible to adjust warpage and expand bonding margins.
  • FIGS. 9 to 19 are diagrams illustrating an example of a method of manufacturing a photodetector.
  • FIGS. 9 to 14 show the photodetecting devices 100 (FIGS. 1 to 3, and FIGS. 5 to 3) according to the first to fourth embodiments and the sixth to eighth embodiments described above.
  • An example of the manufacturing method of 8) is shown below.
  • a substrate 1 including a photodetecting element 1p is prepared, and a chip 2 is provided on the substrate 1.
  • a buried layer 3 is provided to cover the substrate 1 and the chip 2.
  • a seam portion 4 is generated within the buried layer 3 due to the step provided by the chip 2 . At this point, the entire seam portion 4 is a void 4a.
  • the seam portions 4 corresponding to adjacent chips 2 may be connected to each other.
  • the additional layer 9 (FIG. 7) is provided so as to cover the substrate 1 and the chip 2
  • the buried layer 3 is provided so as to cover the additional layer 9.
  • a flattened surface 3a is obtained as shown in FIG.
  • the portion of the surface 3a where the seam portion 4 reaches is open.
  • a sealing layer 5 is provided to cover the buried layer 3.
  • the opening in the surface 3a is closed by the sealing layer 5.
  • the entire seam portion 4 remains the void 4a.
  • the entire seam portion 4 is filled with the material of the sealing layer 5, and that portion becomes the extension portion 5a of the sealing layer 5.
  • the fourth embodiment described above FIG. 3
  • only a portion of the seam portion 4 is filled with the material of the sealing layer 5, and that portion becomes the extension portion 5a of the sealing layer 5.
  • any aspect may be used.
  • an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, the auxiliary layer 6 is polished and cleaned. Since the seam portion 4 is covered with the sealing layer 5, the seam portion 4 does not widen even after cleaning.
  • a plurality of layers eg, layer 61, layer 62, and layer 63
  • the support substrate 7 is bonded to the auxiliary layer 6.
  • the photodetecting device 100 according to the first to fourth embodiments and the sixth to eighth embodiments described above can be manufactured as described above.
  • FIGS. 15 to 19 show an example of the manufacturing method of the fifth embodiment (FIG. 4) described above.
  • the steps up to preparing the substrate 1 and providing the chip 2 on the substrate 1 are the same as those in FIG. 9 described above.
  • the material of the side wall portion 8 (FIG. 4) is provided so as to cover the substrate 1 and chip 2.
  • etching for example, dry etching
  • etching is performed so that the above-mentioned material remains on the side surface of the chip 2.
  • the material remaining on the side surface of the chip 2 becomes the side wall portion 8.
  • a buried layer 3 is provided to cover the substrate 1, the chip 2, and the side wall portion 8.
  • a seam portion 4 is generated within the buried layer 3 due to the step provided by the chip 2 .
  • an auxiliary layer 6 is provided to cover the sealing layer 5.
  • the support substrate 7 is bonded to the auxiliary layer 6.
  • the photodetection device 100 according to the fifth embodiment described above can be manufactured as described above.
  • FIG. 20 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. Please note that the direction of the Z axis is reversed from the previous figures.
  • the illustrated photodetection device 100 is an imaging device configured to include a plurality of pixels 101. Examples of the pixel 101 include a pixel G that receives green light, a pixel R that receives red light, and a pixel B that receives blue light.
  • the substrate 1 is a substrate (image sensor substrate) configured to include a photoelectric conversion element corresponding to each pixel 101.
  • Photodetection device 100 includes a filter layer 10 and a lens layer 11.
  • the filter layer 10 is provided on the opposite side of the chip 2 and the buried layer 3 with the substrate 1 in between. In this example, the filter layer 10 is provided on the back surface 1b of the substrate 1.
  • Filter layer 10 includes multiple filters corresponding to multiple pixels 101.
  • a filter provided in pixel G is referred to as a filter 10G and illustrated.
  • the filter provided in pixel R is referred to as a filter 10R and illustrated.
  • the filter provided in pixel B is referred to as filter 10B and illustrated.
  • Filter 10G passes green light.
  • the filter 10R allows red light to pass through.
  • Filter 10B allows blue light to pass through.
  • Various known materials such as resins may be used.
  • the lens layer 11 is provided on the opposite side of the substrate 1 with the filter layer 10 in between.
  • the lens layer 11 includes a plurality of lenses 11a corresponding to the plurality of pixels 101.
  • the lens 11a is a condenser lens that condenses light that is incident on the photoelectric conversion element of the substrate 1 via the filter layer 10.
  • Various known materials such as resins may be used.
  • the photodetection device 100 having the above configuration can be used as an imaging device.
  • Other configurations are possible, and some examples are described with reference to FIGS. 21-23.
  • FIG. 21 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example.
  • Photodetection device 100 further includes an additional substrate 12 .
  • Additional substrate 12 is provided between substrate 1 and buried layer 3 .
  • the additional substrate 12 can also be said to be an intermediate substrate located between the substrate 1 and the support substrate 7.
  • a surface 12a the surface on the Z-axis positive direction side is referred to as a surface 12a and illustrated.
  • the surface on the negative side of the Z-axis is referred to as a back surface 12b.
  • the front surface 12a of the additional substrate 12 is in contact with the back surface 3b of the buried layer 3, and the back surface 12b of the additional substrate 12 is in contact with the front surface 1a of the substrate 1.
  • the additional board 12 has wiring layers on each of the front surface 12a side and the back surface 12b side.
  • the illustrated wiring layer of the additional board 12 is a multilayer wiring layer, and some wiring L is exposed on the front surface 12a or the back surface 12b.
  • the chip 2 is provided on the additional substrate 12 such that the mounting surface 2b of the chip 2 is in contact with the surface 12a of the additional substrate 12. More specifically, the chip 2 is mounted on the additional substrate 12 such that the wiring L of the chip 2 and the wiring L of the additional substrate 12 are in contact and electrically connected.
  • the mounting surface 2b of the chip 2 and the surface 12a of the additional substrate 12 define a bonding surface (chip bonding surface) between the chip 2 and the additional substrate 12.
  • the additional board 12 is bonded to the board 1 so that the wiring L of the additional board 12 and the wiring L of the board 1 are electrically contacted and connected.
  • the front surface 1a of the substrate 1 and the back surface 12b of the additional substrate 12 define a bonding surface (F2F bonding surface) between the substrate 1 and the additional substrate 12.
  • the additional board 12 includes through vias 12v.
  • the through via 12v penetrates the portion (substrate) between the wiring layer on the front surface 12a side of the additional board 12 and the wiring layer on the back surface 12b side of the additional board 12 so as to connect them.
  • more wiring and circuit elements can be formed.
  • the functionality of the photodetection device 100 can be further improved.
  • two or more additional substrates 12 may be provided.
  • FIGS. 22 and 23 are diagrams illustrating an example of a schematic configuration of a photodetection device according to an application example. As shown in FIG. 22, wiring L and structures are also provided between chips 2 that are arranged adjacent to each other with an interval. A through via V is exemplified as the structure.
  • the buried layer 3 and the auxiliary layer 6 also include the wiring L.
  • Some wiring lines L are provided between adjacent chips 2.
  • the wiring L may be provided in the seam portion 4, and the degree of freedom in layout is improved accordingly.
  • the through via V penetrates the buried layer 3, the sealing layer 5, the auxiliary layer 6, and the support substrate 7. Through the through-vias V, electrical access is made possible from the surface 7a of the support substrate 7 to the wiring layer on the surface 12a side of the additional substrate 12.
  • the through via V can also be called a contact via.
  • the through via V In the buried layer 3, at least some of the through vias V are located between adjacent chips 2. Further, the through via V may pass through the seam portion 4.
  • FIG. 23 schematically shows a planar layout. When viewed in plan (when viewed in the Z-axis direction), some of the through-vias V out of the plurality of through-vias V arranged around the chip 2 overlap with the seam portion 4 . Through vias V can be provided at various positions, and the degree of freedom in layout is improved accordingly.
  • the photodetecting device 100 includes a substrate 1 including a photodetecting element 1p, a chip 2 provided on the substrate 1, and an embedded portion provided to cover the chip 2.
  • a layer 3 a seam portion 4 generated within the buried layer 3 and extending to the surface 3a of the buried layer 3, and a sealing layer 5 provided so as to cover the buried layer 3 and the seam portion 4.
  • the photodetecting device 100 includes a support substrate that is located on the opposite side of the substrate 1 with the sealing layer 5 in between and supports the sealing layer 5 directly or indirectly. 7 may be provided. Since the seam portion 4 covered with the sealing layer 5 does not reach the bonding surface with the support substrate 7, deterioration in bonding quality due to void generation etc. can be suppressed.
  • At least a portion of the seam portion 4 may be a void 4a. Thereby, for example, inter-chip stress can be alleviated.
  • the sealing layer 5 may include the extending portion 5a that extends into the seam portion 4 so as to fill at least a portion of the seam portion 4.
  • the material of the sealing layer 5 may include a low permeability material. Thereby, for example, the effect of suppressing moisture and the like from entering the chip 2 can be enhanced.
  • the material of the sealing layer 5 may include a low Young's modulus material. Thereby, for example, inter-chip stress can be alleviated.
  • the photodetecting device 100 may include the side wall portion 8 provided so as to cover the side surface of the chip 2. Thereby, the protection performance of the chip 2 can be further improved.
  • the chip 2 includes a chip 2-1 (first chip) and a chip 2-2 (second chip) that are spaced apart from each other
  • the seam portion 4 includes a seam portion 4-1 (first seam portion) caused by the chip 2-1 and a seam portion 4-2 (second seam portion) caused by the chip 2-2.
  • the seam portion 4-1 and the seam portion 4-2 may be connected to each other. For example, even if there are a seam portion 4-1 and a seam portion 4-2 that are connected to each other in this manner, communication between them to the outside can be suppressed.
  • the photodetector 100 may include the additional layer 9 provided between the chip 2 and the buried layer 3. Thereby, reliability can be further improved.
  • the photodetector 100 may include the auxiliary layer 6 provided to cover the sealing layer 5. This makes it easier to bond to the support substrate 7, for example.
  • the auxiliary layer 6 may have a laminated structure. Depending on the number of layers and material design, it is possible to adjust warpage and expand bonding margins.
  • the chip 2 may include at least one of a logic chip, a memory chip, and an AI (Artificial Intelligence) chip.
  • a logic chip for example, it is possible to provide a highly functional photodetection device provided with such various chips 2.
  • AI Artificial Intelligence
  • the photodetection device 100 may be an imaging device configured to include a plurality of pixels 101.
  • the photodetecting device 100 includes a filter layer 10 provided on the opposite side of the chip 2 and the embedded layer 3 with the substrate 1 in between, a lens layer 11 provided on the opposite side of the substrate with the filter layer 10 in between, may be provided.
  • the photodetection device 100 can be applied to an imaging device.
  • the photodetecting device 100 may include the additional substrate 12 provided between the substrate 1 and the buried layer 3. Thereby, for example, the photodetection device 100 can be made highly functional.
  • the chip 2 includes two chips 2 arranged adjacent to each other with an interval, and the buried layer 3 is provided between the two chips 2.
  • the wiring L may be included. It becomes possible to further improve the functionality of the photodetecting device 100.
  • the photodetecting device 100 may include a through via V that penetrates the buried layer 3 , the sealing layer 5 , and the support substrate 7 . For example, it becomes possible to access the wiring layer on the surface 12a side of the additional substrate 12 from the surface 7a of the support substrate 7.
  • the photodetection device 100 described so far is a device mounted on any type of moving object such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, a robot, etc. It may also be realized as
  • FIG. 24 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated as the functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
  • the body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp.
  • radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
  • the external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted.
  • an imaging section 12031 is connected to the outside-vehicle information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electrical signal as an image or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040.
  • the driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
  • the microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, Control commands can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or shock mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or shock mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
  • the audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle.
  • an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 25 is a diagram showing an example of the installation position of the imaging section 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at, for example, the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield inside the vehicle.
  • An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100.
  • Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100.
  • An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 25 shows an example of the imaging range of the imaging units 12101 to 12104.
  • An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose.
  • the imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. By determining the following, it is possible to extract, in particular, the closest three-dimensional object on the path of vehicle 12100, which is traveling at a predetermined speed (for example, 0 km/h or more) in approximately the same direction as vehicle 12100, as the preceding vehicle. can. Furthermore, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, etc., in which the vehicle travels autonomously without depending on the driver's operation.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceed
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104.
  • pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not.
  • the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian.
  • the display unit 12062 is controlled to display the .
  • the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the photodetecting device 100 described above can be applied to, for example, the imaging section 12031 among the configurations described above.
  • the reliability of products including the photodetector 100 can be further improved.
  • the sealing layer 5 may or may not extend into the seam portion 4.
  • the material of the sealing layer 5 may be a low permeability material or a low Young's modulus material (for example, resin).
  • Photodetection device 100 may be an imaging device.
  • FIGS. 26 and 27 are diagrams illustrating an example of a schematic configuration of a photodetecting device according to a ninth embodiment.
  • Chip 2 includes a plurality of chips 2. As the plurality of chips 2, two chips 2 are illustrated in FIG. 26, and three chips 2 are illustrated in FIG. 27. The first chip is illustrated and referred to as chip 2-1. The second chip is designated and illustrated as chip 2-2. A third chip is illustrated and referred to as chip 2-3. Note that the chip 2-1 and the chip 2-2 here may be understood separately from the chip 2-1 and the chip 2-2 of the sixth embodiment (FIGS. 5 and 6) described above.
  • the chip 2-1 and the chip 2-2 have mutually different thicknesses (heights).
  • Chip 2-2 has a thickness greater than that of chip 2-1.
  • chip 2-1 has a thickness smaller than that of chip 2-2.
  • the seam portion 4 includes a seam portion 4-1 and a seam portion 4-2.
  • the seam portion 4-1 is a first seam portion extending from the chip 2-1 toward the surface 3a of the buried layer 3.
  • the seam portion 4-2 is a second seam portion extending from the chip 2-2 toward the surface 3a of the buried layer 3.
  • the length of the seam portion 4-1 may be shorter than the length of the seam portion 4-2 in the thickness direction thereof.
  • Seam portion 4-2 may extend closer to surface 3a of buried layer 3 than seam portion 4-1.
  • the seam portion 4-2 has reached the surface 3a of the buried layer 3, whereas the seam portion 4-1 has not reached the surface 3a of the buried layer 3.
  • the extending portion 5a of the sealing layer 5 may extend into the seam portion 4-2 so as to fill at least a portion of the seam portion 4-2.
  • the seam portion 4-1 can become a void 4a.
  • chip 2-3 is provided on chip 2-2.
  • Chip 2-2 and chip 2-3 are a plurality of chips 2 (stacked chips) stacked in this order.
  • Chip 2-3 is electrically connected to chip 2-2 via wiring.
  • the wiring also includes a through via 2v that penetrates the chip 2.
  • Chip 2-2 and chip 2-3 have a total thickness greater than the thickness of chip 2-1. As long as this condition is satisfied, the thickness of the chip 2-2 may be the same as or different from the thickness of the chip 2-1. The same applies to chip 2-3. Note that the number of stacked chips 2 may be three or more.
  • the seam portion 4 is the same as that shown in FIG. 26 described above.
  • the seam portion 4-2 may extend closer to the surface 3a of the buried layer 3 than the seam portion 4-1. In the example shown in FIG. 27, the seam portion 4-2 has reached the surface 3a of the buried layer 3, whereas the seam portion 4-1 has not reached the surface 3a of the buried layer 3.
  • Example of manufacturing method> 28 to 32 are diagrams illustrating an example of a method for manufacturing a photodetecting device. Note that descriptions of content that overlap with the previous description regarding the manufacturing method will be omitted as appropriate.
  • a chip 2-1 and a chip 2-2 are provided on a substrate 1.
  • a buried layer 3 is provided to cover the substrate 1, chips 2-1, and chips 2-2.
  • a seam portion 4-1 and a seam portion 4-2 are generated. At this point, both the seam portion 4-1 and the seam portion 4-2 are voids.
  • the buried layer 3 is planarized. Of the seam portions 4-1 and 4-2, the upper portion of the seam portion 4-2 is open. As shown in FIG. 31, a sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4-2. The sealing layer 5 extends into the seam portion 4-2, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 32, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 26 described above is obtained.
  • ⁇ Modified example> 33 and 34 are diagrams showing modified examples.
  • the seam portion 4-1 reaches the surface 3a of the buried layer 3, compared to the photodetecting device 100 shown in FIGS. 26 and 27 described above. The difference is that the extending portion 5a of the sealing layer 5 extends into the seam portion 4-1.
  • FIGS. 35 and 36 are diagrams showing an example of a schematic configuration of a photodetecting device according to a 10th embodiment.
  • the layered structure of the photodetecting device 100 described so far is multilayered.
  • the chip 2 includes two chips 2 located side by side in the height direction (Z-axis direction).
  • a chip 2-2 and a chip 2-3 are illustrated as two chips 2 located side by side in the height direction.
  • the chip 2-2 is a lower chip located below the chip 2-3 (on the Z-axis negative direction side).
  • Chip 2-3 is an upper chip located above chip 2-2 (on the Z-axis positive direction side). Note that the chip 2-2 is located at the same height as the chip 2-1.
  • the photodetector 100 further includes a bonding layer 13.
  • Bonding layer 13 is provided between chip 2-2 and chip 2-3.
  • the bonding layer 13 is configured to include wiring so as to provide electrical connection between the chips 2-2 and 2-3.
  • the parts of the bonding layer 13 other than the wiring may be made of an insulating material, and in this sense, the bonding layer 13 can also be called an insulating layer.
  • the chip 2-2 and the chip 2-3 are provided on opposite sides of the bonding layer 13 and are electrically connected to each other via the bonding layer 13.
  • the buried layer 3 includes a buried layer 3-1 and a buried layer 3-2.
  • the buried layer 3-1 is a lower buried layer provided to cover the substrate 1, the side surfaces of the chip 2-1, and the side surfaces of the chip 2-2.
  • the buried layer 3-2 is an upper buried layer provided to cover the bonding layer 13 and the chip 2-3.
  • the seam portion 4 includes a seam portion 4-1, a seam portion 4-2, and a seam portion 4-3.
  • Seam portion 4-1 extends from chip 2-1 toward surface 3a of buried layer 3-1.
  • Seam portion 4-2 extends from chip 2-1 toward surface 3a of buried layer 3-1.
  • the seam portion 4-3 extends from the chip 2-3 toward the surface 3a of the buried layer 3-2.
  • the seam portion 4-1 and the seam portion 4-2 are lower seam portions that occur within the buried layer 3-1 and extend to the surface 3a of the buried layer 3-1.
  • the seam portion 4-3 is an upper seam portion that occurs within the buried layer 3-2 and extends to the surface 3a of the buried layer 3-2.
  • the sealing layer 5 is provided to cover the buried layer 3-2 and the seam portion 4-3.
  • the bonding layer 13 is provided so as to cover the buried layer 3-1, the seam portion 4-1, and the seam portion 4-2.
  • the bonding layer 13 can function similarly to the sealing layer 5 with respect to the buried layer 3-1, the seam portion 4-1, and the seam portion 4-2.
  • the chip 2 further includes a dummy chip 2D.
  • the dummy chip 2D is located in the buried layer 3-2 above the chip 2-1.
  • the dummy chip 2D creates a state in the buried layer 3-2 as if a chip 2 with the same volume as the dummy chip 2D exists.
  • the material of the dummy chip 2D may be the same as the material of the chip 2, or may be different.
  • the dummy chip 2D does not need to have the function of the chip 2.
  • the chip 2-1 and the dummy chip 2D are provided on opposite sides of the bonding layer 13. Note that the chip 2-1 and the dummy chip 2D may or may not be electrically connected.
  • the dummy chip 2D has, for example, the same thickness as the chip 2-3.
  • the buried layer 3-2 is provided to cover the bonding layer 13, the dummy chip 2D, and the chip 2-3.
  • the seam portion 4 further includes a seam portion 4-D extending from the dummy chip 2D toward the surface 3a of the buried layer 3-2.
  • the sealing layer 5 is provided to cover the buried layer 3-2, the seam portion 4-D, and the seam portion 4-3.
  • the entire portion must be filled with the buried layer 3, and for example, the height of the buried layer 3 may be insufficient in that portion, making it difficult to planarize the buried layer 3.
  • This problem is addressed by providing a dummy chip 2D. That is, by providing the dummy chip 2D, planarization of the buried layer 3-2 becomes easier than in the case where the dummy chip 2D is not provided.
  • 37 to 43 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As a premise, it is assumed that the manufacturing process similar to that shown in FIGS. 28 and 29 described above has been completed.
  • the buried layer 3-1 here corresponds to the buried layer 3 in FIGS. 28 and 29, and the thickness of the chip 2-2 here is the same as the thickness of the chip 2-2 in FIGS. 28 and 29. is different.
  • the upper part of the buried layer 3-1 is polished and cleaned, and the sealing layer 5 is provided so as to cover the buried layer 3-1, the seam portions 4-1, and the seam portions 4-2.
  • the sealing layer 5 extends to the inside of the seam portion 4-1 and the seam portion 4-2, and that portion becomes an extension portion 5a of the sealing layer 5.
  • the sealing layer 5 is removed by polishing.
  • the extending portion 5a remains within the seam portion 4-1 and within the seam portion 4-2.
  • Surfaces 2a of chips 2-1 and 2-2 are exposed.
  • the surface 2a is the surface of the chips 2-1 and 2-2 on the Z-axis positive direction side.
  • a through via 2v is provided that penetrates the chip 2-2.
  • a bonding layer 13 is provided so as to cover the buried layer 3-1, the chip 2-1, the seam portion 4-1, the chip 2-2, and the seam portion 4-2.
  • a chip 2-3 is provided on the bonding layer 13 on the opposite side of the bonding layer 13 from the chip 2-2.
  • a buried layer 3-2 is provided to cover the bonding layer 13 and the chip 2-2.
  • a seam portion 4-3 is generated. At this point, the seam portion 4-3 is a gap.
  • a sealing layer 5 is provided to cover the buried layer 3-2, chip 2-3, and seam portion 4-3.
  • the sealing layer 5 extends into the seam portion 4-3, and that portion becomes an extension portion 5a of the sealing layer 5.
  • an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 35 described above is obtained.
  • FIG. 44 is a diagram showing a modification.
  • Two substrates 1 are prepared, a chip 2 and a buried layer 3 are provided on each substrate, and then they are bonded together via a bonding layer 13.
  • the first of the two substrates 1 is referred to as a substrate 1-1.
  • the second substrate is illustrated and referred to as substrate 1-2.
  • a manufacturing process similar to that up to the manufacturing process of FIG. 39 described above is performed on the substrate 1-1.
  • a chip 2-1 and a chip 2-2 are provided on the substrate 1-1, and a through via 2v is also provided.
  • a buried layer 3-1 is provided to cover the substrate 1-1, the chip 2-1, and the chip 2-2.
  • a seam portion 4-1 and a seam portion 4-2 are generated within the buried layer 3-1.
  • a sealing layer 5 is provided so as to cover the buried layer 3-1, the seam portion 4-1, and the seam portion 4-2.
  • the sealing layer 5 extends to the inside of the seam portion 4-1 and the seam portion 4-2, and that portion becomes an extension portion 5a of the sealing layer 5.
  • the sealing layer 5 is removed by polishing.
  • the extending portion 5a remains within the seam portion 4-1 and within the seam portion 4-2.
  • a bonding layer 13 is provided so as to cover the buried layer 3-1, the seam portions 4-1, and the seam portions 4-2.
  • a chip 2-3 and a dummy chip 2D are provided on the substrate 1-2, and a through via 3v passing through the chip 2-3 is provided.
  • a buried layer 3-2 is provided to cover the substrate 1-2, chip 2-2, and dummy chip 2D.
  • a seam portion 4-3 and a seam portion 4-D are generated within the buried layer 3-2.
  • a sealing layer 5 is provided to cover the buried layer 3-2, the seam portion 4-3, and the seam portion 4-D. The sealing layer 5 extends into the seam portion 4-3 and into the seam portion 4-D, and that portion becomes an extension portion 5a of the sealing layer 5.
  • the sealing layer 5 is removed by polishing.
  • the extension portion 5a remains within the seam portion 4-3 and within the seam portion 4-D.
  • the structure shown in FIG. 44 is obtained by bonding the buried layer 3-2 on the substrate 1-2 side obtained as described above to the bonding layer 13 on the substrate 1-1 side.
  • This bonding may be performed by bonding a wafer (for example, a semiconductor wafer) containing the substrate 1-1 and a wafer containing the substrate 1-2.
  • the interior of the seam portion 4 is filled with an extension portion 5a, and the opening portion of the seam portion is covered with a bonding layer 13. It can also be said that the bonding layer 13 functions as the sealing layer 5 covering the seam portion 4.
  • the photodetecting device 100 includes the chip 2-1 (first chip) and the chip 2-2 (first chip) having a thickness greater than that of the chip 2-1.
  • the seam portion 4 includes a seam portion 4-1 (first seam portion) extending from the chip 2-1 toward the surface 3a of the buried layer 3, and a seam portion 4-1 (first seam portion) extending from the chip 2-2 toward the surface 3a of the buried layer 3.
  • a seam portion 4-2 (second seam portion) extending toward the surface 3a of the buried layer 3, the seam portion 4-2 being closer to the surface 3a of the buried layer 3 than the seam portion 4-1. It may extend as close as possible.
  • the chip 2 includes a chip 2-1 (first chip), a chip 2-2 (second chip) and a chip 2 stacked in this order.
  • the chip 2-2 and the chip 2-3 have a thickness larger as a whole than the thickness of the chip 2-1, and the seam part 4 is separated from the chip 2-1.
  • a seam portion 4-1 (first seam portion) extending toward the surface 3a of the buried layer 3, and a seam portion 4-2 (first seam portion) extending from the chip 2-2 toward the surface 3a of the buried layer 3.
  • the seam portion 4-2 may extend closer to the surface 3a of the buried layer 3 than the seam portion 4-1. Even in such a configuration in which the thickness of the chip portions is different, communication of the seam portion 4 to the outside can be suppressed.
  • the sealing layer 5 extends into the seam portion 4-2 so as to fill at least a portion of the seam portion 4-2. It may include an extension portion 5a. Thereby, the advantage of the extension part 5a can also be obtained. For example, when the material of the sealing layer 5 includes a low permeability material, the effect of suppressing moisture etc. from entering the chip 2 can be enhanced, and the material of the sealing layer 5 includes a low Young's modulus material. If it is included, inter-chip stress can be alleviated.
  • the seam portion 4-1 does not reach the surface 3a of the buried layer 3, and the seam portion 4-2 does not reach the surface 3a of the buried layer 3. It's okay to do so. In this way, even if there are a mixture of seam portions 4-2 that reach the surface 3a of the buried layer 3 and seam portions 4-1 that do not reach the surface, communication of the seam portion 4 to the outside can be suppressed.
  • the chip 2 includes a chip 2-2 (lower chip) and a chip 2-3 (upper chip) located side by side in the height direction, and includes a photodetector.
  • 100 further includes a bonding layer 13 provided between the chip 2-2 and the chip 2-3, and the buried layer 3 includes a buried layer 3-1 (provided to cover the side surface of the chip 2-2).
  • a lower buried layer and a buried layer 3-2 (upper buried layer) provided to cover the chip 2-3 and the bonding layer 13; , a seam portion 4-2 (lower seam portion) that extends to the surface 3a of the buried layer 3-1, and a seam portion 4 that occurs within the buried layer 3-2 and extends to the surface 3a of the buried layer 3-2.
  • -3 upper seam part
  • the bonding layer 13 is provided so as to cover the buried layer 3-1 and the seam part 4-2, and the sealing layer 5 is provided to cover the buried layer 3-2 and the seam part 4.
  • -3 may be provided to cover. With such a configuration as well, communication of the seam portion 4 to the outside can be suppressed.
  • the chip 2 further includes a chip 2-1 (lower chip) and a dummy chip 2D provided on opposite sides with the bonding layer 13 in between, and a buried layer 3-2. may be provided to cover the chip 2-3, the dummy chip 2D, and the bonding layer 13. This makes planarization of the buried layer 3-2 easier than in the case where the dummy chip 2D is not provided.
  • FIGS. 45 and 46 are diagrams showing an example of a schematic configuration of a photodetecting device according to an 11th embodiment.
  • the sealing layer 5 includes a first portion 51 and a second portion 52.
  • the first portion 51 is a portion of the sealing layer 5 that covers the seam portion 4 . At least a portion of the first portion 51 is located between adjacent chips 2.
  • the second portion 52 is a portion of the sealing layer 5 that does not cover the seam portion 4 . At least a portion of the second portion 52 is located on top of the corresponding chip 2.
  • the second portion 52 may be a portion of the sealing layer 5 other than the first portion 51 .
  • the surface of the first portion 51 on the Z-axis positive direction side is referred to as a surface 51a in the drawing.
  • the surface on the negative side of the Z-axis is referred to as a back surface 51b.
  • the surface of the second portion 52 on the Z-axis positive direction side is referred to as a surface 52a and is illustrated.
  • the surface on the negative side of the Z-axis is referred to as a back surface 52b in the drawing.
  • the back surface 51b of the first portion 51 is located lower than the back surface 52b of the second portion 52 (on the Z-axis negative direction side).
  • the surface 51a of the first portion 51 is located at the same height as the surface 52a of the second portion 52.
  • the entire surface of the sealing layer 5 is a flat surface.
  • the surface 51a of the first portion 51 and the surface 52a of the second portion 52 are located at different heights.
  • the surface 52a of the second portion 52 is located above the surface 51a of the first portion 51 (on the Z-axis positive direction side).
  • the entire surface of the sealing layer 5 is a non-flat surface.
  • the auxiliary layer 6 (for example, SiO2, etc.) provided on the sealing layer 5 has a flat surface 6a, thereby ensuring flatness.
  • the auxiliary layer 6 can also be called an easy-to-planarize layer.
  • the thickness of the sealing layer 5 on the seam portion 4 can be increased compared to the configurations described above. Accordingly, the function of the sealing layer 5 to suppress communication of the seam portion 4 to the outside can be enhanced. Furthermore, since there is no need to flatten the buried layer 3, it is possible to prevent chemical liquid from entering the seam portion 4, which may occur during polishing or cleaning of the buried layer 3, for example.
  • 47 to 51 are diagrams illustrating an example of a method for manufacturing a photodetecting device.
  • 47 to 49 show an example of a manufacturing method for obtaining the configuration shown in FIG. 45 described above.
  • the sealing layer 5 is provided on the buried layer 3 without polishing it.
  • the sealing layer 5 extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5.
  • FIG. 48 by polishing and cleaning the upper part of the sealing layer 5, the sealing layer 5 including the first portion 51 and the second portion 52 as shown in FIG. is obtained.
  • the surface 51a of the first portion 51 and the surface 52a of the second portion 52 are both located at the same height, and the entire surface of the sealing layer 5 is a flat surface.
  • an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 45 described above is obtained.
  • FIGS. 50 and 51 show an example of a manufacturing method for obtaining the configuration shown in FIG. 46 described above. As a premise, it is assumed that the manufacturing process shown in FIG. 47 described above has been completed.
  • a sealing layer 5 including a first portion 51 and a second portion 52 similar to those in FIG. 49 described above is obtained, and this sealing layer 5 is not polished.
  • an auxiliary layer 6 is provided to cover the sealing layer 5.
  • FIG. 51 by polishing and cleaning the upper part of the auxiliary layer 6, the auxiliary layer 6 having a flat surface 6a is obtained. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 46 described above is obtained.
  • the sealing layer 5 may have a laminated structure. This will be explained with reference to FIG. 52.
  • FIG. 52 is a diagram showing an example of a schematic configuration of a sealing layer.
  • FIG. 52A schematically shows a cross section of the sealing layer 5 and its surroundings.
  • FIG. 52(B) schematically shows an enlarged cross section of a part of the sealing layer 5.
  • the sealing layer 5 has a laminated structure in which a plurality of layers are laminated.
  • the plurality of layers may include, for example, two types of layers.
  • One type of layer of the two types of layers may be an inorganic layer and the other type of layer may be an organic layer.
  • the inorganic layer is illustrated as an inorganic layer 53.
  • the organic layer is illustrated as organic layer 54 .
  • inorganic materials may be used as the material for the inorganic layer 53.
  • examples of inorganic materials are Al 2 O 3 , SiN, SiON, SiCN, etc.
  • organic materials may be used as the material for the organic layer 54.
  • materials are polymers, hybrid polymers, etc.
  • polymers are PEN, PET, PEG, etc.
  • Hybrid polymers are materials that include a polymer and, for example, a metallic material.
  • An example of a hybrid polymer when the metal material is aluminum is Alcone.
  • the organic layer 54 may be formed using, for example, spin coating, an inkjet method, an MLD method, or the like.
  • the MLD method may be suitably used to form the sealing layer 5 including the extension portion 5a extending into the seam portion 4.
  • the sealing layer 5 has a six-layer structure including three inorganic layers 53 and three organic layers 54.
  • the inorganic layers 53 and the organic layers 54 are alternately stacked.
  • the number of inorganic layers 53 and organic layers 54 may be smaller or larger than the number shown in FIG. 52.
  • the sealing layer 5 has a laminated structure, the function of the sealing layer 5 can be enhanced. For example, gas (water vapor, etc.) barrier properties can be improved, and robustness against deformation can be improved.
  • gas water vapor, etc.
  • the sealing layer 5 includes a first portion 51 that covers the seam portion 4, a second portion 52 that does not cover the seam portion 4, and a second portion 52 that does not cover the seam portion 4.
  • the back surface 51b of the first portion 51 may be located lower than the back surface 52b of the second portion 52 (on the Z-axis negative direction side).
  • the surface 51a of the first portion 51 may be located at the same height as the surface 52a of the second portion 52.
  • the photodetecting device 100 includes the auxiliary layer 6 provided to cover the sealing layer 5, and the surface 52a of the second portion 52 is It is located above the surface 51a of the portion 51 (on the Z-axis positive direction side), and the surface 6a of the auxiliary layer 6 may be a flat surface.
  • the thickness of the sealing layer 5 on the seam portion 4 can be increased. Accordingly, the function of the sealing layer 5 to suppress communication of the seam portion 4 to the outside can be enhanced.
  • the sealing layer 5 may have a laminated structure in which a plurality of layers are laminated.
  • the plurality of layers of the sealing layer 5 may include an inorganic layer 53 and an organic layer 54.
  • the function of the sealing layer 5 can be enhanced. For example, gas (water vapor, etc.) barrier properties can be improved, and robustness against deformation can be improved.
  • FIG. 53 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a 13th embodiment.
  • Photodetection device 100 includes a dummy chip 2D. Note that the dummy chip 2D here may be understood as being distinct from the dummy chip 2D of the tenth embodiment (FIG. 36) described above.
  • the dummy chip 2D is used to narrow the peripheral interval of the chip 2.
  • the dummy chip 2D is arranged adjacent to the chip 2 with an interval therebetween.
  • the chips 2 include two chips 2 spaced apart from each other.
  • the dummy chip 2D is provided between these two chips 2.
  • the buried layer 3 is provided to cover the substrate 1, chip 2, and dummy chip 2D.
  • Seam portion 4 extends to surface 3a of buried layer 3 in a portion between chip 2 and dummy chip 2D.
  • the aspect ratio of the portion of the buried layer 3 where the seam portion 4 occurs increases by the amount that the dummy chip 2D is provided.
  • the aspect ratio here corresponds to the ratio of the length in the Z-axis direction to the length in the XY plane direction. By increasing the aspect ratio, the direction in which the seam portion 4 extends is restricted.
  • the extending direction of the seam portion 4 is made close to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D.
  • the aspect ratio may be designed so that such a seam portion 4 can be easily obtained.
  • the aspect ratio may be designed within the range of 1-3.
  • the seam portion 4 extends along the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. Extending along the height direction may include not only extending in the same direction as the height direction, but also extending at a certain angle with respect to the height direction. Examples of such upper limits for angles are less than 30 degrees, less than 25 degrees, less than 20 degrees, less than 15 degrees, less than 10 degrees, less than 5 degrees, etc. The lower limit of the angle may be 0 degrees. Note that, hereinafter, extending along the height direction of the chip 2 and the dummy chip 2D will also be referred to as extending in the vertical direction.
  • the sealing layer 5 Since the seam portion 4 extends in the vertical direction, when the sealing layer 5 is provided to cover the embedded layer 3 and the seam portion 4, the sealing layer 5 easily extends into the seam portion 4. Become. The advantages of the extending portion 5a of the sealing layer 5 as described above can be easily obtained.
  • Example of manufacturing method> 54 to 58 are diagrams illustrating an example of a method for manufacturing a photodetecting device.
  • a chip 2 and a dummy chip 2D are provided on a substrate 1.
  • a buried layer 3 is provided (for example, formed into a film) so as to cover the substrate 1, chip 2, and dummy chip 2D. Seam portions 4 occur due to overhang during film formation. That is, the film is formed on the upper part of the chip 2 faster than the film forming speed on the bottom part between the chip 2 and the dummy chip 2D.
  • the material of the buried layer 3 is blocked during the film formation, and a seam portion 4 is generated between the chip 2 and the dummy chip 2D without being formed.
  • the extending direction of the seam portion 4 can be brought closer to the height direction (positive Z-axis direction) of the chips 2 and the dummy chips 2D. .
  • the seam portion 4 is a void.
  • the upper part of the buried layer 3 is polished and cleaned.
  • the upper part of the seam part 4 is open.
  • a sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4. Since the seam portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5.
  • an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 53 described above is obtained.
  • FIG. 59 is a diagram showing an example of a schematic configuration of a photodetection device according to a 14th embodiment.
  • the chip 2 has a shape in which the width (length in the XY plane direction) decreases as it approaches the surface 2a.
  • a portion located at the center of the chip 2 in the XY plane direction is referred to as a central portion 21 and illustrated.
  • a portion located outside the center portion 21 and including the edge of the chip 2 is referred to as an edge portion 22 and illustrated.
  • the edge 22 of the chip 2 has a round shape on the surface 2a of the chip 2.
  • the edge portion 22 may have a shape other than a round shape.
  • An example of another shape is a tapered shape.
  • the buried layer 3 is provided to cover the chip 2.
  • Seam portion 4 extends from chip 2 to surface 3a of buried layer 3. Since the width of the chip 2 on the front surface 2a side is narrow, the seam portion 4 extends along the height direction of the chip 2, that is, extends in the vertical direction. This is because the embeddability of the embedding layer 3 in the bottom of the periphery of the chip 2, more specifically in the area between adjacent chips 2 in this example, is improved.
  • the advantage of the seam portion 4 extending in the vertical direction is as described above.
  • ⁇ Example of manufacturing method> 60 to 64 are diagrams illustrating an example of a method for manufacturing a photodetecting device.
  • a chip 2 is provided on a substrate 1, the width of which is narrower on the front surface 2a side.
  • the chip 2 is processed so that the angle of the edge 22 of the chip 2 is less than 90 degrees.
  • An example of processing is chamfering the surface 2a of the chip 2. Examples of chamfering include C chamfering, R chamfering, etc. by plasma etching or the like.
  • a buried layer 3 is provided to cover the substrate 1 and chip 2.
  • the embedding property of the embedding layer 3 to the bottom of the portion between the chips 2 is improved.
  • the extending direction of the generated seam portion 4 is brought closer to the height direction of the chip 2 (positive Z-axis direction). At this point, the seam portion 4 is a void.
  • the upper part of the buried layer 3 is polished and cleaned.
  • the upper part of the seam part 4 is open.
  • a sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4. Since the seam portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5.
  • an auxiliary layer 6 is provided to cover the sealing layer 5. Even during polishing and cleaning of the auxiliary layer 6, the seam portion 4 is covered with the sealing layer 5, so the seam portion 4 does not widen. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 59 described above is obtained.
  • FIG. 65 is a diagram showing an example of a schematic configuration of a photodetection device according to a 15th embodiment.
  • the seam portion 4 has a shape in which the width (length in the XY plane direction) changes as it progresses in the extending direction.
  • the shape of the seam portion 4 may have a locally bulged shape.
  • the seam portion 4 includes an end portion 41, a center portion 42, and an end portion 43.
  • the center portion 42 is a portion located at the center of the seam portion 4 in the direction in which the seam portion 4 extends.
  • the end portion 41 and the end portion 43 are portions located at the ends of the seam portion 4 in the extending direction of the seam portion 4.
  • the end portion 41 and the end portion 43 are located on opposite sides of the center portion 42 . In this example, the end portion 41, the center portion 42, and the end portion 43 are located in this order along the Z-axis positive direction.
  • the central portion 42 has a width larger than the width of at least one of the end portions 41 and 43.
  • the width of the central portion 42 is greater than the width of the end portions 41 and also greater than the width of the end portions 43.
  • the seam portion 4 has a shape in which a central portion 42 is bulged in its extending direction.
  • the dummy chip 2D is provided on the substrate 1, but even if the dummy chip 2D is not provided, the seam portion 4 having a locally bulged shape may occur. It is possible. By providing the dummy chip 2D, the extending direction of the seam portion 4 can be made closer to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. Furthermore, instead of providing the dummy chip 2D, the same effect can be obtained by using the chip 2 whose width on the front surface 2a side is narrower as shown in FIG. 59 described above.
  • ⁇ Example of manufacturing method> 66 to 69 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As a premise, it is assumed that a manufacturing process similar to that shown in FIG. 54 described above has been completed. As shown in FIG. 66, a buried layer 3 is provided (for example, formed into a film) so as to cover the substrate 1, chip 2, and dummy chip 2D. Seam portions 4 occur due to overhang during film formation. The film is formed on the upper part of the chip 2 faster than the film on the bottom part between the chip 2 and the dummy chip 2D.
  • the material of the buried layer 3 is blocked during the film formation, and a gap is locally formed between the chip 2 and the dummy chip 2D without the film being formed midway. This gap becomes the seam portion 4. Since the peripheral interval of the chips 2 is narrowed by the provision of the dummy chips 2D, the extending direction of the seam portion 4 is brought closer to the height direction (Z-axis positive direction) of the chips 2 and the dummy chips 2D.
  • the upper part of the buried layer 3 is polished and cleaned.
  • the upper part of the seam part 4 is open.
  • a sealing layer 5 is provided to cover the embedded layer 3 and the seam portion 4. Since the seam portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5.
  • an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 65 described above is obtained.
  • the photodetecting device 100 includes the dummy chip 2D that is arranged adjacent to the chip 2 with a space therebetween, and the buried layer 3 supports the chip 2 and the dummy chip 2D.
  • the seam portion 4 may extend to the surface 3a of the buried layer 3 in a portion between the chip 2 and the dummy chip 2D.
  • the seam portion 4 may extend along the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D.
  • the chips 2 include two chips 2 provided apart from each other, and the dummy chip 2D may be provided between the two chips 2. Thereby, when the sealing layer 5 is provided so as to cover the embedded layer 3 and the seam part 4, the sealing layer 5 can easily extend into the seam part 4.
  • the advantages of the extending portion 5a of the sealing layer 5 can be easily obtained.
  • the chip 2 may have a shape in which the width becomes smaller toward the surface 2a of the chip 2 (as it progresses in the positive direction of the Z-axis).
  • the edge 22 of the chip 2 may have a tapered shape or a round shape on the surface 2a of the chip 2.
  • the seam portion 4 may extend along the height direction (Z-axis direction) of the chip 2. Such a configuration also allows the sealing layer 5 to easily extend into the seam portion 4 when the sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4 .
  • the seam portion 4 may have a shape in which the width changes as it progresses in its extending direction.
  • the seam portion 4 includes a center portion 42 located at the center in the extending direction of the seam portion 4, and an end portion 41 (or may be an end portion 43) located at an end in the extending direction of the seam portion 4.
  • the portion 42 may have a width greater than the width of the end portion 41 (which may also be the end portion 43). Even when the seam portion 4 has such a shape, communication of the seam portion 4 to the outside can be suppressed.
  • the extending direction of the seam portion 4 can be set in the height direction of the chip 2 (Z-axis direction). can be approached.
  • FIG. 70 and 71 are diagrams showing a first arrangement example of dummy chips.
  • FIG. 70 schematically shows a cross section of the photodetector 100.
  • FIG. 71 schematically shows a cross section (planar layout) of the photodetector 100 taken along the line II in FIG. 70. Note that in the example shown in FIG. 70, the seam portion 4 is filled with the extension portion 5a. In FIG. 71, the seam portion 4 is simplified and depicted as having no width.
  • the chip 2 has a side surface 2c, a side surface 2d, a side surface 2e, and a side surface 2f.
  • the side surface 2c and the side surface 2d are a pair of side surfaces facing each other.
  • the side surface 2e and the side surface 2f are a pair of side surfaces that face each other and connect the side surface 2c and the side surface 2d.
  • the side surface 2c, the side surface 2d, the side surface 2e, and the side surface 2f of the chip 2 are not particularly distinguished, they are also simply referred to as the side surface of the chip 2.
  • the dummy chip 2D extends to face the side surface of the chip 2 when viewed in plan.
  • the dummy chips 2D may be a plurality of dummy chips 2D, each facing a different side surface of the chip 2.
  • Two or more dummy chips 2D may be provided for one chip 2.
  • the material of the dummy chip 2D may include the same material as the material of the chip 2. Further, the dummy chip 2D may have the same height as the chip 2. In the XY plane direction, the chips 2 and the dummy chips 2D may be provided alternately.
  • the material of the buried layer 3 is reduced from the chip 2 toward the periphery when the buried layer 3 is provided (for example, during film formation), compared to when the dummy chip 2D is not provided. It is possible to suppress the stress that acts on the
  • the dummy chip 2D may include two or more dummy chips 2D.
  • the dummy chips 2D include four dummy chips 2D.
  • the dummy chip 2D facing the side surface 2c of the chip 2 is shown as a dummy chip 2D-1.
  • the dummy chip 2D facing the side surface 2d of the chip 2 is shown as a dummy chip 2D-2.
  • the dummy chip 2D facing the side surface 2e of the chip 2 is shown as a dummy chip 2D-3.
  • the dummy chip 2D facing the side surface 2f of the chip 2 is shown as a dummy chip 2D-4.
  • the dummy chips 2D are arranged at intervals from each other. Near the corners of the chip 2, the dummy chips 2D are spaced apart from each other.
  • FIG. 72 is a diagram showing the effect of the dummy chip.
  • FIG. 72A schematically shows the range of the seam portion 4E1 that may occur when only the chip 2 is provided.
  • FIG. 72(B) schematically shows the range of the seam portion 4E2 that may occur when only the dummy chip 2D is provided.
  • FIG. 72C schematically shows the range of the seam portion 4 that occurs when the chip 2 and the dummy chip 2D are provided.
  • the dummy chip 2D may have a length equal to or more than half the length of the side surface of the opposing chip 2 in its extending direction.
  • the length of the side surface 2c of the chip 2 is shown as a length H.
  • the length of the side surface 2e of the chip 2 is shown as a length W.
  • the length of the dummy chip 2D-1 in the extending direction facing the side surface 2c of the chip 2 is referred to as length HD in the drawing.
  • the length of the dummy chip 2D-3 in the extending direction facing the side surface 2e of the chip 2 is referred to as a length W D in the drawing.
  • the length HD of the dummy chip 2D-1 may be designed to satisfy the following formula (1).
  • Dummy chip 2D-2 may be designed similarly.
  • the dummy chip 2D-3 may be designed to satisfy the following formula (2).
  • W D ⁇ W/2 (2) Dummy chip 2D-4 may be designed similarly.
  • the effect of the dummy chip 2D that is, the extending direction of the seam portion 4 is brought closer to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. This effect becomes easier to obtain.
  • the dummy chip 2D is arranged so as to sandwich the chip 2.
  • the dummy chip 2D-1 and the dummy chip 2D-2 are arranged on opposite sides of the chip 2 so as to sandwich the chip 2 therebetween.
  • the dummy chip 2D-3 and the dummy chip 2D-4 are arranged on opposite sides of the chip 2 so as to sandwich the chip 2 therebetween.
  • the area where the effect of the dummy chip 2D can be obtained can be expanded compared to the case where only the dummy chip 2D is provided facing one side of the chip 2.
  • the components of the photodetector 100 may be provided in each region defined by a scribe line on the wafer, for example.
  • the photodetector 100 is obtained by dicing (cutting) the wafer along the scribe lines. This will be explained with reference to FIG. 73.
  • FIG. 73 is a diagram showing an example of a schematic configuration of a wafer.
  • the ware is referred to as a wafer 200 and illustrated.
  • FIG. 73 schematically shows a part of the wafer 200 when viewed from above (when viewed in the negative Z-axis direction).
  • a scribe line SL-H and a scribe line SL-V are formed on the wafer 200, which are perpendicular to each other. When these are not particularly distinguished, they are simply referred to as scribe lines SL.
  • One area surrounded by scribe line SL-H and scribe line SL-V corresponds to one photodetector 100.
  • the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL (not located on the scribe line SL).
  • One piece (1 shot) obtained by dicing the wafer 200 along the scribe line SL becomes the photodetecting device 100.
  • the material of the dummy chip 2D may include the same material as the material of the chip 2.
  • the dummy chip 2D may have the same height as the chip 2. Further, the dummy chip 2D may be arranged to sandwich the chip 2.
  • FIG. 74 is a diagram showing a second arrangement example of dummy chips.
  • the dummy chip 2D extends continuously to surround the chip 2.
  • dummy chips 2D-1 to 2D-4 are arranged to surround chip 2, and are connected to each other.
  • the entire periphery of the chip 2 is surrounded by the dummy chip 2D, and the effect of the dummy chip 2D can be maximized.
  • FIG. 75 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
  • FIG. 76 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL.
  • the photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
  • FIG. 77 is a diagram showing a third arrangement example of dummy chips.
  • Dummy chip 2D-1, dummy chip 2D-2, dummy chip 2D-3, and dummy chip 2D-4 are arranged so as to surround chip 2, and are spaced apart from each other.
  • the side surface of the dummy chip 2D-1, the side surface of the dummy chip 2D-2, the side surface of the dummy chip 2D-3, and the side surface of the dummy chip 2D-4, which is located on the opposite side to the chip 2, is the side surface 2D-1a. , side surface 2D-2a, side surface 2D-3a, and side surface 2D-4a. These side surfaces constitute part of the side surfaces of the photodetector 100.
  • the side surface 2D-1a, the side surface 2D-2a, the side surface 2D-3a, and the side surface 2D-4a are separated from the buried layer 3. Exposed (not covered by buried layer 3).
  • FIG. 78 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
  • FIG. 79 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 of the photodetector 100 is located inside the scribe line SL.
  • the dummy chips 2D of adjacent photodetecting devices 100 are provided in a continuous manner across the scribe line SL. It can also be said that these dummy chips 2D are provided on the scribe line SL.
  • the photodetector 100 is obtained by dicing the wafer 200 and the dummy chips 2D along the scribe line SL. Since the dummy chips 2D of adjacent photodetecting devices 100 can be provided together, manufacturing becomes easier.
  • FIG. 80 is a diagram showing a fourth example of arrangement of dummy chips.
  • the chip 2 is placed near a corner of the photodetector 100.
  • the chip 2 is arranged such that the side surface 2c and the side surface 2e of the chip 2 are located near the side surface of the photodetecting device 100.
  • Two dummy chips 2D facing the other two sides of the chip 2 are arranged.
  • a dummy chip 2D-2 facing the side surface 2d of the chip 2 and a dummy chip 2D-4 facing the side surface 2f of the chip 2 are arranged.
  • FIG. 81 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
  • FIG. 82 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL.
  • the photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
  • FIG. 83 is a diagram showing a fifth arrangement example of dummy chips.
  • Dummy chip 2D-1, dummy chip 2D-2, dummy chip 2D-3, and dummy chip 2D-4 are arranged so as to surround chip 2, and are spaced apart from each other. Unlike FIG.
  • the side surface 2D-1a of the dummy chip 2D-1, the side surface 2D-2a of the dummy chip 2D-2, and the side surface 2D-2a of the dummy chip 2D-3 are The side surface 2D-3a and the side surface 2D-4a of the dummy chip 2D-4 are not exposed from the buried layer 3 (covered by the buried layer 3).
  • FIG. 84 is a diagram showing the effect of the dummy chip 2D. The explanation will be omitted since it is the same as that of FIG. 72 above.
  • FIG. 85 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL. Unlike FIG. 79 described above, the dummy chips 2D of adjacent photodetecting devices 100 do not straddle the scribe line SL and are separated from each other.
  • the photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
  • FIG. 86 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 includes two or more chips 2, and two chips 2 are illustrated in FIG. A side surface 2e of one chip 2 and a side surface 2f of the other chip 2 face each other.
  • Two dummy chips 2D are arranged. One of the dummy chips 2D is placed between the two chips 2. This dummy chip 2D is shown as a dummy chip 2D-34. Another dummy chip 2D is a dummy chip 2D-2 arranged so as to extend along the side surfaces 2d of the two chips 2.
  • FIG. 87 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
  • FIG. 88 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL.
  • the photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
  • FIG. 89 is a diagram showing a seventh example of arrangement of dummy chips.
  • the advantages of the second arrangement example (FIG. 74) and the third arrangement example (FIG. 77) described above are combined.
  • the dummy chip 2D extends continuously to surround the chip 2.
  • dummy chips 2D-1 to 2D-4 are arranged to surround chip 2, and are connected to each other.
  • the side surface 2D-1a of the dummy chip 2D-1, the side surface 2D-2a of the dummy chip 2D-2, The side surface 2D-3a of the dummy chip 2D-3 and the side surface 2D-4a of the dummy chip 2D-4 are exposed from the buried layer 3.
  • FIG. 90 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
  • FIG. 91 is a diagram showing an example of a schematic configuration of a wafer.
  • the chip 2 of the photodetector 100 is located inside the scribe line SL.
  • the dummy chips 2D of adjacent photodetecting devices 100 are provided so as to be connected across the scribe line SL.
  • the photodetector 100 is obtained by dicing the wafer 200 and the dummy chips 2D along the scribe line SL.
  • FIGS. 92 and 93 are diagrams showing modified examples. .
  • FIG. 92 schematically shows a cross section of the photodetector 100.
  • FIG. 93 schematically shows a cross section (planar layout) of the photodetector 100 taken along line II-II in FIG. 92.
  • the arrangement of the dummy chips 2D is the same as the first arrangement example (FIGS. 70 and 71) described above.
  • the sealing layer 5 does not have the extending portion 5a, and the seam portion 4 is a void. Even in this case, the effect of the dummy chip 2D can be obtained.
  • the seam portion 4 may be a void in the second to seventh arrangement examples described above as well.
  • the photodetecting device 100 in which the dummy chip 2D is arranged as described above is specified, for example, as follows.
  • the chip 2D extends so as to face the side surface of the chip 2, and has a length (in the extending direction) that is at least half the length (length H, length W) of the side surface of the chip 2 that faces the chip 2D. (H D ⁇ H/2, W D ⁇ W/ 2 ).
  • the effect of the dummy chip 2D that is, the extending direction of the seam portion 4 can be adjusted in the height direction of the chip 2 (Z-axis positive direction) of the chip 2 and the dummy chip 2D. It becomes easier to obtain the effect of bringing the distance closer to .
  • the dummy chip 2D may be arranged to sandwich the chip 2 when viewed from above.
  • the dummy chip 2D may include two or more dummy chips 2D.
  • the area where the effect of the dummy chip 2D can be obtained can be expanded, for example, compared to the case where only one dummy chip 2D facing one side of the chip 2 is provided.
  • the material of the dummy chip 2D may include the same material as the material of the chip 2. Furthermore, the dummy chip 2D may have the same height as the chip 2 (length in the Z-axis direction). For example, by using such a dummy chip 2D, the extending direction of the seam portion 4 can be brought closer to the height direction (Z-axis direction) of the chip 2 and the chip 2 of the dummy chip 2D.
  • the chip includes two or more chips. For example, even in such a multi-chip configuration, the effect of the dummy chip 2D can be obtained.
  • the dummy chip 2D may continuously extend to surround the chip 2 when viewed in plan. Thereby, the effect of the dummy chip 2D can be maximized.
  • the dummy chips 2D (for example, the dummy chips 2D-1, Dummy chip 2D-2, dummy chip 2D-3, dummy chip 2D-4) have side surfaces exposed from buried layer 3 (for example, side surface 2D-1a, side surface 2D-2a, side surface 2D-3a, side surface 2D-4a).
  • the dummy chip 2D can be placed at the outermost position of the photodetector 100. For example, it becomes easier to secure a region where the chip 2 is to be provided.
  • the dummy chips 2D of adjacent photodetecting devices 100 can be provided together on the wafer 200, manufacturing becomes easier.
  • FIG. 94 is a diagram showing an example of a schematic configuration of a photodetection device according to a 16th embodiment.
  • the photodetecting device 100 includes a sealing layer 5-2 instead of the sealing layer 5.
  • photodetector 100 does not include auxiliary layer 6.
  • the support substrate 7 is joined (bonded) via the sealing layer 5-2.
  • the buried layer 3 is provided to cover the side surface of the chip 2. A surface 2a of the chip 2 is exposed from the buried layer 3. At least a portion of the seam portion 4 is filled with a material different from the material of the buried layer 3. In this example, the extending portion 5a described above extends within the seam portion 4 so as to fill at least a portion of the seam portion 4.
  • the sealing layer 5-2 is provided to cover the buried layer 3, the seam portion 4, and the surface 2a of the chip 2.
  • the sealing layer 5-2 is in contact not only with the surface 3a of the buried layer 3 but also with the surface 2a of the chip 2.
  • the sealing layer 5-2 has a higher thermal conductivity than that of silicon (Si).
  • the portion to which heat from the chip 2 is transmitted is more likely to be thermally connected to the outside through the sealing layer 5-2 (easier to be thermally exposed, and heat dissipation and other heat dissipation properties can be improved.
  • a metal material is used for the buried layer 3 with the aim of improving heat dissipation by the buried layer 3, there is a possibility that leakage may occur between the buried layer 3 and the chip 2, reducing the reliability of the device.
  • leakage can be suppressed and reliability of the device can be improved.
  • FIG. 95 is a diagram showing an example of a schematic configuration of a photodetecting device according to a 17th embodiment.
  • the photodetecting device 100 includes the above-described sealing layer 5-2 instead of the auxiliary layer 6 described above.
  • Two sealing layers are provided: sealing layer 5 and sealing layer 5-2.
  • the sealing layer 5 is a first sealing layer provided so as to cover the embedded layer 3 and the seam portion 4 .
  • the sealing layer 5-2 is a second sealing layer provided to cover the sealing layer 5.
  • Support substrate 7 is bonded via sealing layer 5-2. It is also possible to improve heat dissipation by providing the sealing layer 5-2 in this manner.
  • FIG. 96 is a diagram showing an example of a schematic configuration of a photodetection device according to an 18th embodiment.
  • the photodetecting device 100 differs from the configuration of FIG. 94 described above in that it does not include the sealing layer 5-2 but includes the sealing layer 5-3.
  • the sealing layer 5-3 is a metal layer.
  • materials for the metal layer include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), and palladium ( Pd) etc.
  • Support substrate 7 is bonded via sealing layer 5-3. In this way, the sealing layer 5-3, which is a metal layer, can be provided to improve heat dissipation.
  • FIG. 97 is a diagram showing an example of a schematic configuration of a photodetection device according to a nineteenth embodiment.
  • the photodetecting device 100 does not include the sealing layer 5-2, but does include the sealing layer 5-4, compared to the configuration of FIG. 94 described above.
  • the sealing layer 5-4 includes an insulating layer 50 and a sealing layer 5-2 that extend continuously in the plane direction (XY plane direction) of the sealing layer 5-4.
  • the insulating layer 50 is a first portion of the sealing layer 5-4 that covers the buried layer 3 and the buried layer 3 of the chip 2.
  • the sealing layer 5-2 is a second portion provided to cover the buried layer 3 and the buried layer 3 of the chip 2.
  • the insulating layer 50 has insulating properties. Examples of materials for the insulating layer 50 include SiOx, SiNx, SiON, SiOC, SiCN, and SiC. As mentioned earlier, the sealing layer 5-2 has a higher thermal conductivity than that of silicon. The sealing layer 5-2 may be provided so as to be in contact with the surface 2a of the chip 2. It is also possible to improve heat dissipation by providing the sealing layer 5-2 in this manner.
  • FIG. 98 is a diagram showing an example of a schematic configuration of a photodetection device according to a 20th embodiment.
  • the photodetecting device 100 differs from the configuration of FIG. 94 described above in that it does not include the sealing layer 5-2 but includes the additional layer 9.
  • the additional layer 9 here may be understood separately from the additional layer 9 of the seventh embodiment (FIG. 7) described above.
  • the additional layer 9 is provided between the chip 2 and the buried layer 3. More specifically, the additional layer 9 is provided to cover the substrate 1 and the chip 2. The buried layer 3 is provided to cover the additional layer 9 except for the portion of the additional layer 9 located above the chip 2 .
  • the additional layer 9 in this embodiment is a metal layer (also called a barrier metal).
  • a metal layer also called a barrier metal.
  • materials for the metal layer are titanium (Ti), tantalum (Ta), and the like.
  • the interior of the seam portion 4 is filled with an extension portion 5a, and the seam portion 4 is covered with an additional layer 9.
  • Support substrate 7 is bonded via buried layer 3 and additional layer 9 .
  • the support substrate 7 and the additional layer 9 can serve as a sealing layer covering the buried layer 3 , the seam 4 and the chip 2 .
  • FIG. 99 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a 21st embodiment.
  • a part of the seam part 4 is filled with an extension part 5a, but the remaining part is a void 4a.
  • the sealing layer 5-2 can be provided to improve heat dissipation.
  • the stress between the chips 2 can be relaxed by the amount of the gap 4a.
  • part of the seam portion 4 may be filled with the extension portion 5a, and the remaining portion may be the void 4a.
  • FIG. 100 is a diagram showing an example of a schematic configuration of a photodetecting device according to a 22nd embodiment.
  • the photodetecting device 100 differs from the configuration of FIG. 94 described above in that it includes a compound layer 14.
  • the compound layer 14 is provided between the chip 2 and the sealing layer 5-2, and is also provided on the sealing layer 5-2.
  • the compound layer 14 may be, for example, a silicide layer.
  • Examples of materials for the compound layer 14 may include semiconductor materials such as silicon (Si) and metal materials.
  • the first compound layer 14 is provided on the surface 2a of the chip 2.
  • the sealing layer 5-2 is provided so as to cover the buried layer 3, the seam portion 4, and the first compound layer 14.
  • the second compound layer 14 is provided to cover the sealing layer 5-2.
  • the support substrate 7 is bonded via this compound layer 14. It is also possible to improve heat dissipation by providing the compound layer 14 containing a metal material in this way.
  • FIG. 101 is a diagram showing an example of a schematic configuration of a photodetection device according to a 23rd embodiment.
  • the photodetecting device 100 differs from the configuration of FIG. 94 described above in that it does not include the sealing layer 5-2 but includes the sealing layer 5-5.
  • the sealing layer 5-5 is a layer in which metal structures such as wiring (including vias) are provided within an insulator.
  • the metal structure provides a heat dissipation path and can be used as wiring or as a pad.
  • An example of a metal structure is shown labeled as via 5-5v. Heat dissipation can also be improved by providing the sealing layer 5-5 in this manner.
  • wiring can be formed on the bonding surface between the buried layer 3 and the support substrate 7.
  • Example of Application to Imaging Device An example of application of the photodetecting device 100 according to the sixteenth to twenty-third embodiments described above is an imaging device. The imaging device was previously described with reference to FIGS. 20 to 23, so detailed description will not be repeated. For example, when the photodetection device 100 according to the sixteenth embodiment is used as an imaging device, a configuration including a sealing layer 5-2 in place of the sealing layer 5 and the auxiliary layer 6 in FIGS. 20 to 22 is adopted. be able to.
  • FIGS. 102 to 107 are diagrams showing an example of a method of manufacturing a photodetector. 102 to 105 show an example of a manufacturing method for obtaining the structure shown in FIG. 94 described above. It is assumed that a manufacturing process similar to that shown in FIGS. 9 to 12 described above has been completed.
  • the sealing layer 5 and the buried layer 3 are polished and cleaned.
  • the surface 2a of the chip 2 is exposed from the buried layer 3.
  • a sealing layer 5-2 is provided to cover the buried layer 3, seam portion 4, and chip 2.
  • FIG. 104 by bonding the support substrate 7 through the sealing layer 5-2, the configuration shown in FIG. 94 described above can be obtained.
  • bonding surface B is located between support substrate 7 and sealing layer 5-2.
  • bonding surface C is located in the sealing layer 5-2.
  • the bonding surface D is located between the sealing layer 5-2 and the buried layer 3.
  • the supporting substrate 7, the sealing layer 5-2, and the buried layer 3 are disassembled in the Z-axis direction at the bonding surface B, bonding surface C, and bonding surface D.
  • the diagram is shown schematically. A compound (silicide) is generated during the bonding process, and in that case, the configuration shown in FIG. 100 described above is obtained.
  • FIGS. 106 and 107 show an example of a manufacturing method for obtaining the configuration shown in FIG. 101 described above. As a premise, it is assumed that the manufacturing process up to FIG. 102 described above has been completed.
  • a sealing layer 5-5 is provided to cover the buried layer 3, seam portion 4, and chip 2.
  • the structure shown in FIG. 101 described above can be obtained by bonding the support substrate 7 through the sealing layer 5-5.
  • the photodetecting device 100 is specified, for example, as follows. As described with reference to FIGS. 94 and 99, at least a portion of the seam portion 4 is filled with a material (for example, the extension portion 5a) different from the material of the buried layer 3, and the sealing layer 5 -2 is a layer having a thermal conductivity higher than that of silicon (Si). Even in such a configuration, communication of the seam portion 4 to the outside can be suppressed. Moreover, heat dissipation can be improved.
  • a material for example, the extension portion 5a
  • Si silicon
  • the photodetector 100 includes the sealing layer 5 (first sealing layer) provided so as to cover the embedded layer 3 and the seam portion 4, and the sealing layer 5.
  • a sealing layer 5-2 (second sealing layer) provided to cover the silicon (Si), and the sealing layer 5-2 has a thermal conductivity higher than that of silicon (Si). You may do so. Such a configuration can also improve heat dissipation.
  • the sealing layer 5-3 may be a metal layer. Such a configuration can also improve heat dissipation.
  • the sealing layer 5-4 includes an insulating layer 50 (first portion) that covers the buried layer 3 of the buried layer 3 and the chip 2, and an insulating layer 50 (first portion) that covers the buried layer 3 and the chip 2.
  • the insulating layer 50 has an insulating property
  • the sealing layer 5-2 includes a sealing layer 5-2 (second portion) that covers the chip 2 of the silicon (Si). It may have higher thermal conductivity than conductivity. Such a configuration can also improve heat dissipation.
  • the photodetector 100 includes the additional layer 9 provided between the chip 2 and the buried layer 3, and the additional layer 9 may be a metal layer. Such a configuration can also improve heat dissipation.
  • the photodetector 100 includes the compound layer 14 provided between the chip 2 and the sealing layer 5-2, and the compound layer 14 is a silicide layer. good. Such a configuration can also improve heat dissipation.
  • the sealing layer 5-5 may be a layer in which a metal structure (for example, a via 5-5v, etc.) is provided within an insulator. Such a configuration can also improve heat dissipation. When the support substrate 7 is bonded, wiring can also be formed on the bonding surface portion.
  • a metal structure for example, a via 5-5v, etc.
  • FIGS. 108 and 109 are diagrams showing an example of a schematic configuration of a photodetection device according to a 24th embodiment. Note that illustration of the support substrate 7 is omitted, and this point is also the same in subsequent figures.
  • the photodetecting device 100 includes a sealing layer 5-6 instead of the sealing layer 5.
  • the sealing layer 5-6 is a resin layer. Among the surfaces of the sealing layer 5-6, the surface on the Z-axis positive direction side is referred to as a surface 5-6a in the drawing.
  • FIG. 109 schematically shows an enlarged view of a portion including the chip 2, the buried layer 3 located above it, and the sealing layer 5.
  • the buried layer 3 has an uneven shape on the surface 3a.
  • the surface 3a of the buried layer 3 has a concave portion 3c1 and a convex portion 3c2.
  • the recessed portion 3c1 has a concave shape that is recessed downward (in the Z-axis positive direction).
  • the convex portion 3c2 has a convex shape that protrudes upward (in the Z-axis positive direction).
  • the sealing layer 5-6 is a resin layer provided to fill the recess 3c1 and cover the recess 3c1 and the projection 3c2.
  • the resin layer may be an oxidized layer or an organic layer.
  • the oxide layer may be, for example, an oxide-based insulating film or an oxide-based bonding film.
  • the organic layer may have a heat resistance of, for example, 400° C. or higher. Examples of materials for such organic layers are polyimides, siloxanes, silicones, etc. It can withstand heat even when exposed to heat of about 400°C in a post-process.
  • the sealing layer 5-6 may be coated on the buried layer 3 in the form of a coating liquid during manufacturing. This makes it easier to fill the recess 3c1 with the sealing layer 5-6, and also makes it easier for the sealing layer 5-6 to extend into the seam portion 4. Since it is not a conformal film formation method, the surface after application is flatter than before application. In the example shown in FIG. 109, the surface 5-6a of the sealing layer 5-6 is a flat surface. That is, the sealing layer 5-6 absorbs the shapes of the concave portions 3c1 and convex portions 3c2 on the surface 3a of the buried layer 3, resulting in a flat surface 5-6a.
  • 110 to 114 are diagrams illustrating an example of a method for manufacturing a photodetecting device.
  • chips 2 are provided on a substrate 1, and a buried layer 3 is provided to cover them.
  • a seam portion 4 is generated within the buried layer 3.
  • the buried layer 3 on the chip 2 is removed by a lithography process including dry etching, leaving the upper part of the corner of the chip 2.
  • the buried layer 3 remaining above the corner of the chip 2 is shown as a corner 3h. By leaving the corner portion 3h, the outer portion of the chip 2 can be protected and the embedded layer 3 on the outer side of the chip 2 can be prevented from falling out.
  • a buried layer 3 is further provided.
  • a seam 4 also occurs within the buried layer 3 at the top of the chip 2.
  • the corner 3h is removed by CMP.
  • the CMP here differs from normal CMP in the slurry composition, etc., and ends when the slurry becomes somewhat flat (Self-stop CMP).
  • a sealing layer 5-6 is provided to cover the buried layer 3 and the seam portion 4.
  • the sealing layer 5-6 is provided by applying the material (resin material). At this time, the material of the sealing layer 5-6 extends into the seam portion 4, and that portion becomes the extended portion 5a of the sealing layer 5-6.
  • the recess 3c1 in the surface 3a of the buried layer 3, which was previously explained with reference to FIG. 109, is filled with the sealing layer 5-6. Thereafter, by providing the auxiliary layer 6 to cover the sealing layer 5, the configurations shown in FIGS. 108 and 109 described above are obtained.
  • the lithography and subsequent process of forming the buried layer 3 may be omitted.
  • 115 to 119 are diagrams illustrating an example of a method for manufacturing a photodetecting device. Compared to the manufacturing method shown in FIGS. 110 to 114 described above, a CMP process is added before providing the sealing layer 5-6. As a premise, it is assumed that the manufacturing process shown in FIG. 111 described above has been completed.
  • a buried layer 3 is further provided.
  • the thickness (length in the Z-axis direction) of the buried layer 3 added here may be greater than the thickness of the buried layer 3 in FIG. 112 described above.
  • the corner 3h is removed by self-stop CMP.
  • the upper part of the buried layer 3 is polished and cleaned by CMP. During this CMP, the portions of the buried layer 3 corresponding to the corners of the chip 2 are rounded (rounded).
  • a sealing layer 5-6 is provided to cover the buried layer 3 and seam portion 4.
  • an auxiliary layer 6 is provided to cover the sealing layer 5.
  • a structure similar to that shown in FIGS. 108 and 109 described above is obtained, except that the buried layer 3 in the portions corresponding to the corners of the chip 2 are rounded.
  • the lithography, the subsequent film formation of the buried layer 3, and the self-stop CMP process may be omitted.
  • the surface 3a of the buried layer 3 may have a concave portion 3c1 and a convex portion 3c2. This will be explained with reference to FIGS. 120 and 121.
  • 120 and 121 are diagrams showing examples of CMP. Note that for ease of understanding, illustration of the seam portion 4 is omitted.
  • FIG. 120 schematically shows the Self-stop CMP performed in FIGS. 113 and 116 described above.
  • the upper part of the buried layer 3 for example, an oxide film such as SiO2
  • the corner portion 3h is removed.
  • the buried layer 3 has a concave portion 3c1 and a convex portion 3c2.
  • the remaining portions of the corner portions 3h that are not cut, the slits that occur between the remaining corner portions, the seam portions 4, etc. may become the recessed portions 3c1 and the convex portions 3c2.
  • FIG. 121 schematically shows the CMP performed in FIG. 117 described above.
  • the upper part of the buried layer 3 is polished using a polishing PAD.
  • the ceria abrasive grains Pa are not adsorbed to the buried layer 3 and exist freely.
  • slurry pools are generated in the concave portions 3c1 and convex portions 3c2 of the buried layer 3 located above the corners of the chip 2, local stress increases, and polishing progresses. Polishing of the flat portion at the tip of the convex portion 3c2 having a relatively wide width (length in the XY plane direction) is inhibited by the effect of the additive Ad.
  • the buried layer 3 comes to have a recess 3c1 and a projection 3c2 in the manufacturing process.
  • the sealing layer 5-6 resin layer
  • the recess 3c1 and the projection 3c2 are absorbed and a flat surface 5-6a is obtained.
  • FIG. 122 is a diagram showing an example of a schematic configuration of a photodetection device according to a 25th embodiment.
  • the photodetecting device 100 includes a resin layer 15 instead of the sealing layer 5.
  • the resin layer 15 is an oxidized layer or an organic layer, similar to the sealing layer 5-6 described above.
  • the material of the resin layer 15 may be the same as the material of the sealing layer 5-6.
  • the resin layer 15 is provided between the chip 2 and the buried layer 3.
  • the resin layer 15 is provided to cover the substrate 1 and the side surfaces of the chip 2.
  • the resin layer 15 not only the side surface of the chip 2 but also the surface 2a may be covered with the resin layer 15.
  • the shape of the chip 2 portion for example, the shape of the stepped portion with respect to the substrate 1 becomes gentle. Accordingly, the seam portion 4 is less likely to occur. Even if a seam portion 4 occurs, the auxiliary layer 6 functions as a sealing layer that covers the buried layer 3 and the seam portion 4, thereby suppressing communication of the seam portion 4 to the outside, as explained above. be able to.
  • 123 to 128 are diagrams illustrating an example of a method for manufacturing a photodetecting device.
  • chips 2 are provided on a substrate 1, and a resin layer 15 is provided to cover them.
  • the buried layer 3 is provided so as to cover the resin layer 15 (also the surface 2a of the chip 2 in this example).
  • no seam portion 4 is generated within the buried layer 3.
  • the buried layer 3 is removed by a lithography process including dry etching or the like so as to leave the corner 3h.
  • a buried layer 3 is further provided. As shown in FIG. 127, the corner 3h is removed by CMP (Self-stop CMP). As shown in FIG. 128, the upper part of the buried layer 3 is polished and cleaned by CMP. Thereafter, by providing the auxiliary layer 6 so as to cover the buried layer 3, the structure shown in FIG. 122 described above is obtained.
  • CMP Self-stop CMP
  • the sealing layer 5-6 may be a resin layer (for example, an oxide layer or an organic layer).
  • the surface 3a of the buried layer 3 may have a recess 3c1, and the sealing layer 5-6 may be provided to fill the recess 3c1.
  • the surface 5-6a of the sealing layer 5-6 may be a flat surface.
  • the sealing layer 5-6 which is an organic layer, may have heat resistance of 400° C. or higher.
  • the material of the organic layer may include at least one of polyimide, siloxane, and silicone. This makes it possible to withstand heat, for example, even when exposed to heat of about 400° C. in a post-process.
  • the photodetector 100 may include the resin layer 15 (for example, an oxide layer or an organic layer) provided between the chip 2 and the buried layer 3. Thereby, the occurrence of seam portions 4 can be suppressed.
  • the resin layer 15 for example, an oxide layer or an organic layer
  • the resin layer 15 may have the same characteristics as the sealing layer 5-6 described above.
  • the resin layer 15, which is an organic layer may have heat resistance of 400° C. or higher.
  • the material of the organic layer may include at least one of polyimide, siloxane, and silicone. This makes it possible to withstand heat, for example, even when exposed to heat of about 400° C. in a post-process.
  • the present technology can also have the following configuration.
  • at least a portion of the seam portion is a void;
  • the sealing layer includes an extension portion that extends into the seam portion so as to fill at least a portion of the seam portion.
  • the material of the sealing layer includes a low permeability material.
  • the material of the sealing layer includes a low Young's modulus material.
  • the chip includes a first chip and a second chip that are spaced apart from each other,
  • the seam part includes a first seam part caused by the first chip and a second seam part caused by the second chip, the first seam part and the second seam part are connected to each other,
  • an additional layer provided between the chip and the buried layer;
  • (10) comprising an auxiliary layer provided to cover the sealing layer;
  • the auxiliary layer has a laminated structure, The photodetector according to (10).
  • the chip includes at least one of a logic chip, a memory chip, and an AI (Artificial Intelligence) chip.
  • the photodetector according to any one of (1) to (11).
  • An imaging device configured to include a plurality of pixels, The photodetector according to any one of (1) to (12).
  • a filter layer provided on the opposite side of the chip and the buried layer with the substrate in between; a lens layer provided on the opposite side of the substrate with the filter layer in between; Equipped with The photodetector according to (13).
  • an additional substrate provided between the substrate and the buried layer; The photodetector according to any one of (1) to (14).
  • the chip includes two chips arranged adjacent to each other with an interval, The buried layer includes wiring provided between the two chips, The photodetector according to any one of (1) to (15).
  • a supporting substrate that is provided on the opposite side of the substrate with the sealing layer in between and directly or indirectly supports the sealing layer; a through via that penetrates the buried layer, the sealing layer, and the support substrate; Equipped with The photodetector according to any one of (1) to (16).
  • the chip is a first chip; a second chip having a thickness greater than the thickness of the first chip; including;
  • the seam portion is a first seam extending from the first chip toward the surface of the buried layer; a second seam extending from the second chip toward the surface of the buried layer; including; The second seam portion extends closer to the surface of the buried layer than the first seam portion.
  • the chip is a first chip; including a second chip and a third chip stacked in order, The second chip and the third chip have an overall thickness greater than the thickness of the first chip,
  • the seam portion is a first seam extending from the first chip toward the surface of the buried layer; a second seam extending from the second chip toward the surface of the buried layer; including; The second seam portion extends closer to the surface of the buried layer than the first seam portion.
  • the photodetector according to any one of (1) to (18).
  • the sealing layer includes an extension portion that extends into the second seam portion so as to fill at least a portion of the second seam portion.
  • the photodetecting device further includes a bonding layer provided between the lower chip and the upper chip,
  • the embedded layer is a lower buried layer provided to cover a side surface of the lower chip; an upper buried layer provided to cover the upper chip and the bonding layer; including;
  • the seam portion is a lower seam generated within the lower buried layer and extending to a surface of the lower buried layer; an upper seam occurring within the upper buried layer and extending to a surface of the upper buried layer; including;
  • the bonding layer is provided to cover the lower buried layer and the lower seam portion,
  • the sealing layer is provided to cover the upper buried layer and the upper seam part,
  • the photodetector according to any one of (1) to (21).
  • the chip further includes a lower chip and a dummy chip provided on opposite sides of the bonding layer, The upper buried layer is provided to cover the upper chip, the dummy chip, and the bonding layer.
  • the sealing layer is a first portion covering the seam portion; a second portion that does not cover the seam portion; including; The back surface of the first portion is located below the back surface of the second portion.
  • a surface of the first portion is located at the same height as a surface of the second portion; The photodetector according to (24).
  • the sealing layer has a laminated structure in which a plurality of layers are laminated.
  • the plurality of layers of the sealing layer include an inorganic layer and an organic layer.
  • the photodetector according to (27). a dummy chip arranged adjacent to the chip with a space therebetween; The buried layer is provided to cover the chip and the dummy chip, The seam portion extends to the surface of the buried layer in a portion between the chip and the dummy chip.
  • the seam portion extends along the height direction of the chip and the dummy chip.
  • the chip includes two chips spaced apart from each other, The dummy chip is provided between the two chips, The photodetector according to (29) or (30).
  • the chip has a shape whose width decreases toward the surface of the chip, The photodetector according to any one of (1) to (31).
  • the edge of the chip has a tapered shape or a round shape on the surface of the chip, The photodetector according to (32).
  • the seam portion extends along the height direction of the chip.
  • the seam portion has a shape whose width changes as it progresses in its extending direction.
  • the photodetection device according to any one of (1) to (34).
  • the seam portion is a central portion located at the center in the extending direction of the seam portion; an end located at the end in the extending direction of the seam part; including; The central portion has a width greater than the width of the end portions.
  • the photodetector according to (35). When viewed in plan, the dummy chip extends so as to face the side surface of the chip, and has a length in the extending direction that is at least half the length of the side surface of the opposing chip.
  • the photodetector according to any one of (29) to (36).
  • the dummy chip When viewed from above, the dummy chip is arranged to sandwich the chip, The photodetector according to any one of (29) to (37). (39) The dummy chip includes two or more dummy chips. The photodetector according to any one of (29) to (38). (40) The material of the dummy chip includes the same material as the material of the chip, The photodetector according to any one of (29) to (39). (41) the dummy chip has the same height as the chip; The photodetector according to any one of (29) to (40). (42) The chip includes two or more chips. The photodetector according to any one of (29) to (41).
  • the dummy chip When viewed in plan, the dummy chip extends continuously so as to surround the chip, The photodetector according to any one of (29) to (42). (44) When the photodetection device is viewed from the side, the dummy chip has a side surface exposed from the buried layer. The photodetector according to any one of (29) to (43). (45) At least a portion of the seam portion is filled with a material different from the material of the buried layer, The sealing layer is a layer having a thermal conductivity higher than that of silicon, The photodetector according to any one of (1) to (44).
  • the sealing layer is a metal layer, The photodetector according to (45) or (46).
  • the sealing layer is a first portion of the buried layer and the chip that covers the buried layer; a second portion of the embedded layer and the chip that covers the chip; including; The first portion has insulating properties, the second portion has a thermal conductivity higher than that of silicon;
  • the photodetector according to any one of (45) to (48). comprising a compound layer provided between the chip and the sealing layer, the compound layer is a silicide layer, The photodetector according to any one of (45) to (49).
  • the sealing layer is a layer in which a metal structure is provided within an insulator.
  • the sealing layer is a resin layer.
  • the surface of the buried layer has a recess, The sealing layer is provided to fill the recess, The photodetector according to (52).
  • the surface of the sealing layer is a flat surface.
  • the resin layer is an oxidized layer or an organic layer, The photodetector according to any one of (52) to (54).
  • the organic layer has heat resistance of 400° C. or higher, The photodetector according to (55).
  • the material of the organic layer includes at least one of polyimide, siloxane, and silicone. The photodetector according to (56).
  • the resin layer is an oxidized layer or an organic layer, The photodetector according to (58).
  • the organic layer has heat resistance of 400° C. or higher, The photodetector according to (59).
  • the material of the organic layer includes at least one of polyimide, siloxane, and silicone. The photodetector according to (60).

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Abstract

This light detection device comprises: a substrate that includes a light detection element; chips that are provided to the substrate; a buried layer that is provided so as to cover the chips; a seam portion that occurs in the buried layer and extends to the surface of the buried layer; and a sealing layer that is provided so as to cover the buried layer and the seam portion.

Description

光検出装置light detection device
　本開示は、光検出装置に関する。 The present disclosure relates to a photodetection device.
　基板上の段差に起因して、基板を覆うように設けられた層にシーム部が発生することが知られている。例えば特許文献１は、積層された２つの層それぞれのシーム部を不連続にすることで、シーム部の外部への連通を抑制する技術を開示する。 It is known that a seam occurs in a layer provided to cover a substrate due to a step on the substrate. For example, Patent Document 1 discloses a technique for suppressing communication of the seam portions to the outside by making the seam portions of two stacked layers discontinuous.
国際公開第２０１７／１８３３９０号International Publication No. 2017/183390
　光検出素子を含む基板に対して設けられたチップを覆うように層が設けられた構成を備える光検出装置がある。チップが与える段差に起因してシーム部が発生し得る。シーム部の外部への連通を抑制する手法を検討する余地が依然として残る。 There is a photodetection device that has a structure in which a layer is provided so as to cover a chip provided on a substrate containing a photodetection element. Seams may occur due to the step provided by the chip. There is still room to consider ways to suppress communication of the seam portion to the outside.
　本開示の一側面は、シーム部の外部への連通を抑制する。 One aspect of the present disclosure suppresses communication of the seam portion to the outside.
　本開示の一側面に係る光検出装置は、光検出素子を含む基板と、基板に対して設けられたチップと、チップを覆うように設けられた埋め込み層と、埋め込み層内に発生し、埋め込み層の表面まで延在しているシーム部と、埋め込み層及びシーム部を覆うように設けられた封止層と、を備える。 A photodetection device according to one aspect of the present disclosure includes a substrate including a photodetection element, a chip provided to the substrate, an embedded layer provided to cover the chip, and a photodetector generated in the embedded layer. It includes a seam portion extending to the surface of the layer, and a sealing layer provided so as to cover the buried layer and the seam portion.
第１実施形態に係る光検出装置の概略構成の例を示す図である。FIG. 1 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a first embodiment. 第２実施形態に係る光検出装置の概略構成の例を示す図である。FIG. 3 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a second embodiment. 第４実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 4th embodiment. 第５実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 5th embodiment. 第６実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 6th embodiment. 第６実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 6th embodiment. 第７実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 7th embodiment. 第８実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning an 8th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 応用例に係る光検出装置の概略構成の例を示す図である。FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. 応用例に係る光検出装置の概略構成の例を示す図である。FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. 応用例に係る光検出装置の概略構成の例を示す図である。FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. 応用例に係る光検出装置の概略構成の例を示す図である。FIG. 2 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. 車両制御システムの概略的な構成の一例を示すブロック図である。FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system. 車外情報検出部及び撮像部の設置位置の一例を示す説明図である。FIG. 2 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection section and an imaging section. 第９実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 9th embodiment. 第９実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 9th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 変形例を示す図である。It is a figure showing a modification. 変形例を示す図である。It is a figure showing a modification. 第１０実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 10th embodiment. 第１０実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 10th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 変形例を示す図である。It is a figure showing a modification. 第１１実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning an 11th embodiment. 第１１実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning an 11th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 封止層の概略構成の例を示す図である。FIG. 3 is a diagram showing an example of a schematic configuration of a sealing layer. 第１３実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 13th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 第１４実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 14th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 第１５実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 15th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. ダミーチップの第１配置例を示す図である。FIG. 3 is a diagram showing a first arrangement example of dummy chips. ダミーチップの第１配置例を示す図である。FIG. 3 is a diagram showing a first arrangement example of dummy chips. ダミーチップの効果を示す図である。It is a figure showing the effect of a dummy chip. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ダミーチップの第２配置例を示す図である。FIG. 7 is a diagram showing a second example of arrangement of dummy chips. ダミーチップの効果を示す図である。It is a figure showing the effect of a dummy chip. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ダミーチップの第３配置例を示す図である。FIG. 7 is a diagram showing a third arrangement example of dummy chips. ダミーチップの効果を示す図である。It is a figure showing the effect of a dummy chip. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ダミーチップの第４配置例を示す図である。It is a figure which shows the 4th example of arrangement|positioning of a dummy chip. ダミーチップの効果を示す図である。It is a figure showing the effect of a dummy chip. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ダミーチップの第５配置例を示す図である。It is a figure which shows the 5th example of arrangement|positioning of a dummy chip. ダミーチップ２Ｄの効果を示す図である。It is a figure showing the effect of dummy chip 2D. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ダミーチップの効果を示す図である。It is a figure showing the effect of a dummy chip. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. ダミーチップの第７配置例を示す図である。It is a figure which shows the 7th example of arrangement|positioning of a dummy chip. ダミーチップの効果を示す図である。It is a figure showing the effect of a dummy chip. ウェハの概略構成の例を示す図である。FIG. 2 is a diagram showing an example of a schematic configuration of a wafer. 変形例を示す図である。It is a figure showing a modification. 変形例を示す図である。It is a figure showing a modification. 第１６実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 16th embodiment. 第１７実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 17th embodiment. 第１８実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning an 18th embodiment. 第１９実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 19th embodiment. 第２０実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 20th embodiment. 第２１実施形態に係る光検出装置の概略構成の例を示す図である。FIG. 7 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a twenty-first embodiment. 第２２実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 22nd embodiment. 第２３実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 23rd embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 第２４実施形態に係る光検出装置の概略構成の例を示す図である。FIG. 7 is a diagram showing an example of a schematic configuration of a photodetection device according to a twenty-fourth embodiment. 第２４実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 24th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. ＣＭＰの例を示す図である。FIG. 3 is a diagram showing an example of CMP. ＣＭＰの例を示す図である。FIG. 3 is a diagram showing an example of CMP. 第２５実施形態に係る光検出装置の概略構成の例を示す図である。It is a figure showing an example of a schematic structure of a photodetection device concerning a 25th embodiment. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device. 光検出装置の製造方法の例を示す図である。It is a figure which shows the example of the manufacturing method of a photodetection device.
　以下に、本開示の実施形態について図面に基づいて詳細に説明する。なお、とくに説明がある場合を除き、以下の各実施形態において、同一の要素には同一の符号を付することにより重複する説明を省略する。 Below, embodiments of the present disclosure will be described in detail based on the drawings. Note that, unless otherwise specified, in each of the embodiments below, the same elements are given the same reference numerals and redundant explanation will be omitted.
　以下に示す項目順序に従って本開示を説明する。
　　１．第１実施形態
　　２．第２実施形態
　　３．第３実施形態
　　４．第４実施形態
　　５．第５実施形態
　　６．第６実施形態
　　７．第７実施形態
　　８．第８実施形態
　　９．製造方法の例
　１０．撮像装置への応用例
　１１．効果の例
　１２．移動体への応用例
　１３．第９実施形態
　１４．第１０実施形態
　１５．第１１実施形態
　１６．第１２実施形態
　１７．第１３実施形態
　１８．第１４実施形態
　１９．第１５実施形態
　２０．ダミーチップの配置の例
　２１．第１６実施形態
　２２．第１７実施形態
　２３．第１８実施形態
　２４．第１９実施形態
　２５．第２０実施形態
　２６．第２１実施形態
　２７．第２２実施形態
　２８．第２３実施形態
　２９．撮像装置への応用例
　３０．製造方法の例
　３１．第２４実施形態
　３２．第２５実施形態 The present disclosure will be described according to the order of items shown below.
1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment 7. Seventh embodiment 8. Eighth embodiment 9. Example of manufacturing method 10. Application example to imaging device 11. Example of effect 12. Example of application to mobile objects 13. Ninth embodiment 14. 10th embodiment 15. Eleventh embodiment 16. Twelfth embodiment 17. Thirteenth embodiment 18. Fourteenth embodiment 19. Fifteenth embodiment 20. Example of dummy chip arrangement 21. Sixteenth embodiment 22. Seventeenth embodiment 23. Eighteenth embodiment 24. Nineteenth embodiment 25. 20th embodiment 26. 21st embodiment 27. 22nd embodiment 28. 23rd embodiment 29. Application example to imaging device 30. Example of manufacturing method 31. 24th embodiment 32. 25th embodiment
１．第１実施形態
　図１は、第１実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００の断面が模式的に示される。光検出装置１００は、基板１と、チップ２と、埋め込み層３と、シーム部４と、封止層５と、補助層６と、支持基板７とを含む。なお、矛盾の無い範囲において、「層」は、「膜」、「部材」等に適宜読み替えられてよい。また、「設ける」は、「形成する、「配置する」等に適宜読み替えられてよい。 1. First Embodiment FIG. 1 is a diagram showing an example of a schematic configuration of a photodetection device according to a first embodiment. A cross section of a photodetector 100 is schematically shown. The photodetecting device 100 includes a substrate 1 , a chip 2 , a buried layer 3 , a seam portion 4 , a sealing layer 5 , an auxiliary layer 6 , and a support substrate 7 . Note that, within the scope of consistency, "layer" may be read as "film", "member", etc. as appropriate. Further, "provide" may be read as "form", "arrange", etc. as appropriate.
　図において、ＸＹＺ座標系も図示される。Ｚ軸方向は、基板や層の厚さ方向に相当する。Ｘ軸方向及びＹ軸方向（ＸＹ平面方向）は、基板や層の面方向に相当する。基板１及び支持基板７は、互いに対向している。この例では、基板１及び支持基板７のうち、基板１がＺ軸負方向側に位置し、支持基板７がＺ軸正方向側に位置している。チップ２、埋め込み層３、シーム部４、封止層５及び補助層６は、基板１と支持基板７との間に位置している。 In the figure, an XYZ coordinate system is also illustrated. The Z-axis direction corresponds to the thickness direction of the substrate or layer. The X-axis direction and the Y-axis direction (XY plane direction) correspond to the plane direction of the substrate or layer. The substrate 1 and the support substrate 7 are opposed to each other. In this example, of the substrate 1 and the support substrate 7, the substrate 1 is located on the negative side of the Z-axis, and the support substrate 7 is located on the positive side of the Z-axis. The chip 2 , the buried layer 3 , the seam 4 , the sealing layer 5 and the auxiliary layer 6 are located between the substrate 1 and the support substrate 7 .
　光検出装置１００は、配線層を含む。配線層に設けられた配線を、いずれも配線Ｌと称し図示する。配線Ｌの材料の例は、銅（Ｃｕ）等である。なお、異なる配線層の配線Ｌどうしを接続するいくつかのビアも、配線Ｌと同じハッチングで図示される。 The photodetector 100 includes a wiring layer. All wiring provided in the wiring layer is referred to as wiring L and illustrated. An example of the material of the wiring L is copper (Cu) or the like. Note that some vias connecting the wirings L in different wiring layers are also shown with the same hatching as the wirings L.
　基板１は、例えばシリコン（Ｓｉ）半導体基板等の半導体基板であり、光検出素子１ｐを含む。光検出素子の例は、ＰＤ（Photo　Diode）等の光電変換素子であり、例えばＸＹ平面方向にアレイ状に配置された複数の光電変換素子が、光検出素子１ｐに相当し得る。図示しないが、各光電変換素子を駆動したり、各光電変換素子の受光光量に応じた電気信号を取り出したりするためのトランジスタ等の回路素子も、基板１に含まれる。そのような回路素子を含む回路を、画素回路とも称する。 The substrate 1 is a semiconductor substrate such as a silicon (Si) semiconductor substrate, and includes a photodetector element 1p. An example of the photodetection element is a photoelectric conversion element such as a PD (Photo Diode). For example, a plurality of photoelectric conversion elements arranged in an array in the XY plane direction may correspond to the photodetection element 1p. Although not shown, the substrate 1 also includes circuit elements such as transistors for driving each photoelectric conversion element and extracting an electric signal according to the amount of light received by each photoelectric conversion element. A circuit including such a circuit element is also referred to as a pixel circuit.
　基板１の面のうち、Ｚ軸正方向側の面を、表面１ａと称し図示する。Ｚ軸負方向側の面を、裏面１ｂと称し図示する。例示される光検出装置１００は、基板１の裏面１ｂに入射した光を検出する裏面照射型の光検出装置である。 Among the surfaces of the substrate 1, the surface on the Z-axis positive direction side is referred to as a surface 1a and illustrated. The surface on the negative side of the Z-axis is referred to as a back surface 1b and illustrated. The illustrated photodetector 100 is a backside illumination type photodetector that detects light incident on the backside 1b of the substrate 1.
　基板１は、表面１ａ側に配線層を有する。基板１の配線層の配線Ｌは、画素回路の一部を構成し得る。例示される基板１の配線層は多層配線層であり、いくつかの配線Ｌが表面１ａに露出している。 The substrate 1 has a wiring layer on the front surface 1a side. The wiring L in the wiring layer of the substrate 1 may constitute a part of a pixel circuit. The wiring layer of the illustrated substrate 1 is a multilayer wiring layer, and some wirings L are exposed on the surface 1a.
　チップ２は、基板１に対して設けられる。基板１に対して設けられるとは、基板１に直接設けられることだけでなく、別の要素（例えば後述の図２１の追加基板１２）を介して設けられることを含む意味に解されてよい。図１に示される例では、チップ２は、基板１に直接設けられ、より具体的には、基板１の表面１ａ上に設けられる。チップ２の実装面を、実装面２ｂと称し図示する。チップ２は、実装面２ｂ側に配線層を有する。例示されるチップ２の配線層は多層配線層であり、いくつかの配線Ｌが実装面２ｂに露出している。 The chip 2 is provided on the substrate 1. Being provided on the substrate 1 may be understood to include not only being provided directly on the substrate 1, but also being provided via another element (for example, an additional substrate 12 in FIG. 21, which will be described later). In the example shown in FIG. 1, the chip 2 is provided directly on the substrate 1, more specifically on the surface 1a of the substrate 1. The mounting surface of the chip 2 is shown as a mounting surface 2b. The chip 2 has a wiring layer on the mounting surface 2b side. The wiring layer of the illustrated chip 2 is a multilayer wiring layer, and some wirings L are exposed on the mounting surface 2b.
　チップ２は、チップ２の実装面２ｂが基板１の表面１ａと接触するように、基板１上に設けられる。より具体的に、チップ２は、チップ２の配線Ｌと基板１の配線Ｌとが接触して電気的に接続されるように、基板１に実装される。このような接続は、配線Ｌの材料がＣｕの場合には、Ｃｕ－Ｃｕ接合等とも称される。チップ２の実装面２ｂ及び基板１の表面１ａは、チップ２及び基板１の接合面（チップ接合面）を規定する。 The chip 2 is provided on the substrate 1 so that the mounting surface 2b of the chip 2 is in contact with the surface 1a of the substrate 1. More specifically, the chip 2 is mounted on the substrate 1 such that the wiring L of the chip 2 and the wiring L of the substrate 1 are in contact with each other and electrically connected. Such a connection is also called a Cu--Cu bond or the like when the material of the wiring L is Cu. The mounting surface 2b of the chip 2 and the surface 1a of the substrate 1 define a bonding surface between the chip 2 and the substrate 1 (chip bonding surface).
　チップ２は、光検出装置１００に用いることのできるあらゆるチップ（ＩＣ等）であってよい。チップ２の一例は、ロジックチップであり、例えば画素回路のトランジスタを駆動したり、画素回路から取り出された電気信号を処理したりする。チップ２の別の例は、メモリチップであり、例えばロジックチップによる処理で用いられるデータや、処理によって得られたデータを記憶する。チップ２のさらに別の例は、ＡＩ（Artificial　Intelligence）チップであり、学習済みモデル（例えば学習済みのＤＮＮ（Deep　Neural　Network））を用いた演算処理を高速に行うように専用に設計されている。 The chip 2 may be any chip (IC, etc.) that can be used in the photodetector 100. An example of the chip 2 is a logic chip, which drives, for example, a transistor of a pixel circuit or processes an electric signal taken out from the pixel circuit. Another example of the chip 2 is a memory chip, which stores, for example, data used in processing by a logic chip or data obtained by processing. Yet another example of chip 2 is an AI (Artificial Intelligence) chip, which is specifically designed to perform high-speed arithmetic processing using a trained model (for example, a trained DNN (Deep Neural Network)). .
　図１から理解されるように、基板１上に設けられたチップ２が、段差を与える。この例では、チップ２は、基板１の表面１ａを基準としてＺ軸正方向に向かって突出する凸形状を有する段差部である。なお、光検出装置１００に含まれるチップ２の数は、図１に示される例に限られない。光検出装置１００は、１つ以上の任意の数のチップ２を含んでよい。 As understood from FIG. 1, the chip 2 provided on the substrate 1 provides a step. In this example, the chip 2 is a stepped portion having a convex shape protruding toward the positive direction of the Z-axis with respect to the surface 1a of the substrate 1 as a reference. Note that the number of chips 2 included in the photodetector 100 is not limited to the example shown in FIG. 1. The photodetection device 100 may include any number of chips 2, one or more.
　埋め込み層３は、チップ２を覆うように、より具体的にこの例では基板１及びチップ２を覆うように設けられる。埋め込み層３は、チップ２を保護する保護層として機能し得る。例えば、水分、薬品、不所望のガス等のチップ２への侵入が抑制される。埋め込み層３の材料の例は、ＳｉＮ、ＳｉＯ２等である。埋め込み層３の面のうち、Ｚ軸正方向側の面を、表面３ａと称し図示する。Ｚ軸負方向側の面を、裏面３ｂと称し図示する。 The buried layer 3 is provided so as to cover the chip 2, and more specifically, to cover the substrate 1 and the chip 2 in this example. The buried layer 3 can function as a protective layer that protects the chip 2. For example, entry of moisture, chemicals, undesired gases, etc. into the chip 2 is suppressed. Examples of the material of the buried layer 3 are SiN, SiO2 , etc. Among the surfaces of the buried layer 3, the surface on the Z-axis positive direction side is referred to as a surface 3a and illustrated. The surface on the negative side of the Z-axis is referred to as a back surface 3b in the drawing.
　シーム部４は、チップ２が与える段差に起因して、埋め込み層３内に発生する。シーム部４は、例えば段差の立ち上がり部分又はその周辺部分を起点とし、埋め込み層３の表面３ａまで延在している。 The seam portion 4 occurs within the buried layer 3 due to the step provided by the chip 2. The seam portion 4 starts from, for example, the rising portion of the step or its surrounding portion, and extends to the surface 3a of the buried layer 3.
　シーム部４の少なくとも一部は、空隙であってよい。シーム部４が有する空隙を、空隙４ａと称し図示する。図１に示される例では、シーム部４の全部が空隙４ａである。埋め込み層３の表面３ａのうち、シーム部４の位置する部分は開口している。 At least a portion of the seam portion 4 may be a void. The void that the seam portion 4 has is shown as a void 4a. In the example shown in FIG. 1, the entire seam portion 4 is a void 4a. A portion of the surface 3a of the buried layer 3 where the seam portion 4 is located is open.
　封止層５は、埋め込み層３及びシーム部４を覆うように設けられる。シーム部４によって埋め込み層３の表面３ａにできた開口も、封止層５よって塞がれる。封止層５により、シーム部４の外部への連通が抑制される。封止層５の材料は、埋め込み層３の材料と同じであってもよいし、異なっていてもよい。封止層５の材料のいくつかの例は後述する。 The sealing layer 5 is provided so as to cover the buried layer 3 and the seam portion 4. The opening formed in the surface 3a of the buried layer 3 by the seam portion 4 is also closed by the sealing layer 5. The sealing layer 5 prevents the seam portion 4 from communicating with the outside. The material of the sealing layer 5 may be the same as the material of the buried layer 3, or may be different. Some examples of materials for the sealing layer 5 will be described later.
　補助層６は、封止層５を覆うように設けられる。補助層６は、例えば支持基板７との接合に適した材料を含んで構成される。補助層６の材料の例は、主にＳｉＯｘ（ＳｉＮｘ、ＳｉＯＮ、ＳｉＣＮ、ＳｉＯＣ）である。補助層６の面のうち、Ｚ軸正方向側の面を、表面６ａと称し図示する。 The auxiliary layer 6 is provided to cover the sealing layer 5. The auxiliary layer 6 includes, for example, a material suitable for bonding to the support substrate 7. Examples of materials for the auxiliary layer 6 are mainly SiOx (SiNx, SiON, SiCN, SiOC). Among the surfaces of the auxiliary layer 6, the surface on the Z-axis positive direction side is referred to as a surface 6a and illustrated.
　支持基板７は、封止層５を挟んで基板１とは反対側に位置し、封止層５を直接的又は間接的に支持する。支持基板７は、例えばシリコン（Ｓｉ）半導体基板等であってよい。図１に示される例では、支持基板７は、封止層５及び補助層６を挟んで基板１とは反対側に位置し、補助層６を介して封止層５を（すなわち封止層５を間接的に）支持するように、補助層６に貼り合わされる。支持基板７の面のうち、Ｚ軸正方向側の面を、表面７ａと称し図示する。Ｚ軸負方向側の面を、裏面７ｂと称し図示する。支持基板７の裏面７ｂ及び補助層６の表面６ａは、支持基板７及び補助層６の接合面（支持基板接合面）を規定する。なお、光検出装置１００は、補助層６を含まなくてもよく、その場合、支持基板７は、封止層５を直接的に支持するように封止層５に貼り合わされる。 The support substrate 7 is located on the opposite side of the substrate 1 with the sealing layer 5 in between, and supports the sealing layer 5 directly or indirectly. The support substrate 7 may be, for example, a silicon (Si) semiconductor substrate. In the example shown in FIG. It is bonded to the auxiliary layer 6 so as to indirectly support 5). Among the surfaces of the support substrate 7, the surface on the Z-axis positive direction side is referred to as a surface 7a and illustrated. The surface on the negative side of the Z-axis is referred to as a back surface 7b. The back surface 7b of the support substrate 7 and the front surface 6a of the auxiliary layer 6 define a bonding surface between the support substrate 7 and the auxiliary layer 6 (support substrate bonding surface). Note that the photodetecting device 100 may not include the auxiliary layer 6, and in that case, the support substrate 7 is bonded to the sealing layer 5 so as to directly support the sealing layer 5.
　以上で説明した光検出装置１００によれば、埋め込み層３及びシーム部４を覆う封止層５を設けることで、シーム部４の外部への連通を抑制することができる。具体的に、図１に示される例では、シーム部４が、支持基板７との接合面である補助層６の表面６ａまで到達するのを防ぐことができる。仮にシーム部４が補助層６の表面６ａに到達すると、支持基板７との接合面に開口ができてしまい、ボイド発生等によって接合品質が低下する可能性がある。このような接合品質の低下が、光検出装置１００によって抑制される。 According to the photodetection device 100 described above, by providing the sealing layer 5 that covers the embedded layer 3 and the seam portion 4, communication of the seam portion 4 to the outside can be suppressed. Specifically, in the example shown in FIG. 1, it is possible to prevent the seam portion 4 from reaching the surface 6a of the auxiliary layer 6, which is the bonding surface with the support substrate 7. If the seam portion 4 reaches the surface 6a of the auxiliary layer 6, an opening will be formed at the bonding surface with the support substrate 7, and there is a possibility that the bonding quality will be degraded due to the generation of voids or the like. Such deterioration in bonding quality is suppressed by the photodetecting device 100.
　上記の技術をベースとするいくつかの他の実施形態について説明する。矛盾の無い範囲において、各実施形態の技術特徴は適宜組み合わされてよい。 Several other embodiments based on the above technology will be described. The technical features of each embodiment may be combined as appropriate to the extent that there is no contradiction.
２．第２実施形態
　図２は、第２実施形態に係る光検出装置の概略構成の例を示す図である。封止層５は、シーム部４内まで延在する延在部５ａを含む。延在部５ａは、シーム部４の少なくとも一部を埋めるように延在し、図２に示される例では、シーム部４の全部を埋めるように延在している。シーム部４は、空隙４ａ（図１）を有さない。封止層５の材料（延在部５ａの材料）は、低浸透性材料を含む。低浸透性材料の例は、ＳｉＮ系材料等である。ＳｉＮ系材料の例は、ＳｉＮｘ、ＳｉＣＮ、ＳｉＯＮ等である。このような封止層５の延在部５ａがシーム部４を埋めることで、例えばチップ２への水分等の侵入の抑制効果を高めることができる。信頼性向上等にもつながる。 2. Second Embodiment FIG. 2 is a diagram showing an example of a schematic configuration of a photodetection device according to a second embodiment. The sealing layer 5 includes an extension portion 5 a that extends into the seam portion 4 . The extending portion 5a extends so as to fill at least a portion of the seam portion 4, and in the example shown in FIG. 2, extends so as to fill the entire seam portion 4. The seam portion 4 does not have a void 4a (FIG. 1). The material of the sealing layer 5 (the material of the extension portion 5a) includes a low permeability material. Examples of low permeability materials include SiN-based materials. Examples of SiN-based materials are SiNx, SiCN, SiON, etc. By filling the seam portion 4 with the extending portion 5a of the sealing layer 5, the effect of suppressing moisture from entering the chip 2, for example, can be enhanced. This also leads to improved reliability.
３．第３実施形態
　一実施形態において、封止層５の材料は、低ヤング率材料を含む。低ヤング率材料の例は、Ｌｏｗ－ｋ材料、有機材料等である。Ｌｏｗ－ｋ材料の例は、多孔性のＳｉＯ２等である。有機材料の例は、シリコーン、シロキサン、ポリイミド等である。このような封止層５の延在部５ａがシーム部４を埋めることで、例えばチップ間応力を緩和することができる。 3. Third Embodiment In one embodiment, the material of the sealing layer 5 includes a low Young's modulus material. Examples of low Young's modulus materials are low-k materials, organic materials, etc. An example of a low-k material is porous SiO2, etc. Examples of organic materials are silicones, siloxanes, polyimides, etc. By filling the seam portion 4 with the extending portion 5a of the sealing layer 5, for example, inter-chip stress can be alleviated.
４．第４実施形態
　図３は、第４実施形態に係る光検出装置の概略構成の例を示す図である。封止層５の延在部５ａは、シーム部４の一部だけを埋めるように延在している。シーム部４の残部は空隙４ａである。空隙４ａを残すことでチップ間応力を緩和することもできる。 4. Fourth Embodiment FIG. 3 is a diagram showing an example of a schematic configuration of a photodetection device according to a fourth embodiment. The extending portion 5a of the sealing layer 5 extends so as to fill only a portion of the seam portion 4. The remainder of the seam portion 4 is a void 4a. By leaving the void 4a, inter-chip stress can also be alleviated.
　なお、以降では、とくに説明がある場合を除き、封止層５の延在部５ａがシーム部４の全部を埋めるように延在している場合で説明する。 Note that, in the following description, unless otherwise specified, a case will be described in which the extending portion 5a of the sealing layer 5 extends so as to fill the entire seam portion 4.
５．第５実施形態
　図４は、第５実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、側壁部８をさらに含む。側壁部８は、チップ２の側面（側壁）を覆うように設けられる。埋め込み層３は、基板１、チップ２及び側壁部８を覆うように設けられる。側壁部８の材料の例は、無機材料等である。無機材料の例は、主にＳｉＮｘ（ＳｉＯｘ、ＳｉＯＮ、ＳｉＣＮ、ＳｉＯＣ）である。側壁部８を設けることで、チップ２の保護性能をさらに高めることができる。 5. Fifth Embodiment FIG. 4 is a diagram showing an example of a schematic configuration of a photodetection device according to a fifth embodiment. Photodetection device 100 further includes a side wall portion 8 . The side wall portion 8 is provided so as to cover the side surface (side wall) of the chip 2 . The buried layer 3 is provided so as to cover the substrate 1 , the chip 2 , and the sidewall portion 8 . An example of the material of the side wall portion 8 is an inorganic material. Examples of inorganic materials are mainly SiNx (SiOx, SiON, SiCN, SiOC). By providing the side wall portion 8, the protection performance of the chip 2 can be further improved.
６．第６実施形態
　図５及び図６は、第６実施形態に係る光検出装置の概略構成の例を示す図である。２つの異なるチップ２に起因して発生したシーム部４どうしが、互いにつながっている。２つのチップ２のうち、第１のチップを、チップ２－１と称し図示する。第２のチップを、チップ２－２と称し図示する。 6. Sixth Embodiment FIGS. 5 and 6 are diagrams showing an example of a schematic configuration of a photodetecting device according to a sixth embodiment. Seam portions 4 caused by two different chips 2 are connected to each other. Among the two chips 2, the first chip is shown as a chip 2-1. The second chip is designated and illustrated as chip 2-2.
　シーム部４は、シーム部４－１及びシーム部４－２を含む。シーム部４－１は、チップ２－１に起因して発生した第１のシーム部である。シーム部４－２は、チップ２－２に起因して発生した第２のシーム部である。図５に示される例では、シーム部４－１及びシーム部４－２は、埋め込み層３の表面３ａに向かう途中で互いにつながり、埋め込み層３の表面３ａまで延在している。図６に示される例では、シーム部４－１が与える段差及びシーム部４－２がはじめから互いにつながっており、一緒に埋め込み層３の表面３ａまで延在している。例えばこのように互いにつながっているシーム部４－１及びシーム部４－２がある場合でも、それらの外部への連通を抑制することができる。 The seam portion 4 includes a seam portion 4-1 and a seam portion 4-2. The seam portion 4-1 is a first seam portion caused by the chip 2-1. The seam portion 4-2 is a second seam portion caused by the chip 2-2. In the example shown in FIG. 5, the seam portion 4-1 and the seam portion 4-2 are connected to each other on the way to the surface 3a of the buried layer 3, and extend to the surface 3a of the buried layer 3. In the example shown in FIG. 6, the step provided by the seam portion 4-1 and the seam portion 4-2 are connected to each other from the beginning and extend together to the surface 3a of the buried layer 3. For example, even if there are a seam portion 4-1 and a seam portion 4-2 that are connected to each other in this manner, communication between them to the outside can be suppressed.
７．第７実施形態
　図７は、第７実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、追加層９をさらに含む。追加層９は、基板１及びチップ２と、埋め込み層３との間に設けられる。換言すると、追加層９は、基板１及びチップ２を覆うように設けられ、埋め込み層３は、追加層９を覆うように設けられる。追加層９の材料は、埋め込み層３の材料と同じであってもよいし、異なっていてもよい。追加層９の材料の例は、主にＳｉＮｘ（ＳｉＯｘ、ＳｉＯＮ、ＳｉＣＮ、ＳｉＯＣ）である。追加層９は、単層構造を有していてもよいし、積層構造を有していてもよい。追加層９を設けることで、信頼性をさらに向上させることができる。 7. Seventh Embodiment FIG. 7 is a diagram showing an example of a schematic configuration of a photodetection device according to a seventh embodiment. Photodetection device 100 further includes an additional layer 9 . An additional layer 9 is provided between the substrate 1 and the chip 2 and the buried layer 3. In other words, the additional layer 9 is provided so as to cover the substrate 1 and the chip 2 , and the buried layer 3 is provided so as to cover the additional layer 9 . The material of the additional layer 9 may be the same as the material of the buried layer 3 or may be different. Examples of materials for the additional layer 9 are mainly SiNx (SiOx, SiON, SiCN, SiOC). The additional layer 9 may have a single layer structure or a laminated structure. By providing the additional layer 9, reliability can be further improved.
８．第８実施形態
　図８は、第８実施形態に係る光検出装置の概略構成の例を示す図である。補助層６は、積層構造を有する。この例では、補助層６は、３層構造であり、Ｚ軸正方向に、層６１、層６２及び層６３をこの順に含む。層６１、層６２及び層６３それぞれの材料は、互いに異なる材料であってもよいし、同じ材料であってもよい。層数や材料の設計により、反り調整、接合マージン拡大等が可能になる。 8. Eighth Embodiment FIG. 8 is a diagram showing an example of a schematic configuration of a photodetection device according to an eighth embodiment. The auxiliary layer 6 has a laminated structure. In this example, the auxiliary layer 6 has a three-layer structure and includes a layer 61, a layer 62, and a layer 63 in this order in the positive Z-axis direction. The layers 61, 62, and 63 may be made of different materials or the same material. Depending on the number of layers and material design, it is possible to adjust warpage and expand bonding margins.
９．製造方法の例
　図９～図１９は、光検出装置の製造方法の例を示す図である。図９～図１４には、前述の第１実施形態～第４実施形態、及び、第６実施形態～第８実施形態に係る光検出装置１００（図１～図３、及び、図５～図８）の製造方法の例が示される。 9. Example of Manufacturing Method FIGS. 9 to 19 are diagrams illustrating an example of a method of manufacturing a photodetector. FIGS. 9 to 14 show the photodetecting devices 100 (FIGS. 1 to 3, and FIGS. 5 to 3) according to the first to fourth embodiments and the sixth to eighth embodiments described above. An example of the manufacturing method of 8) is shown below.
　図９に示されるように、光検出素子１ｐを含む基板１を準備し、チップ２を基板１上に設ける。図１０に示されるように、基板１及びチップ２を覆うように、埋め込み層３を設ける。チップ２が与える段差に起因して、埋め込み層３内にシーム部４が発生する。この時点では、シーム部４の全体が空隙４ａである。 As shown in FIG. 9, a substrate 1 including a photodetecting element 1p is prepared, and a chip 2 is provided on the substrate 1. As shown in FIG. 10, a buried layer 3 is provided to cover the substrate 1 and the chip 2. A seam portion 4 is generated within the buried layer 3 due to the step provided by the chip 2 . At this point, the entire seam portion 4 is a void 4a.
　前述の第６実施形態（図５、図６）のように、隣り合うチップ２それぞれに対応するシーム部４どうしが繋がる場合もある。前述の第７実施形態（図７）の場合は、基板１及びチップ２を覆うように追加層９（図７）を設けた後で、追加層９を覆うように埋め込み層３を設ける。 As in the aforementioned sixth embodiment (FIGS. 5 and 6), the seam portions 4 corresponding to adjacent chips 2 may be connected to each other. In the case of the seventh embodiment (FIG. 7) described above, after the additional layer 9 (FIG. 7) is provided so as to cover the substrate 1 and the chip 2, the buried layer 3 is provided so as to cover the additional layer 9.
　埋め込み層３の上部（Ｚ軸正方向側の部分）を研磨し、洗浄することで、図１１に示されるように、平坦化された表面３ａが得られる。表面３ａにおいてシーム部４が到達している部分は開口している。この状態で、図１２に示されるように、埋め込み層３を覆うように封止層５を設ける。表面３ａの開口は、封止層５によって塞がれる。 By polishing and cleaning the upper part of the buried layer 3 (the part on the Z-axis positive direction side), a flattened surface 3a is obtained as shown in FIG. The portion of the surface 3a where the seam portion 4 reaches is open. In this state, as shown in FIG. 12, a sealing layer 5 is provided to cover the buried layer 3. The opening in the surface 3a is closed by the sealing layer 5.
　前述の第１実施形態（図１）の場合は、シーム部４の全部が空隙４ａのままである。前述の第２実施形態及び第３実施形態（図２）の場合は、シーム部４の全部が封止層５の材料によって埋められ、その部分が封止層５の延在部５ａになる。前述の第４実施形態（図３）の場合は、シーム部４の一部だけが封止層５の材料によって埋められ、その部分が封止層５の延在部５ａになる。前述の第６実施形態～第８実施形態（図５～図８）の場合は、いずれの態様であってもよい。 In the case of the first embodiment (FIG. 1) described above, the entire seam portion 4 remains the void 4a. In the case of the second and third embodiments (FIG. 2) described above, the entire seam portion 4 is filled with the material of the sealing layer 5, and that portion becomes the extension portion 5a of the sealing layer 5. In the case of the fourth embodiment described above (FIG. 3), only a portion of the seam portion 4 is filled with the material of the sealing layer 5, and that portion becomes the extension portion 5a of the sealing layer 5. In the case of the sixth to eighth embodiments (FIGS. 5 to 8) described above, any aspect may be used.
　図１３に示されるように、封止層５を覆うように補助層６を設ける。その後、補助層６を研磨し、洗浄を行う。シーム部４が封止層５で覆われているので、洗浄を行っても、シーム部４は広がらない。前述の第８実施形態（図８）の場合は、補助層６が積層構造を有するように、複数の層（例えば層６１、層６２及び層６３）が設けられる。図１４に示されるように、支持基板７を補助層６に貼り合わせる。 As shown in FIG. 13, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, the auxiliary layer 6 is polished and cleaned. Since the seam portion 4 is covered with the sealing layer 5, the seam portion 4 does not widen even after cleaning. In the case of the eighth embodiment (FIG. 8) described above, a plurality of layers (eg, layer 61, layer 62, and layer 63) are provided so that the auxiliary layer 6 has a laminated structure. As shown in FIG. 14, the support substrate 7 is bonded to the auxiliary layer 6.
　例えば以上のようにして、前述の実施形態１～実施形態４、及び、実施形態６～実施形態８に係る光検出装置１００を製造することができる。 For example, the photodetecting device 100 according to the first to fourth embodiments and the sixth to eighth embodiments described above can be manufactured as described above.
　図１５～図１９には、前述の第５実施形態（図４）の製造方法の例が示される。基板１を準備し、チップ２を基板１上に設けるところまでは、先に説明した図９と同様である。図１５に示されるように、基板１及びチップ２を覆うように、側壁部８（図４）の材料を設ける。 FIGS. 15 to 19 show an example of the manufacturing method of the fifth embodiment (FIG. 4) described above. The steps up to preparing the substrate 1 and providing the chip 2 on the substrate 1 are the same as those in FIG. 9 described above. As shown in FIG. 15, the material of the side wall portion 8 (FIG. 4) is provided so as to cover the substrate 1 and chip 2.
　図１６に示されるように、チップ２の側面上に上述の材料が残るように、エッチング（例えばドライエッチング）を行う。チップ２の側面上に残った材料が、側壁部８になる。図１７に示されるように、基板１、チップ２及び側壁部８を覆うように、埋め込み層３を設ける。チップ２が与える段差に起因して、埋め込み層３内にシーム部４が発生する。図１８に示されるように、封止層５を覆うように補助層６を設ける。図１９に示されるように、支持基板７を補助層６に貼り合わせる。 As shown in FIG. 16, etching (for example, dry etching) is performed so that the above-mentioned material remains on the side surface of the chip 2. The material remaining on the side surface of the chip 2 becomes the side wall portion 8. As shown in FIG. 17, a buried layer 3 is provided to cover the substrate 1, the chip 2, and the side wall portion 8. A seam portion 4 is generated within the buried layer 3 due to the step provided by the chip 2 . As shown in FIG. 18, an auxiliary layer 6 is provided to cover the sealing layer 5. As shown in FIG. 19, the support substrate 7 is bonded to the auxiliary layer 6.
　例えば以上のようにして、上述の実施形態５に係る光検出装置１００を製造することができる。 For example, the photodetection device 100 according to the fifth embodiment described above can be manufactured as described above.
１０．撮像装置への応用例
　これまで説明した光検出装置１００の応用の一例は、撮像装置である。図２０～図２３を参照して説明する。 10. Application Example to Imaging Device An example of application of the photodetection device 100 described so far is an imaging device. This will be explained with reference to FIGS. 20 to 23.
　図２０は、応用例に係る光検出装置の概略構成の例を示す図である。これまでの図とはＺ軸の向きが逆になっていることに留意されたい。例示される光検出装置１００は、複数の画素１０１を含むように構成された撮像装置である。画素１０１として、緑色光を受光する画素Ｇ、赤色光を受光する画素Ｒ、及び、青色光を受光する画素Ｂが例示される。基板１は、各画素１０１に対応する光電変換素子を含むように構成された基板（イメージセンサ基板）である。光検出装置１００は、フィルタ層１０及びレンズ層１１を含む。 FIG. 20 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. Please note that the direction of the Z axis is reversed from the previous figures. The illustrated photodetection device 100 is an imaging device configured to include a plurality of pixels 101. Examples of the pixel 101 include a pixel G that receives green light, a pixel R that receives red light, and a pixel B that receives blue light. The substrate 1 is a substrate (image sensor substrate) configured to include a photoelectric conversion element corresponding to each pixel 101. Photodetection device 100 includes a filter layer 10 and a lens layer 11.
　フィルタ層１０は、基板１を挟んでチップ２及び埋め込み層３とは反対側に設けられる。この例では、フィルタ層１０は、基板１の裏面１ｂ上に設けられる。フィルタ層１０は、複数の画素１０１に対応する複数のフィルタを含む。画素Ｇに設けられるフィルタを、フィルタ１０Ｇと称し図示する。画素Ｒに設けられるフィルタを、フィルタ１０Ｒと称し図示する。画素Ｂに設けられるフィルタを、フィルタ１０Ｂと称し図示する。フィルタ１０Ｇは、緑色の光を通過させる。フィルタ１０Ｒは、赤色の光を通過させる。フィルタ１０Ｂは、青色の光を通過させる。樹脂等の種々の公知の材料が用いられてよい。 The filter layer 10 is provided on the opposite side of the chip 2 and the buried layer 3 with the substrate 1 in between. In this example, the filter layer 10 is provided on the back surface 1b of the substrate 1. Filter layer 10 includes multiple filters corresponding to multiple pixels 101. A filter provided in pixel G is referred to as a filter 10G and illustrated. The filter provided in pixel R is referred to as a filter 10R and illustrated. The filter provided in pixel B is referred to as filter 10B and illustrated. Filter 10G passes green light. The filter 10R allows red light to pass through. Filter 10B allows blue light to pass through. Various known materials such as resins may be used.
　レンズ層１１は、フィルタ層１０を挟んで基板１とは反対側に設けられる。レンズ層１１は、複数の画素１０１に対応する複数のレンズ１１ａを含む。レンズ１１ａは、フィルタ層１０を介して基板１の光電変換素子に入射する光を集光する集光レンズである。樹脂等の種々の公知の材料が用いられてよい。 The lens layer 11 is provided on the opposite side of the substrate 1 with the filter layer 10 in between. The lens layer 11 includes a plurality of lenses 11a corresponding to the plurality of pixels 101. The lens 11a is a condenser lens that condenses light that is incident on the photoelectric conversion element of the substrate 1 via the filter layer 10. Various known materials such as resins may be used.
　例えば上記の構成を備える光検出装置１００を、撮像装置として用いることができる。他の構成も可能であり、いくつかの例について、図２１～図２３を参照して説明する。 For example, the photodetection device 100 having the above configuration can be used as an imaging device. Other configurations are possible, and some examples are described with reference to FIGS. 21-23.
　図２１は、応用例に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、追加基板１２をさらに含む。追加基板１２は、基板１と埋め込み層３との間に設けられる。追加基板１２は、基板１と支持基板７との間に位置する中間基板ともいえる。追加基板１２の面のうち、Ｚ軸正方向側の面を、表面１２ａと称し図示する。Ｚ軸負方向側の面を、裏面１２ｂと称し図示する。追加基板１２の表面１２ａが埋め込み層３の裏面３ｂに接触し、追加基板１２の裏面１２ｂが基板１の表面１ａに接触している。 FIG. 21 is a diagram illustrating an example of a schematic configuration of a photodetection device according to an application example. Photodetection device 100 further includes an additional substrate 12 . Additional substrate 12 is provided between substrate 1 and buried layer 3 . The additional substrate 12 can also be said to be an intermediate substrate located between the substrate 1 and the support substrate 7. Among the surfaces of the additional substrate 12, the surface on the Z-axis positive direction side is referred to as a surface 12a and illustrated. The surface on the negative side of the Z-axis is referred to as a back surface 12b. The front surface 12a of the additional substrate 12 is in contact with the back surface 3b of the buried layer 3, and the back surface 12b of the additional substrate 12 is in contact with the front surface 1a of the substrate 1.
　追加基板１２は、表面１２ａ側及び裏面１２ｂ側それぞれに配線層を有する。例示される追加基板１２の配線層は多層配線層であり、いくつかの配線Ｌが表面１２ａ又は裏面１２ｂに露出している。 The additional board 12 has wiring layers on each of the front surface 12a side and the back surface 12b side. The illustrated wiring layer of the additional board 12 is a multilayer wiring layer, and some wiring L is exposed on the front surface 12a or the back surface 12b.
　チップ２は、チップ２の実装面２ｂが追加基板１２の表面１２ａと接触するように、追加基板１２上に設けられる。より具体的に、チップ２は、チップ２の配線Ｌと追加基板１２の配線Ｌとが接触して電気的に接続されるように、追加基板１２に実装される。チップ２の実装面２ｂ及び追加基板１２の表面１２ａは、チップ２及び追加基板１２の接合面（チップ接合面）を規定する。 The chip 2 is provided on the additional substrate 12 such that the mounting surface 2b of the chip 2 is in contact with the surface 12a of the additional substrate 12. More specifically, the chip 2 is mounted on the additional substrate 12 such that the wiring L of the chip 2 and the wiring L of the additional substrate 12 are in contact and electrically connected. The mounting surface 2b of the chip 2 and the surface 12a of the additional substrate 12 define a bonding surface (chip bonding surface) between the chip 2 and the additional substrate 12.
　追加基板１２は、追加基板１２の配線Ｌと基板１の配線Ｌとが電気的に接触して接続されるように、基板１に貼り合わされる。基板１の表面１ａ及び追加基板１２の裏面１２ｂは、基板１及び追加基板１２の接合面（Ｆ２Ｆ接合面）を規定する。 The additional board 12 is bonded to the board 1 so that the wiring L of the additional board 12 and the wiring L of the board 1 are electrically contacted and connected. The front surface 1a of the substrate 1 and the back surface 12b of the additional substrate 12 define a bonding surface (F2F bonding surface) between the substrate 1 and the additional substrate 12.
　追加基板１２は、貫通ビア１２ｖを含む。貫通ビア１２ｖは、追加基板１２の表面１２ａ側の配線層と、追加基板１２の裏面１２ｂ側の配線層とを接続するように、それらの間の部分（基体）を貫通する。追加基板１２の配線層も利用することで、より多くの配線や回路素子を形成することができる。例えば光検出装置１００をさらに高機能化することができる。なお、２つ以上の追加基板１２が設けられてもよい。 The additional board 12 includes through vias 12v. The through via 12v penetrates the portion (substrate) between the wiring layer on the front surface 12a side of the additional board 12 and the wiring layer on the back surface 12b side of the additional board 12 so as to connect them. By also utilizing the wiring layer of the additional substrate 12, more wiring and circuit elements can be formed. For example, the functionality of the photodetection device 100 can be further improved. Note that two or more additional substrates 12 may be provided.
　図２２及び図２３は、応用例に係る光検出装置の概略構成の例を示す図である。図２２に示されるように、間隔をあけて隣り合うように配置されたチップ２どうしの間にも、配線Ｌや構造体が設けられる。構造体として、貫通ビアＶが例示される。 FIGS. 22 and 23 are diagrams illustrating an example of a schematic configuration of a photodetection device according to an application example. As shown in FIG. 22, wiring L and structures are also provided between chips 2 that are arranged adjacent to each other with an interval. A through via V is exemplified as the structure.
　具体的に、図２２に示されるように、埋め込み層３及び補助層６も、配線Ｌを含む。いくつかの配線Ｌは、隣り合うチップ２どうしの間に設けられる。埋め込み層３及び補助層６にも配線Ｌを設けることで、光検出装置１００のさらなる高機能化が可能になる。配線Ｌはシーム部４に設けられていてもよく、その分レイアウト自由度が向上する。 Specifically, as shown in FIG. 22, the buried layer 3 and the auxiliary layer 6 also include the wiring L. Some wiring lines L are provided between adjacent chips 2. By providing the wiring L in the buried layer 3 and the auxiliary layer 6 as well, it is possible to further improve the functionality of the photodetecting device 100. The wiring L may be provided in the seam portion 4, and the degree of freedom in layout is improved accordingly.
　貫通ビアＶは、埋め込み層３、封止層５、補助層６及び支持基板７を貫通する。貫通ビアＶを介して、支持基板７の表面７ａから追加基板１２の表面１２ａ側の配線層への電気的なアクセスが可能になる。貫通ビアＶは、コンタクトビアともいえる。埋め込み層３において、少なくとも一部の貫通ビアＶは、隣り合うチップ２どうしの間に位置している。また、貫通ビアＶは、シーム部４を貫通していてよい。具体的に、図２３には、平面レイアウトが模式的に示される。平面視したときに（Ｚ軸方向にみたときに）、チップ２の周辺に配置された複数の貫通ビアＶのうちのいくつかの貫通ビアＶが、シーム部４と重なっている。さまざまな位置に貫通ビアＶを設けることができ、その分レイアウト自由度が向上する。 The through via V penetrates the buried layer 3, the sealing layer 5, the auxiliary layer 6, and the support substrate 7. Through the through-vias V, electrical access is made possible from the surface 7a of the support substrate 7 to the wiring layer on the surface 12a side of the additional substrate 12. The through via V can also be called a contact via. In the buried layer 3, at least some of the through vias V are located between adjacent chips 2. Further, the through via V may pass through the seam portion 4. Specifically, FIG. 23 schematically shows a planar layout. When viewed in plan (when viewed in the Z-axis direction), some of the through-vias V out of the plurality of through-vias V arranged around the chip 2 overlap with the seam portion 4 . Through vias V can be provided at various positions, and the degree of freedom in layout is improved accordingly.
１１．効果の例
　以上で説明した技術は、例えば次のように特定される。開示される技術の１つは、光検出装置１００である。図１等を参照して説明したように、光検出装置１００は、光検出素子１ｐを含む基板１と、基板１に対して設けられたチップ２と、チップ２を覆うように設けられた埋め込み層３と、埋め込み層３内に発生し、埋め込み層３の表面３ａまで延在しているシーム部４と、埋め込み層３及びシーム部４を覆うように設けられた封止層５と、を備える。 11. Examples of effects The techniques described above are specified as follows, for example. One of the techniques disclosed is a photodetection device 100. As described with reference to FIG. 1 etc., the photodetecting device 100 includes a substrate 1 including a photodetecting element 1p, a chip 2 provided on the substrate 1, and an embedded portion provided to cover the chip 2. A layer 3, a seam portion 4 generated within the buried layer 3 and extending to the surface 3a of the buried layer 3, and a sealing layer 5 provided so as to cover the buried layer 3 and the seam portion 4. Be prepared.
　上記の光検出装置１００によれば、埋め込み層３及びシーム部４を覆うように封止層５を設けることで、シーム部４の外部への連通を抑制することができる。 According to the above photodetecting device 100, by providing the sealing layer 5 to cover the embedded layer 3 and the seam portion 4, communication of the seam portion 4 to the outside can be suppressed.
　図１等を参照して説明したように、光検出装置１００は、封止層５を挟んで基板１とは反対側に位置し、封止層５を直接的又は間接的に支持する支持基板７を備えてよい。封止層５で覆われたシーム部４が支持基板７との接合面までは到達しないので、ボイド発生等による接合品質の低下を抑制することができる。 As described with reference to FIG. 1 and the like, the photodetecting device 100 includes a support substrate that is located on the opposite side of the substrate 1 with the sealing layer 5 in between and supports the sealing layer 5 directly or indirectly. 7 may be provided. Since the seam portion 4 covered with the sealing layer 5 does not reach the bonding surface with the support substrate 7, deterioration in bonding quality due to void generation etc. can be suppressed.
　図１及び図３等を参照して説明したように、シーム部４の少なくとも一部は、空隙４ａであってよい。これにより、例えばチップ間応力を緩和することができる。 As described with reference to FIGS. 1 and 3, at least a portion of the seam portion 4 may be a void 4a. Thereby, for example, inter-chip stress can be alleviated.
　図２及び図３等を参照して説明したように、封止層５は、シーム部４の少なくとも一部を埋めるようにシーム部４内まで延在する延在部５ａを含んでよい。封止層５の材料は、低浸透性材料を含んでよい。これにより、例えばチップ２への水分等の侵入の抑制効果を高めることができる。封止層５の材料は、低ヤング率材料を含んでよい。これにより、例えばチップ間応力を緩和することができる。 As described with reference to FIGS. 2, 3, etc., the sealing layer 5 may include the extending portion 5a that extends into the seam portion 4 so as to fill at least a portion of the seam portion 4. The material of the sealing layer 5 may include a low permeability material. Thereby, for example, the effect of suppressing moisture and the like from entering the chip 2 can be enhanced. The material of the sealing layer 5 may include a low Young's modulus material. Thereby, for example, inter-chip stress can be alleviated.
　図４等を参照して説明したように、光検出装置１００は、チップ２の側面を覆うように設けられた側壁部８を備えてよい。これにより、チップ２の保護性能をさらに高めることができる。 As described with reference to FIG. 4 and the like, the photodetecting device 100 may include the side wall portion 8 provided so as to cover the side surface of the chip 2. Thereby, the protection performance of the chip 2 can be further improved.
　図５及び図６等を参照して説明したように、チップ２は、互いに離間して設けられたチップ２－１（第１のチップ）及びチップ２－２（第２のチップ）を含み、シーム部４は、チップ２－１に起因して発生したシーム部４－１（第１のシーム部）及びチップ２－２に起因して発生したシーム部４－２（第２のシーム部）を含み、シーム部４－１及びシーム部４－２は、互いにつながっていてよい。例えばこのように互いにつながっているシーム部４－１及びシーム部４－２がある場合でも、それらの外部への連通を抑制することができる。 As described with reference to FIGS. 5 and 6, the chip 2 includes a chip 2-1 (first chip) and a chip 2-2 (second chip) that are spaced apart from each other, The seam portion 4 includes a seam portion 4-1 (first seam portion) caused by the chip 2-1 and a seam portion 4-2 (second seam portion) caused by the chip 2-2. The seam portion 4-1 and the seam portion 4-2 may be connected to each other. For example, even if there are a seam portion 4-1 and a seam portion 4-2 that are connected to each other in this manner, communication between them to the outside can be suppressed.
　図７等を参照して説明したように、光検出装置１００は、チップ２と埋め込み層３との間に設けられた追加層９を備えてよい。これにより、信頼性をさらに向上させることができる。 As described with reference to FIG. 7 and the like, the photodetector 100 may include the additional layer 9 provided between the chip 2 and the buried layer 3. Thereby, reliability can be further improved.
　図１及び図８等を参照して説明したように、光検出装置１００は、封止層５を覆うように設けられた補助層６を備えてよい。これにより、例えば支持基板７との接合を行い易くすることができる。補助層６は、積層構造を有してよい。層数や材料の設計により、反り調整、接合マージン拡大等が可能になる。 As described with reference to FIGS. 1, 8, etc., the photodetector 100 may include the auxiliary layer 6 provided to cover the sealing layer 5. This makes it easier to bond to the support substrate 7, for example. The auxiliary layer 6 may have a laminated structure. Depending on the number of layers and material design, it is possible to adjust warpage and expand bonding margins.
　図１等を参照して説明したように、チップ２は、ロジックチップ、メモリチップ及びＡＩ（Artificial　Intelligence）チップの少なくとも１つを含んでよい。例えばこのようなさまざまなチップ２が設けられ高機能化された光検出装置を提供することができる。 As described with reference to FIG. 1 and the like, the chip 2 may include at least one of a logic chip, a memory chip, and an AI (Artificial Intelligence) chip. For example, it is possible to provide a highly functional photodetection device provided with such various chips 2.
　図２０等を参照して説明したように、光検出装置１００は、複数の画素１０１を含むように構成された撮像装置であってよい。光検出装置１００は、基板１を挟んでチップ２及び埋め込み層３とは反対側に設けられたフィルタ層１０と、フィルタ層１０を挟んで基板とは反対側に設けられたレンズ層１１と、を備えてよい。光検出装置１００を撮像装置に応用することができる。 As described with reference to FIG. 20 and the like, the photodetection device 100 may be an imaging device configured to include a plurality of pixels 101. The photodetecting device 100 includes a filter layer 10 provided on the opposite side of the chip 2 and the embedded layer 3 with the substrate 1 in between, a lens layer 11 provided on the opposite side of the substrate with the filter layer 10 in between, may be provided. The photodetection device 100 can be applied to an imaging device.
　図２１等を参照して説明したように、光検出装置１００は、基板１と埋め込み層３との間に設けられた追加基板１２を備えてよい。これにより、例えば光検出装置１００を高機能化することができる。 As described with reference to FIG. 21 and the like, the photodetecting device 100 may include the additional substrate 12 provided between the substrate 1 and the buried layer 3. Thereby, for example, the photodetection device 100 can be made highly functional.
　図２２等を参照して説明したように、チップ２は、間隔をあけて隣り合うように配置された２つのチップ２を含み、埋め込み層３は、２つのチップ２どうしの間に設けられた配線Ｌを含んでよい。光検出装置１００のさらなる高機能化が可能になる。光検出装置１００は、埋め込み層３、封止層５及び支持基板７を貫通する貫通ビアＶを備えてよい。例えば支持基板７の表面７ａから追加基板１２の表面１２ａ側の配線層へのアクセスが可能になる。 As described with reference to FIG. 22 and the like, the chip 2 includes two chips 2 arranged adjacent to each other with an interval, and the buried layer 3 is provided between the two chips 2. The wiring L may be included. It becomes possible to further improve the functionality of the photodetecting device 100. The photodetecting device 100 may include a through via V that penetrates the buried layer 3 , the sealing layer 5 , and the support substrate 7 . For example, it becomes possible to access the wiring layer on the surface 12a side of the additional substrate 12 from the surface 7a of the support substrate 7.
　なお、本開示に記載された効果は、あくまで例示であって、開示された内容に限定されない。他の効果があってもよい。 Note that the effects described in the present disclosure are merely examples and are not limited to the disclosed contents. There may also be other effects.
１２．移動体への応用例
　これまで説明した技術は、さまざまな製品へ応用することができる。例えば、これまで説明した光検出装置１００は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 12. Examples of applications to mobile objects The technology described so far can be applied to a variety of products. For example, the photodetection device 100 described so far is a device mounted on any type of moving object such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, a robot, etc. It may also be realized as
　図２４は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 24 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図２４に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ（Interface）１２０５３が図示されている。 The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 24, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted. For example, an imaging section 12031 is connected to the outside-vehicle information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects in-vehicle information. For example, a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040. The driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ（Advanced　Driver　Assistance　System）の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, Control commands can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or shock mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０２０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図２４の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle. In the example of FIG. 24, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
　図２５は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 25 is a diagram showing an example of the installation position of the imaging section 12031.
　図２５では、撮像部１２０３１として、撮像部１２１０１、１２１０２、１２１０３、１２１０４、１２１０５を有する。 In FIG. 25, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
　撮像部１２１０１、１２１０２、１２１０３、１２１０４、１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２、１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at, for example, the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield inside the vehicle. An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100. An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100. The imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
　なお、図２５には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 25 shows an example of the imaging range of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose. The imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０km/h以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. By determining the following, it is possible to extract, in particular, the closest three-dimensional object on the path of vehicle 12100, which is traveling at a predetermined speed (for example, 0 km/h or more) in approximately the same direction as vehicle 12100, as the preceding vehicle. can. Furthermore, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, etc., in which the vehicle travels autonomously without depending on the driver's operation.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not. This is done by a procedure that determines the When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian. The display unit 12062 is controlled to display the . Furthermore, the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、先に説明した光検出装置１００は、以上説明した構成のうち、例えば撮像部１２０３１に適用され得る。例えば、光検出装置１００を含む製品の信頼性をより向上させることができる。 The photodetecting device 100 described above can be applied to, for example, the imaging section 12031 among the configurations described above. For example, the reliability of products including the photodetector 100 can be further improved.
　光検出装置１００のさらなる実施形態について説明する。なお、これまで説明した技術内容も含め、矛盾の無い範囲において、開示される技術が適宜組み合わされてよい。例えば、封止層５は、シーム部４内まで延在していてもよいし、していなくてもよい。封止層５の材料は、低浸透性材料であってもよいし、低ヤング率材料（例えば樹脂）であってもよい。光検出装置１００は、撮像装置であってよい。 Further embodiments of the photodetection device 100 will be described. Note that the disclosed technologies may be combined as appropriate, including the technical contents described so far, within the scope of consistency. For example, the sealing layer 5 may or may not extend into the seam portion 4. The material of the sealing layer 5 may be a low permeability material or a low Young's modulus material (for example, resin). Photodetection device 100 may be an imaging device.
１３．第９実施形態
　図２６及び図２７は、第９実施形態に係る光検出装置の概略構成の例を示す図である。チップ２は、複数のチップ２を含む。複数のチップ２として、図２６には２つのチップ２が、図２７には３つのチップ２が例示される。第１のチップを、チップ２－１と称し図示する。第２のチップを、チップ２－２と称し図示する。第３のチップを、チップ２－３と称し図示する。なお、ここでのチップ２－１及びチップ２－２は、先に説明した第６実施形態（図５及び図６）のチップ２－１及びチップ２－２とは区別して解されてよい。 13. Ninth Embodiment FIGS. 26 and 27 are diagrams illustrating an example of a schematic configuration of a photodetecting device according to a ninth embodiment. Chip 2 includes a plurality of chips 2. As the plurality of chips 2, two chips 2 are illustrated in FIG. 26, and three chips 2 are illustrated in FIG. 27. The first chip is illustrated and referred to as chip 2-1. The second chip is designated and illustrated as chip 2-2. A third chip is illustrated and referred to as chip 2-3. Note that the chip 2-1 and the chip 2-2 here may be understood separately from the chip 2-1 and the chip 2-2 of the sixth embodiment (FIGS. 5 and 6) described above.
　図２６に示される例では、チップ２－１及びチップ２－２は、互いに異なる厚さ（高さ）を有する。チップ２－２は、チップ２－１の厚さよりも大きい厚さを有する。換言すると、チップ２－１は、チップ２－２の厚さよりも小さい厚さを有する。シーム部４は、シーム部４－１と、シーム部４－２とを含む。シーム部４－１は、チップ２－１から埋め込み層３の表面３ａに向かって延在する第１のシーム部である。シーム部４－２は、チップ２－２から埋め込み層３の表面３ａに向かって延在する第２のシーム部である。 In the example shown in FIG. 26, the chip 2-1 and the chip 2-2 have mutually different thicknesses (heights). Chip 2-2 has a thickness greater than that of chip 2-1. In other words, chip 2-1 has a thickness smaller than that of chip 2-2. The seam portion 4 includes a seam portion 4-1 and a seam portion 4-2. The seam portion 4-1 is a first seam portion extending from the chip 2-1 toward the surface 3a of the buried layer 3. The seam portion 4-2 is a second seam portion extending from the chip 2-2 toward the surface 3a of the buried layer 3.
　チップ２－１の厚さがチップ２－２の厚さよりも小さいので、それらの厚さ方向において、シーム部４－１の長さは、シーム部４－２の長さよりも短くなり得る。シーム部４－２は、シーム部４－１よりも埋め込み層３の表面３ａの近くまで延在し得る。図２６に示される例では、シーム部４－２は埋め込み層３の表面３ａに到達しているのに対し、シーム部４－１は、埋め込み層３の表面３ａに到達していない。封止層５の延在部５ａは、シーム部４－２の少なくとも一部を埋めるように、シーム部４－２内まで延在し得る。一方で、シーム部４－１は、空隙４ａになり得る。 Since the thickness of the chip 2-1 is smaller than the thickness of the chip 2-2, the length of the seam portion 4-1 may be shorter than the length of the seam portion 4-2 in the thickness direction thereof. Seam portion 4-2 may extend closer to surface 3a of buried layer 3 than seam portion 4-1. In the example shown in FIG. 26, the seam portion 4-2 has reached the surface 3a of the buried layer 3, whereas the seam portion 4-1 has not reached the surface 3a of the buried layer 3. The extending portion 5a of the sealing layer 5 may extend into the seam portion 4-2 so as to fill at least a portion of the seam portion 4-2. On the other hand, the seam portion 4-1 can become a void 4a.
　図２７に示される例では、チップ２－３が、チップ２－２上に設けられる。チップ２－２及びチップ２－３は、この順に積層された複数のチップ２（積層チップ）である。チップ２－３は、配線を介して、チップ２－２と電気的に接続される。配線には、チップ２を貫通する貫通ビア２ｖも含まれる。チップ２－２及びチップ２－３は、全体として、チップ２－１の厚さよりも大きい厚さを有する。この条件を満たす限りにおいて、チップ２－２の厚さは、チップ２－１の厚さと同じであってもよいし、異なっていてもよい。チップ２－３についても同様である。なお、積層されるチップ２の数は、３以上であってもよい。 In the example shown in FIG. 27, chip 2-3 is provided on chip 2-2. Chip 2-2 and chip 2-3 are a plurality of chips 2 (stacked chips) stacked in this order. Chip 2-3 is electrically connected to chip 2-2 via wiring. The wiring also includes a through via 2v that penetrates the chip 2. Chip 2-2 and chip 2-3 have a total thickness greater than the thickness of chip 2-1. As long as this condition is satisfied, the thickness of the chip 2-2 may be the same as or different from the thickness of the chip 2-1. The same applies to chip 2-3. Note that the number of stacked chips 2 may be three or more.
　シーム部４については、先に説明した図２６と同様である。シーム部４－２は、シーム部４－１よりも埋め込み層３の表面３ａの近くまで延在していてよい。図２７に示される例では、シーム部４－２は埋め込み層３の表面３ａに到達しているのに対し、シーム部４－１は、埋め込み層３の表面３ａに到達していない。 The seam portion 4 is the same as that shown in FIG. 26 described above. The seam portion 4-2 may extend closer to the surface 3a of the buried layer 3 than the seam portion 4-1. In the example shown in FIG. 27, the seam portion 4-2 has reached the surface 3a of the buried layer 3, whereas the seam portion 4-1 has not reached the surface 3a of the buried layer 3.
＜製造方法の例＞
　図２８～図３２は、光検出装置の製造方法の例を示す図である。なお、製造方法に関するこれまでの説明と重複する内容については適宜説明を省略する。 <Example of manufacturing method>
28 to 32 are diagrams illustrating an example of a method for manufacturing a photodetecting device. Note that descriptions of content that overlap with the previous description regarding the manufacturing method will be omitted as appropriate.
　図２８に示されるように、チップ２－１及びチップ２－２を基板１上に設ける。図２９に示されるように、基板１、チップ２－１及びチップ２－２を覆うように、埋め込み層３を設ける。シーム部４－１及びシーム部４－２が発生する。この時点では、シーム部４－１及びシーム部４－２はいずれも空隙である。 As shown in FIG. 28, a chip 2-1 and a chip 2-2 are provided on a substrate 1. As shown in FIG. 29, a buried layer 3 is provided to cover the substrate 1, chips 2-1, and chips 2-2. A seam portion 4-1 and a seam portion 4-2 are generated. At this point, both the seam portion 4-1 and the seam portion 4-2 are voids.
　図３０に示されるように、埋め込み層３を平坦化する。シーム部４－１及びシーム部４－２のうち、シーム部４－２の上部が開口している。図３１に示されるように、埋め込み層３及びシーム部４－２を覆うように、封止層５を設ける。封止層５がシーム部４－２内まで延在し、その部分が封止層５の延在部５ａになる。図３２に示されるように、封止層５を覆うように補助層６を設ける。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図２６の構成が得られる。 As shown in FIG. 30, the buried layer 3 is planarized. Of the seam portions 4-1 and 4-2, the upper portion of the seam portion 4-2 is open. As shown in FIG. 31, a sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4-2. The sealing layer 5 extends into the seam portion 4-2, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 32, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 26 described above is obtained.
　上記の製造プロセスにおけるチップ２－２を、チップ２－２及びチップ２－３の積層構造に置き換えることによって、先に説明した図２７の構成が得られる。 By replacing chip 2-2 in the above manufacturing process with a stacked structure of chip 2-2 and chip 2-3, the configuration shown in FIG. 27 described earlier can be obtained.
＜変形例＞
　図３３及び図３４は、変形例を示す図である。図３３及び図３４に示される光検出装置１００は、先に説明した図２６及び図２７の光検出装置１００と比較して、シーム部４－１が埋め込み層３の表面３ａに到達している点、及び、封止層５の延在部５ａがシーム部４－１内まで延在している点において相違する。 <Modified example>
33 and 34 are diagrams showing modified examples. In the photodetecting device 100 shown in FIGS. 33 and 34, the seam portion 4-1 reaches the surface 3a of the buried layer 3, compared to the photodetecting device 100 shown in FIGS. 26 and 27 described above. The difference is that the extending portion 5a of the sealing layer 5 extends into the seam portion 4-1.
１４．第１０実施形態
　図３５及び図３６は、第１０実施形態に係る光検出装置の概略構成の例を示す図である。これまで説明した光検出装置１００の層構造が多層化される。チップ２は、高さ方向（Ｚ軸方向）に並んで位置する２つのチップ２を含む。 14. 10th Embodiment FIGS. 35 and 36 are diagrams showing an example of a schematic configuration of a photodetecting device according to a 10th embodiment. The layered structure of the photodetecting device 100 described so far is multilayered. The chip 2 includes two chips 2 located side by side in the height direction (Z-axis direction).
　図３５を参照すると、高さ方向に並んで位置する２つのチップ２として、チップ２－２及びチップ２－３が例示される。チップ２－２は、チップ２－３よりも下方（Ｚ軸負方向側）に位置する下方チップである。チップ２－３は、チップ２－２よりも上方（Ｚ軸正方向側）に位置する上方チップである。なお、チップ２－２は、チップ２－１と同じ高さに位置している。 Referring to FIG. 35, a chip 2-2 and a chip 2-3 are illustrated as two chips 2 located side by side in the height direction. The chip 2-2 is a lower chip located below the chip 2-3 (on the Z-axis negative direction side). Chip 2-3 is an upper chip located above chip 2-2 (on the Z-axis positive direction side). Note that the chip 2-2 is located at the same height as the chip 2-1.
　光検出装置１００は、接合層１３をさらに含む。接合層１３は、チップ２－２とチップ２－３との間に設けられる。接合層１３は、チップ２－２とチップ２－３との電気的な接続を与えるように、配線を含んで構成される。接合層１３における配線以外の部分は、絶縁材料であってよく、この意味において、接合層１３は、絶縁層とも呼べる。チップ２－２及びチップ２－３は、接合層１３を介して互いに反対側に設けられるとともに、接合層１３を介して互いに電気的に接続される。 The photodetector 100 further includes a bonding layer 13. Bonding layer 13 is provided between chip 2-2 and chip 2-3. The bonding layer 13 is configured to include wiring so as to provide electrical connection between the chips 2-2 and 2-3. The parts of the bonding layer 13 other than the wiring may be made of an insulating material, and in this sense, the bonding layer 13 can also be called an insulating layer. The chip 2-2 and the chip 2-3 are provided on opposite sides of the bonding layer 13 and are electrically connected to each other via the bonding layer 13.
　埋め込み層３は、埋め込み層３－１と、埋め込み層３－２とを含む。埋め込み層３－１は、基板１、チップ２－１の側面及びチップ２－２の側面を覆うように設けられた下方埋め込み層である。埋め込み層３－２は、接合層１３及びチップ２－３を覆うように設けられた上方埋め込み層である。 The buried layer 3 includes a buried layer 3-1 and a buried layer 3-2. The buried layer 3-1 is a lower buried layer provided to cover the substrate 1, the side surfaces of the chip 2-1, and the side surfaces of the chip 2-2. The buried layer 3-2 is an upper buried layer provided to cover the bonding layer 13 and the chip 2-3.
　シーム部４は、シーム部４－１と、シーム部４－２と、シーム部４－３とを含む。シーム部４－１は、チップ２－１から埋め込み層３－１の表面３ａに向かって延在する。シーム部４－２は、チップ２－１から埋め込み層３－１の表面３ａに向かって延在する。シーム部４－３は、チップ２－３から埋め込み層３－２の表面３ａ向かって延在する。 The seam portion 4 includes a seam portion 4-1, a seam portion 4-2, and a seam portion 4-3. Seam portion 4-1 extends from chip 2-1 toward surface 3a of buried layer 3-1. Seam portion 4-2 extends from chip 2-1 toward surface 3a of buried layer 3-1. The seam portion 4-3 extends from the chip 2-3 toward the surface 3a of the buried layer 3-2.
　シーム部４－１及びシーム部４－２は、埋め込み層３－１内に発生し、埋め込み層３－１の表面３ａまで延在する下方シーム部である。シーム部４－３は、埋め込み層３－２内に発生し、埋め込み層３－２の表面３ａまで延在する上方シーム部である。 The seam portion 4-1 and the seam portion 4-2 are lower seam portions that occur within the buried layer 3-1 and extend to the surface 3a of the buried layer 3-1. The seam portion 4-3 is an upper seam portion that occurs within the buried layer 3-2 and extends to the surface 3a of the buried layer 3-2.
　封止層５は、埋め込み層３－２及びシーム部４－３を覆うように設けられる。接合層１３は、埋め込み層３－１、シーム部４－１及びシーム部４－２を覆うように設けられる。接合層１３は、埋め込み層３－１、シーム部４－１及びシーム部４－２に対して、封止層５と同様に機能し得る。 The sealing layer 5 is provided to cover the buried layer 3-2 and the seam portion 4-3. The bonding layer 13 is provided so as to cover the buried layer 3-1, the seam portion 4-1, and the seam portion 4-2. The bonding layer 13 can function similarly to the sealing layer 5 with respect to the buried layer 3-1, the seam portion 4-1, and the seam portion 4-2.
　図３６に示される例では、チップ２は、ダミーチップ２Ｄをさらに含む。ダミーチップ２Ｄは、チップ２－１よりも上方において、埋め込み層３－２内に位置する。ダミーチップ２Ｄは、埋め込み層３－２内に、あたかもダミーチップ２Ｄの容積と同じ容積のチップ２が存在するような状態を作り出す。ダミーチップ２Ｄの材料は、チップ２の材料と同じであってもよいし、異なっていてもよい。ダミーチップ２Ｄは、チップ２の機能を有していなくてもよい。 In the example shown in FIG. 36, the chip 2 further includes a dummy chip 2D. The dummy chip 2D is located in the buried layer 3-2 above the chip 2-1. The dummy chip 2D creates a state in the buried layer 3-2 as if a chip 2 with the same volume as the dummy chip 2D exists. The material of the dummy chip 2D may be the same as the material of the chip 2, or may be different. The dummy chip 2D does not need to have the function of the chip 2.
　チップ２－１及びダミーチップ２Ｄは、接合層１３を介して互いに反対側に設けられる。なお、チップ２－１とダミーチップ２Ｄとは、電気的に接続されてもよいし、接続されていなくてもよい。ダミーチップ２Ｄは、例えばチップ２－３の厚さと同じ厚さを有する。 The chip 2-1 and the dummy chip 2D are provided on opposite sides of the bonding layer 13. Note that the chip 2-1 and the dummy chip 2D may or may not be electrically connected. The dummy chip 2D has, for example, the same thickness as the chip 2-3.
　埋め込み層３－２は、接合層１３、ダミーチップ２Ｄ及びチップ２－３を覆うように設けられる。シーム部４は、ダミーチップ２Ｄから埋め込み層３－２の表面３ａに向かって延在するシーム部４－Ｄをさらに含む。封止層５は、埋め込み層３－２、シーム部４－Ｄ及びシーム部４－３を覆うように設けられる。 The buried layer 3-2 is provided to cover the bonding layer 13, the dummy chip 2D, and the chip 2-3. The seam portion 4 further includes a seam portion 4-D extending from the dummy chip 2D toward the surface 3a of the buried layer 3-2. The sealing layer 5 is provided to cover the buried layer 3-2, the seam portion 4-D, and the seam portion 4-3.
　ダミーチップ２Ｄが無いと、その部分をすべて埋め込み層３で埋めなければならず、例えばその部分だけ埋め込み層３の高さが不足する等して、埋め込み層３の平坦化が難しくなる。この問題が、ダミーチップ２Ｄを設けることによって対処される。すなわち、ダミーチップ２Ｄを設けることで、ダミーチップ２Ｄを設けない場合よりも、埋め込み層３－２の平坦化が容易になる。 If there is no dummy chip 2D, the entire portion must be filled with the buried layer 3, and for example, the height of the buried layer 3 may be insufficient in that portion, making it difficult to planarize the buried layer 3. This problem is addressed by providing a dummy chip 2D. That is, by providing the dummy chip 2D, planarization of the buried layer 3-2 becomes easier than in the case where the dummy chip 2D is not provided.
＜製造方法の例＞
　図３７～図４３は、光検出装置の製造方法の例を示す図である。前提として、先に説明した図２８及び図２９と同様の製造プロセスが完了しているものとする。ここでの埋め込み層３－１は、図２８及び図２９の埋め込み層３に相当し、また、ここでのチップ２－２の厚さは、図２８及び図２９のチップ２－２の厚さとは異なる。 <Example of manufacturing method>
37 to 43 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As a premise, it is assumed that the manufacturing process similar to that shown in FIGS. 28 and 29 described above has been completed. The buried layer 3-1 here corresponds to the buried layer 3 in FIGS. 28 and 29, and the thickness of the chip 2-2 here is the same as the thickness of the chip 2-2 in FIGS. 28 and 29. is different.
　図３７に示されるように、埋め込み層３－１の上部を研磨、洗浄し、埋め込み層３－１、シーム部４－１及びシーム部４－２を覆うように封止層５を設ける。封止層５がシーム部４－１内及びシーム部４－２内まで延在し、その部分が封止層５の延在部５ａになる。図３８に示されるように、研磨によって封止層５を取り除く。延在部５ａは、シーム部４－１内及びシーム部４－２内に残る。チップ２－１及びチップ２－２の表面２ａが露出する。表面２ａは、チップ２－１及びチップ２－２のＺ軸正方向側の面である。 As shown in FIG. 37, the upper part of the buried layer 3-1 is polished and cleaned, and the sealing layer 5 is provided so as to cover the buried layer 3-1, the seam portions 4-1, and the seam portions 4-2. The sealing layer 5 extends to the inside of the seam portion 4-1 and the seam portion 4-2, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 38, the sealing layer 5 is removed by polishing. The extending portion 5a remains within the seam portion 4-1 and within the seam portion 4-2. Surfaces 2a of chips 2-1 and 2-2 are exposed. The surface 2a is the surface of the chips 2-1 and 2-2 on the Z-axis positive direction side.
　図３９に示されるように、チップ２－２を貫通する貫通ビア２ｖを設ける。また、埋め込み層３－１、チップ２－１、シーム部４－１、チップ２－２及びシーム部４－２を覆うように、接合層１３を設ける。図４０に示されるように、接合層１３を挟んでチップ２－２とは反対側において、接合層１３上にチップ２－３を設ける。図４１に示されるように、接合層１３及びチップ２－２を覆うように、埋め込み層３－２を設ける。シーム部４－３が発生する。この時点ではシーム部４－３は空隙である。 As shown in FIG. 39, a through via 2v is provided that penetrates the chip 2-2. Further, a bonding layer 13 is provided so as to cover the buried layer 3-1, the chip 2-1, the seam portion 4-1, the chip 2-2, and the seam portion 4-2. As shown in FIG. 40, a chip 2-3 is provided on the bonding layer 13 on the opposite side of the bonding layer 13 from the chip 2-2. As shown in FIG. 41, a buried layer 3-2 is provided to cover the bonding layer 13 and the chip 2-2. A seam portion 4-3 is generated. At this point, the seam portion 4-3 is a gap.
　図４２に示されるように、埋め込み層３－２、チップ２－３及びシーム部４－３を覆うように封止層５を設ける。封止層５がシーム部４－３内まで延在し、その部分が封止層５の延在部５ａになる。図４３に示されるように、封止層５を覆うように補助層６を設ける。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図３５の構成が得られる。 As shown in FIG. 42, a sealing layer 5 is provided to cover the buried layer 3-2, chip 2-3, and seam portion 4-3. The sealing layer 5 extends into the seam portion 4-3, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 43, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 35 described above is obtained.
　上記の製造プロセスにおいて、チップ２－３を設ける際にダミーチップ２Ｄも設けることで、先に説明した図３６の構成が得られる。 In the above manufacturing process, by also providing the dummy chip 2D when providing the chip 2-3, the configuration shown in FIG. 36 described earlier can be obtained.
＜変形例＞
　図４４は、変形例を示す図である。２つの基板１が準備され、それぞれの基板上にチップ２及び埋め込み層３を設けたうえで、それらが接合層１３を介して貼り合わされる。２つの基板１のうちの第１の基板を、基板１－１と称し図する。第２の基板を、基板１－２と称し図示する。 <Modified example>
FIG. 44 is a diagram showing a modification. Two substrates 1 are prepared, a chip 2 and a buried layer 3 are provided on each substrate, and then they are bonded together via a bonding layer 13. The first of the two substrates 1 is referred to as a substrate 1-1. The second substrate is illustrated and referred to as substrate 1-2.
　先に説明した図３９の製造プロセスまでと同様の製造プロセスを、基板１－１に対して行う。基板１－１上に、チップ２－１及びチップ２－２を設け、また、貫通ビア２ｖを設ける。基板１－１、チップ２－１及びチップ２－２を覆うように、埋め込み層３－１を設ける。埋め込み層３－１内に、シーム部４－１及びシーム部４－２が発生する。埋め込み層３－１、シーム部４－１及びシーム部４－２を覆うように、封止層５を設ける。封止層５がシーム部４－１内及びシーム部４－２内まで延在し、その部分が、封止層５の延在部５ａになる。研磨により封止層５を取り除く。延在部５ａは、シーム部４－１内及びシーム部４－２内に残る。埋め込み層３－１、シーム部４－１及びシーム部４－２を覆うように、接合層１３を設ける。 A manufacturing process similar to that up to the manufacturing process of FIG. 39 described above is performed on the substrate 1-1. A chip 2-1 and a chip 2-2 are provided on the substrate 1-1, and a through via 2v is also provided. A buried layer 3-1 is provided to cover the substrate 1-1, the chip 2-1, and the chip 2-2. A seam portion 4-1 and a seam portion 4-2 are generated within the buried layer 3-1. A sealing layer 5 is provided so as to cover the buried layer 3-1, the seam portion 4-1, and the seam portion 4-2. The sealing layer 5 extends to the inside of the seam portion 4-1 and the seam portion 4-2, and that portion becomes an extension portion 5a of the sealing layer 5. The sealing layer 5 is removed by polishing. The extending portion 5a remains within the seam portion 4-1 and within the seam portion 4-2. A bonding layer 13 is provided so as to cover the buried layer 3-1, the seam portions 4-1, and the seam portions 4-2.
　基板１－２上に、チップ２－３及びダミーチップ２Ｄを設け、また、チップ２－３を貫通する貫通ビア３ｖを設ける。基板１－２、チップ２－２及びダミーチップ２Ｄを覆うように、埋め込み層３－２を設ける。埋め込み層３－２内に、シーム部４－３及びシーム部４－Ｄが発生する。埋め込み層３－２、シーム部４－３及びシーム部４－Ｄを覆うように、封止層５を設ける。封止層５がシーム部４－３内及びシーム部４－Ｄ内まで延在し、その部分が、封止層５の延在部５ａになる。研磨により、封止層５を取り除く。延在部５ａは、シーム部４－３内及びシーム部４－Ｄ内に残る。 A chip 2-3 and a dummy chip 2D are provided on the substrate 1-2, and a through via 3v passing through the chip 2-3 is provided. A buried layer 3-2 is provided to cover the substrate 1-2, chip 2-2, and dummy chip 2D. A seam portion 4-3 and a seam portion 4-D are generated within the buried layer 3-2. A sealing layer 5 is provided to cover the buried layer 3-2, the seam portion 4-3, and the seam portion 4-D. The sealing layer 5 extends into the seam portion 4-3 and into the seam portion 4-D, and that portion becomes an extension portion 5a of the sealing layer 5. The sealing layer 5 is removed by polishing. The extension portion 5a remains within the seam portion 4-3 and within the seam portion 4-D.
　上記のようにして得られた基板１－２側の埋め込み層３－２を、基板１－１側の接合層１３に貼り合わせることで、図４４の構成が得られる。この貼り合わせは、基板１－１を含むウェハ（例えば半導体ウェハ）と、基板１－２を含むウェハとを接合することによって行われてよい。シーム部４内は延在部５ａで埋められており、シーム部の開口部分は接合層１３で覆われている。接合層１３が、シーム部４を覆う封止層５として機能するともいえる。 The structure shown in FIG. 44 is obtained by bonding the buried layer 3-2 on the substrate 1-2 side obtained as described above to the bonding layer 13 on the substrate 1-1 side. This bonding may be performed by bonding a wafer (for example, a semiconductor wafer) containing the substrate 1-1 and a wafer containing the substrate 1-2. The interior of the seam portion 4 is filled with an extension portion 5a, and the opening portion of the seam portion is covered with a bonding layer 13. It can also be said that the bonding layer 13 functions as the sealing layer 5 covering the seam portion 4.
＜小結＞
　以上で説明した第９実施形態及び第１０実施形態に係る光検出装置１００は、例えば次のように特定される。図２６及び図３３等を参照して説明したように、チップ２は、チップ２－１（第１のチップ）と、チップ２－１の厚さよりも大きい厚さを有するチップ２－２（第２のチップ）と、を含み、シーム部４は、チップ２－１から埋め込み層３の表面３ａに向かって延在するシーム部４－１（第１のシーム部）と、チップ２－２から埋め込み層３の表面３ａに向かって延在するシーム部４－２（第２のシーム部）と、を含み、シーム部４－２は、シーム部４－１よりも、埋め込み層３の表面３ａの近くまで延在していてよい。或いは、図２７及び図３４等を参照して説明したように、チップ２は、チップ２－１（第１のチップ）と、順に積層されたチップ２－２（第２のチップ）及びチップ２－３（第３のチップ）を含み、チップ２－２及びチップ２－３は、全体として、チップ２－１の厚さよりも大きい厚さを有し、シーム部４は、チップ２－１から埋め込み層３の表面３ａに向かって延在するシーム部４－１（第１のシーム部）と、チップ２－２から埋め込み層３の表面３ａに向かって延在するシーム部４－２（第２のシーム部）と、を含み、シーム部４－２は、シーム部４－１よりも、埋め込み層３の表面３ａの近くまで延在していてよい。このようにチップ部分の厚さが異なる構成においても、シーム部４の外部への連通を抑制することができる。 <Small conclusion>
The photodetecting device 100 according to the ninth embodiment and the tenth embodiment described above is specified, for example, as follows. As described with reference to FIGS. 26, 33, etc., the chip 2 includes the chip 2-1 (first chip) and the chip 2-2 (first chip) having a thickness greater than that of the chip 2-1. The seam portion 4 includes a seam portion 4-1 (first seam portion) extending from the chip 2-1 toward the surface 3a of the buried layer 3, and a seam portion 4-1 (first seam portion) extending from the chip 2-2 toward the surface 3a of the buried layer 3. A seam portion 4-2 (second seam portion) extending toward the surface 3a of the buried layer 3, the seam portion 4-2 being closer to the surface 3a of the buried layer 3 than the seam portion 4-1. It may extend as close as possible. Alternatively, as described with reference to FIGS. 27 and 34, the chip 2 includes a chip 2-1 (first chip), a chip 2-2 (second chip) and a chip 2 stacked in this order. -3 (third chip), the chip 2-2 and the chip 2-3 have a thickness larger as a whole than the thickness of the chip 2-1, and the seam part 4 is separated from the chip 2-1. A seam portion 4-1 (first seam portion) extending toward the surface 3a of the buried layer 3, and a seam portion 4-2 (first seam portion) extending from the chip 2-2 toward the surface 3a of the buried layer 3. The seam portion 4-2 may extend closer to the surface 3a of the buried layer 3 than the seam portion 4-1. Even in such a configuration in which the thickness of the chip portions is different, communication of the seam portion 4 to the outside can be suppressed.
　図２６、図２７、図３３及び図３４等を参照して説明したように、封止層５は、シーム部４－２の少なくとも一部を埋めるようにシーム部４－２内まで延在する延在部５ａを含んでよい。これにより、延在部５ａによるメリットも得られる。例えば、封止層５の材料が低浸透性材料を含む場合には、チップ２への水分等の侵入の抑制効果を高めることができ、また、封止層５の材料が低ヤング率材料を含む場合には、チップ間応力を緩和することができる。 As described with reference to FIG. 26, FIG. 27, FIG. 33, FIG. 34, etc., the sealing layer 5 extends into the seam portion 4-2 so as to fill at least a portion of the seam portion 4-2. It may include an extension portion 5a. Thereby, the advantage of the extension part 5a can also be obtained. For example, when the material of the sealing layer 5 includes a low permeability material, the effect of suppressing moisture etc. from entering the chip 2 can be enhanced, and the material of the sealing layer 5 includes a low Young's modulus material. If it is included, inter-chip stress can be alleviated.
　図２６及び図２７等を参照して説明したように、シーム部４－１は、埋め込み層３の表面３ａに到達しておらず、シーム部４－２は、埋め込み層３の表面３ａに到達していてよい。このように、埋め込み層３の表面３ａに到達するシーム部４－２と、到達しないシーム部４－１とが混在する場合でも、シーム部４の外部への連通を抑制することができる。 As described with reference to FIGS. 26 and 27, the seam portion 4-1 does not reach the surface 3a of the buried layer 3, and the seam portion 4-2 does not reach the surface 3a of the buried layer 3. It's okay to do so. In this way, even if there are a mixture of seam portions 4-2 that reach the surface 3a of the buried layer 3 and seam portions 4-1 that do not reach the surface, communication of the seam portion 4 to the outside can be suppressed.
　図３５及び図３６等を参照して説明したように、チップ２は、高さ方向に並んで位置するチップ２－２（下方チップ）及びチップ２－３（上方チップ）を含み、光検出装置１００は、チップ２－２とチップ２－３との間に設けられた接合層１３をさらに備え、埋め込み層３は、チップ２－２の側面を覆うように設けられた埋め込み層３－１（下方埋め込み層）と、チップ２－３及び接合層１３を覆うように設けられた埋め込み層３－２（上方埋め込み層）と、を含み、シーム部４は、埋め込み層３－１内に発生し、埋め込み層３－１の表面３ａまで延在するシーム部４－２（下方シーム部）と、埋め込み層３－２内に発生し、埋め込み層３－２の表面３ａまで延在するシーム部４－３（上方シーム部）と、を含み、接合層１３は、埋め込み層３－１及びシーム部４－２を覆うように設けられ、封止層５は、埋め込み層３－２及びシーム部４－３を覆うように設けられてよい。このような構成によっても、シーム部４の外部への連通を抑制することができる。 As described with reference to FIGS. 35, 36, etc., the chip 2 includes a chip 2-2 (lower chip) and a chip 2-3 (upper chip) located side by side in the height direction, and includes a photodetector. 100 further includes a bonding layer 13 provided between the chip 2-2 and the chip 2-3, and the buried layer 3 includes a buried layer 3-1 (provided to cover the side surface of the chip 2-2). a lower buried layer) and a buried layer 3-2 (upper buried layer) provided to cover the chip 2-3 and the bonding layer 13; , a seam portion 4-2 (lower seam portion) that extends to the surface 3a of the buried layer 3-1, and a seam portion 4 that occurs within the buried layer 3-2 and extends to the surface 3a of the buried layer 3-2. -3 (upper seam part), the bonding layer 13 is provided so as to cover the buried layer 3-1 and the seam part 4-2, and the sealing layer 5 is provided to cover the buried layer 3-2 and the seam part 4. -3 may be provided to cover. With such a configuration as well, communication of the seam portion 4 to the outside can be suppressed.
　図３６等を参照して説明したように、チップ２は、接合層１３を挟んで互いに反対側に設けられたチップ２－１（下方チップ）及びダミーチップ２Ｄをさらに含み、埋め込み層３－２は、チップ２－３、ダミーチップ２Ｄ及び接合層１３を覆うように設けられてよい。これにより、ダミーチップ２Ｄを設けない場合よりも、埋め込み層３－２の平坦化が容易になる。 As described with reference to FIG. 36 etc., the chip 2 further includes a chip 2-1 (lower chip) and a dummy chip 2D provided on opposite sides with the bonding layer 13 in between, and a buried layer 3-2. may be provided to cover the chip 2-3, the dummy chip 2D, and the bonding layer 13. This makes planarization of the buried layer 3-2 easier than in the case where the dummy chip 2D is not provided.
１５．第１１実施形態
　図４５及び図４６は、第１１実施形態に係る光検出装置の概略構成の例を示す図である。封止層５は、第１の部分５１と、第２の部分５２とを含む。 15. 11th Embodiment FIGS. 45 and 46 are diagrams showing an example of a schematic configuration of a photodetecting device according to an 11th embodiment. The sealing layer 5 includes a first portion 51 and a second portion 52.
　第１の部分５１は、封止層５のうち、シーム部４を覆う部分である。第１の部分５１の少なくとも一部は、隣り合うチップ２どうしの間に位置している。第２の部分５２は、封止層５のうち、シーム部４を覆わない部分である。第２の部分５２の少なくとも一部は、対応するチップ２の上部に位置している。第２の部分５２は、封止層５における第１の部分５１以外の部分であってよい。 The first portion 51 is a portion of the sealing layer 5 that covers the seam portion 4 . At least a portion of the first portion 51 is located between adjacent chips 2. The second portion 52 is a portion of the sealing layer 5 that does not cover the seam portion 4 . At least a portion of the second portion 52 is located on top of the corresponding chip 2. The second portion 52 may be a portion of the sealing layer 5 other than the first portion 51 .
　第１の部分５１のＺ軸正方向側の面を、表面５１ａと称し図示する。Ｚ軸負方向側の面を、裏面５１ｂと称し図示する。第２の部分５２のＺ軸正方向側の面を、表面５２ａと称し図示する。Ｚ軸負方向側の面を、裏面５２ｂと称し図示する。第１の部分５１の裏面５１ｂは、第２の部分５２の裏面５２ｂよりも下方（Ｚ軸負方向側）に位置している。 The surface of the first portion 51 on the Z-axis positive direction side is referred to as a surface 51a in the drawing. The surface on the negative side of the Z-axis is referred to as a back surface 51b. The surface of the second portion 52 on the Z-axis positive direction side is referred to as a surface 52a and is illustrated. The surface on the negative side of the Z-axis is referred to as a back surface 52b in the drawing. The back surface 51b of the first portion 51 is located lower than the back surface 52b of the second portion 52 (on the Z-axis negative direction side).
　図４５に示される例では、第１の部分５１の表面５１ａは、第２の部分５２の表面５２ａと同じ高さに位置している。封止層５全体の表面は、平坦面である。 In the example shown in FIG. 45, the surface 51a of the first portion 51 is located at the same height as the surface 52a of the second portion 52. The entire surface of the sealing layer 5 is a flat surface.
　図４６に示される例では、第１の部分５１の表面５１ａと、第２の部分５２の表面５２ａとは、互いに異なる高さに位置している。この例では、第２の部分５２の表面５２ａは、第１の部分５１の表面５１ａよりも上方（Ｚ軸正方向側）に位置している。封止層５全体の表面は、非平坦面である。ただし、封止層５上に設けられた補助層６（例えばＳｉＯ２等）が平坦な表面６ａを有し、そこで平坦性が確保される。封止層５の材料によっては研磨等による封止層５の平坦化が難しい場合があり、その場合には、封止層５は平坦化せず、より平坦化が容易な補助層６で対応することで、製造プロセスを容易化することができる。補助層６は、平坦化容易層と呼ぶこともできる。 In the example shown in FIG. 46, the surface 51a of the first portion 51 and the surface 52a of the second portion 52 are located at different heights. In this example, the surface 52a of the second portion 52 is located above the surface 51a of the first portion 51 (on the Z-axis positive direction side). The entire surface of the sealing layer 5 is a non-flat surface. However, the auxiliary layer 6 (for example, SiO2, etc.) provided on the sealing layer 5 has a flat surface 6a, thereby ensuring flatness. Depending on the material of the sealing layer 5, it may be difficult to flatten the sealing layer 5 by polishing or the like, and in that case, instead of flattening the sealing layer 5, use the auxiliary layer 6, which is easier to flatten. By doing so, the manufacturing process can be facilitated. The auxiliary layer 6 can also be called an easy-to-planarize layer.
　上記の図４５及び図４６の構成によれば、これまでに説明した構成と比較して、シーム部４上の封止層５の厚さを大きくすることができる。その分、シーム部４の外部への連通を抑制するという封止層５の機能を高めることができる。また、埋め込み層３を平坦化する必要が無いので、例えば、埋め込み層３の研磨、洗浄時に生じ得るシーム部４への薬液の侵入を防ぐことができる。 According to the configurations shown in FIGS. 45 and 46 above, the thickness of the sealing layer 5 on the seam portion 4 can be increased compared to the configurations described above. Accordingly, the function of the sealing layer 5 to suppress communication of the seam portion 4 to the outside can be enhanced. Furthermore, since there is no need to flatten the buried layer 3, it is possible to prevent chemical liquid from entering the seam portion 4, which may occur during polishing or cleaning of the buried layer 3, for example.
＜製造方法の例＞
　図４７～図５１は、光検出装置の製造方法の例を示す図である。図４７～図４９には、先に説明した図４５の構成を得るための製造方法の例が示される。前提として、先に説明した図９及び図１０と同様の製造プロセスが完了しているものとする。 <Example of manufacturing method>
47 to 51 are diagrams illustrating an example of a method for manufacturing a photodetecting device. 47 to 49 show an example of a manufacturing method for obtaining the configuration shown in FIG. 45 described above. As a premise, it is assumed that the manufacturing process similar to that shown in FIGS. 9 and 10 described above has been completed.
　図４７に示されるように、埋め込み層３を研磨することなく、その上に封止層５を設ける。封止層５がシーム部４内まで延在し、その部分が、封止層５の延在部５ａになる。図４８に示されるように、封止層５の上部を研磨し、洗浄することで、先に説明した図４５のような、第１の部分５１及び第２の部分５２を含む封止層５が得られる。第１の部分５１の表面５１ａ及び第２の部分５２の表面５２ａは、いずれも同じ高さに位置し、封止層５全体の表面は平坦面になる。図４９に示されるように、封止層５を覆うように補助層６を設ける。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図４５の構成が得られる。 As shown in FIG. 47, the sealing layer 5 is provided on the buried layer 3 without polishing it. The sealing layer 5 extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 48, by polishing and cleaning the upper part of the sealing layer 5, the sealing layer 5 including the first portion 51 and the second portion 52 as shown in FIG. is obtained. The surface 51a of the first portion 51 and the surface 52a of the second portion 52 are both located at the same height, and the entire surface of the sealing layer 5 is a flat surface. As shown in FIG. 49, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 45 described above is obtained.
　図５０及び図５１には、先に説明した図４６の構成を得るための製造方法の例が示される。前提として、先に説明した図４７の製造プロセスが完了しているものとする。 FIGS. 50 and 51 show an example of a manufacturing method for obtaining the configuration shown in FIG. 46 described above. As a premise, it is assumed that the manufacturing process shown in FIG. 47 described above has been completed.
　図５０に示されるように、先に説明した図４９と同様の第１の部分５１及び第２の部分５２を含む封止層５が得られており、この封止層５を研磨することなく、封止層５を覆うように補助層６を設ける。図５１に示されるように、補助層６の上部を研磨、洗浄することで、平坦な表面６ａを有する補助層６が得られる。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図４６の構成が得られる。 As shown in FIG. 50, a sealing layer 5 including a first portion 51 and a second portion 52 similar to those in FIG. 49 described above is obtained, and this sealing layer 5 is not polished. , an auxiliary layer 6 is provided to cover the sealing layer 5. As shown in FIG. 51, by polishing and cleaning the upper part of the auxiliary layer 6, the auxiliary layer 6 having a flat surface 6a is obtained. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 46 described above is obtained.
１６．第１２実施形態
　一実施形態において、封止層５は、積層構造を有してよい。図５２を参照して説明する。 16. Twelfth Embodiment In one embodiment, the sealing layer 5 may have a laminated structure. This will be explained with reference to FIG. 52.
　図５２は、封止層の概略構成の例を示す図である。図５２の（Ａ）には、封止層５及びその周辺の断面が模式的に示される。図５２の（Ｂ）には、封止層５の一部を拡大した断面が模式的に示される。 FIG. 52 is a diagram showing an example of a schematic configuration of a sealing layer. FIG. 52A schematically shows a cross section of the sealing layer 5 and its surroundings. FIG. 52(B) schematically shows an enlarged cross section of a part of the sealing layer 5.
　封止層５は、複数の層が積層された積層構造を有する。複数の層は、例えば２種類の層を含んでよい。２種類の層のうちの一方の種類の層は無機層であってよく、他方の種類の層は有機層であってよい。無機層を、無機層５３と称し図示する。有機層を、有機層５４と称し図示する。 The sealing layer 5 has a laminated structure in which a plurality of layers are laminated. The plurality of layers may include, for example, two types of layers. One type of layer of the two types of layers may be an inorganic layer and the other type of layer may be an organic layer. The inorganic layer is illustrated as an inorganic layer 53. The organic layer is illustrated as organic layer 54 .
　無機層５３の材料として、種々の公知の無機材料が用いられてよい。無機材料の例は、Ａｌ２Ｏ３、ＳｉＮ、ＳｉＯＮ、ＳｉＣＮ等である。 Various known inorganic materials may be used as the material for the inorganic layer 53. Examples of inorganic materials are Al 2 O 3 , SiN, SiON, SiCN, etc.
　有機層５４の材料として、種々の公知の有機材料が用いられてよい。材料の例は、ポリマー、ハイブリッドポリマー等である。ポリマーの例は、ＰＥＮ、ＰＥＴ、ＰＥＧ等である。ハイブリッドポリマーは、ポリマーと例えば金属材料と含む材料である。金属材料がアルミニウムの場合のハイブリッドポリマーの一例は、Ａｌｃｏｎｅである。有機層５４は、例えばスピンコート、インクジェット法、ＭＬＤ法等を用いて形成されてよい。シーム部４の内部まで延在する延在部５ａを含む封止層５の形成には、ＭＬＤ法が好適に用いられ得る。 Various known organic materials may be used as the material for the organic layer 54. Examples of materials are polymers, hybrid polymers, etc. Examples of polymers are PEN, PET, PEG, etc. Hybrid polymers are materials that include a polymer and, for example, a metallic material. An example of a hybrid polymer when the metal material is aluminum is Alcone. The organic layer 54 may be formed using, for example, spin coating, an inkjet method, an MLD method, or the like. The MLD method may be suitably used to form the sealing layer 5 including the extension portion 5a extending into the seam portion 4.
　図５２に示される例では、封止層５は、３つの無機層５３と、３つの有機層５４とを含む６層構造を有する。無機層５３及び有機層５４は、交互に積層される。ただし、無機層５３及び有機層５４の数は、図５２に示される数よりも少なくてもよいし、多くてもよい。 In the example shown in FIG. 52, the sealing layer 5 has a six-layer structure including three inorganic layers 53 and three organic layers 54. The inorganic layers 53 and the organic layers 54 are alternately stacked. However, the number of inorganic layers 53 and organic layers 54 may be smaller or larger than the number shown in FIG. 52.
　封止層５が積層構造を有することにより、封止層５の機能を高めることができる。例えば、ガス（水蒸気等）バリア性を向上させたり、変形に対するロバスト性を向上させたりすることができる。 Since the sealing layer 5 has a laminated structure, the function of the sealing layer 5 can be enhanced. For example, gas (water vapor, etc.) barrier properties can be improved, and robustness against deformation can be improved.
＜小結＞
　以上で説明した第１１実施形態及び第１２実施形態に係る光検出装置１００は、例えば次のように特定される。図４５及び図４６等を参照して説明したように、封止層５は、シーム部４を覆う第１の部分５１と、シーム部４を覆わない第２の部分５２と、を含み、第１の部分５１の裏面５１ｂは、第２の部分５２の裏面５２ｂよりも下方（Ｚ軸負方向側）に位置していてよい。図４５等を参照して説明したように、第１の部分５１の表面５１ａは、第２の部分５２の表面５２ａと同じ高さに位置していてよい。或いは、図４６等を参照して説明したように、光検出装置１００は、封止層５を覆うように設けられた補助層６を備え、第２の部分５２の表面５２ａは、第１の部分５１の表面５１ａよりも上方（Ｚ軸正方向側）に位置しており、補助層６の表面６ａは、平坦面であってよい。例えばこのような構成により、シーム部４上の封止層５の厚さを大きくすることができる。その分、シーム部４の外部への連通を抑制するという封止層５の機能を高めることができる。また、埋め込み層３を平坦化する必要が無いので、例えば、埋め込み層３の研磨、洗浄時に生じ得るシーム部４への薬液の侵入を防ぐことができる。 <Small conclusion>
The photodetecting device 100 according to the eleventh embodiment and the twelfth embodiment described above is specified as follows, for example. As described with reference to FIGS. 45 and 46, the sealing layer 5 includes a first portion 51 that covers the seam portion 4, a second portion 52 that does not cover the seam portion 4, and a second portion 52 that does not cover the seam portion 4. The back surface 51b of the first portion 51 may be located lower than the back surface 52b of the second portion 52 (on the Z-axis negative direction side). As described with reference to FIG. 45 and the like, the surface 51a of the first portion 51 may be located at the same height as the surface 52a of the second portion 52. Alternatively, as described with reference to FIG. 46 etc., the photodetecting device 100 includes the auxiliary layer 6 provided to cover the sealing layer 5, and the surface 52a of the second portion 52 is It is located above the surface 51a of the portion 51 (on the Z-axis positive direction side), and the surface 6a of the auxiliary layer 6 may be a flat surface. For example, with such a configuration, the thickness of the sealing layer 5 on the seam portion 4 can be increased. Accordingly, the function of the sealing layer 5 to suppress communication of the seam portion 4 to the outside can be enhanced. Furthermore, since there is no need to flatten the buried layer 3, it is possible to prevent chemical liquid from entering the seam portion 4, which may occur during polishing or cleaning of the buried layer 3, for example.
　図５２等を参照して説明したように、封止層５は、複数の層が積層された積層構造を有してよい。封止層５の複数の層は、無機層５３及び有機層５４を含んでよい。これにより、封止層５の機能を高めることができる。例えば、ガス（水蒸気等）バリア性を向上させたり、変形に対するロバスト性を向上させたりすることができる。 As described with reference to FIG. 52 and the like, the sealing layer 5 may have a laminated structure in which a plurality of layers are laminated. The plurality of layers of the sealing layer 5 may include an inorganic layer 53 and an organic layer 54. Thereby, the function of the sealing layer 5 can be enhanced. For example, gas (water vapor, etc.) barrier properties can be improved, and robustness against deformation can be improved.
１７．第１３実施形態
　図５３は、第１３実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、ダミーチップ２Ｄを含む。なお、ここでのダミーチップ２Ｄは、先に説明した第１０実施形態（図３６）のダミーチップ２Ｄとは区別して解されてよい。 17. 13th Embodiment FIG. 53 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a 13th embodiment. Photodetection device 100 includes a dummy chip 2D. Note that the dummy chip 2D here may be understood as being distinct from the dummy chip 2D of the tenth embodiment (FIG. 36) described above.
　ダミーチップ２Ｄは、チップ２の周辺間隔を狭めるために用いられる。ダミーチップ２Ｄは、チップ２と間隔をあけて隣り合うように配置される。この例では、チップ２は、互いに離間して設けられた２つのチップ２を含む。ダミーチップ２Ｄは、それら２つのチップ２どうしの間に設けられる。 The dummy chip 2D is used to narrow the peripheral interval of the chip 2. The dummy chip 2D is arranged adjacent to the chip 2 with an interval therebetween. In this example, the chips 2 include two chips 2 spaced apart from each other. The dummy chip 2D is provided between these two chips 2.
　埋め込み層３は、基板１、チップ２及びダミーチップ２Ｄを覆うように設けられる。シーム部４は、チップ２とダミーチップ２Ｄとの間の部分において、埋め込み層３の表面３ａまで延在する。ダミーチップ２Ｄが設けられる分だけ、埋め込み層３においてシーム部４が発生する部分のアスペクト比が大きくなる。ここでいうアスペクト比は、ＸＹ平面方向の長さに対するＺ軸方向の長さの比率に相当する。アスペクト比が大きくなることで、シーム部４の延在方向が制限される。シーム部４の延在方向は、チップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に近づけられる。このようなシーム部４が得られ易くなるようにアスペクト比が設計されてよい。例えば、アスペクト比は、１～３の範囲内に設計されてよい。 The buried layer 3 is provided to cover the substrate 1, chip 2, and dummy chip 2D. Seam portion 4 extends to surface 3a of buried layer 3 in a portion between chip 2 and dummy chip 2D. The aspect ratio of the portion of the buried layer 3 where the seam portion 4 occurs increases by the amount that the dummy chip 2D is provided. The aspect ratio here corresponds to the ratio of the length in the Z-axis direction to the length in the XY plane direction. By increasing the aspect ratio, the direction in which the seam portion 4 extends is restricted. The extending direction of the seam portion 4 is made close to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. The aspect ratio may be designed so that such a seam portion 4 can be easily obtained. For example, the aspect ratio may be designed within the range of 1-3.
　シーム部４は、チップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に沿って延在する。高さ方向に沿って延在するとは、高さ方向と同じ方向に延在することだけでなく、高さ方向に対してある程度の角度を有して延在する場合も含んでよい。そのような角度の上限値の例は、３０度未満、２５度未満、２０度未満、１５度未満、１０度未満、５度未満等である。角度の下限値は、０度であってよい。なお、以降では、チップ２及びダミーチップ２Ｄの高さ方向に沿って延在することを、縦方向に延在する等ともいう。 The seam portion 4 extends along the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. Extending along the height direction may include not only extending in the same direction as the height direction, but also extending at a certain angle with respect to the height direction. Examples of such upper limits for angles are less than 30 degrees, less than 25 degrees, less than 20 degrees, less than 15 degrees, less than 10 degrees, less than 5 degrees, etc. The lower limit of the angle may be 0 degrees. Note that, hereinafter, extending along the height direction of the chip 2 and the dummy chip 2D will also be referred to as extending in the vertical direction.
　シーム部４が縦方向に延在していることで、埋め込み層３及びシーム部４を覆うように封止層５を設けた際に、封止層５がシーム部４内まで延在し易くなる。これまで説明したような封止層５の延在部５ａによるメリットが得られ易くなる。 Since the seam portion 4 extends in the vertical direction, when the sealing layer 5 is provided to cover the embedded layer 3 and the seam portion 4, the sealing layer 5 easily extends into the seam portion 4. Become. The advantages of the extending portion 5a of the sealing layer 5 as described above can be easily obtained.
＜製造方法の例＞
　図５４～図５８は、光検出装置の製造方法の例を示す図である。図５４に示されるように、基板１上に、チップ２及びダミーチップ２Ｄを設ける。図５５に示されるように、基板１、チップ２及びダミーチップ２Ｄを覆うように、埋め込み層３を設ける（例えば成膜する）。成膜時のオーバーハングにより、シーム部４が発生する。すなわち、チップ２とダミーチップ２Ｄとの間の部分における底部の成膜速度に対して、チップ２上部が早く成膜される。オーバーハングにより成膜途中で埋め込み層３の材料が閉塞し、チップ２とダミーチップ２Ｄとの間は途中で成膜されずにシーム部４が発生する。ただし、ダミーチップ２Ｄを設けた分だけチップ２の周辺間隔が狭くなっているので、シーム部４の延在方向は、チップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に近づけられる。この時点では、シーム部４は空隙である。 <Example of manufacturing method>
54 to 58 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As shown in FIG. 54, a chip 2 and a dummy chip 2D are provided on a substrate 1. As shown in FIG. 55, a buried layer 3 is provided (for example, formed into a film) so as to cover the substrate 1, chip 2, and dummy chip 2D. Seam portions 4 occur due to overhang during film formation. That is, the film is formed on the upper part of the chip 2 faster than the film forming speed on the bottom part between the chip 2 and the dummy chip 2D. Due to the overhang, the material of the buried layer 3 is blocked during the film formation, and a seam portion 4 is generated between the chip 2 and the dummy chip 2D without being formed. However, since the peripheral spacing of the chips 2 is narrowed by the provision of the dummy chips 2D, the extending direction of the seam portion 4 can be brought closer to the height direction (positive Z-axis direction) of the chips 2 and the dummy chips 2D. . At this point, the seam portion 4 is a void.
　図５６に示されるように、埋め込み層３の上部を研磨し、洗浄する。シーム部４の上部が開口する。図５７に示されるように、埋め込み層３及びシーム部４を覆うように封止層５を設ける。シーム部４が縦方向に延在しているので、封止層５がシーム部４内まで延在し易くなり、その部分が、封止層５の延在部５ａになる。図５８に示されるように、封止層５を覆うように補助層６を設ける。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図５３の構成が得られる。 As shown in FIG. 56, the upper part of the buried layer 3 is polished and cleaned. The upper part of the seam part 4 is open. As shown in FIG. 57, a sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4. Since the seam portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 58, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 53 described above is obtained.
１８．第１４実施形態
　図５９は、第１４実施形態に係る光検出装置の概略構成の例を示す図である。チップ２は、表面２ａに近づくにつれて幅（ＸＹ平面方向の長さ）が小さくなる形状を有する。 18. 14th Embodiment FIG. 59 is a diagram showing an example of a schematic configuration of a photodetection device according to a 14th embodiment. The chip 2 has a shape in which the width (length in the XY plane direction) decreases as it approaches the surface 2a.
　ＸＹ平面方向において、チップ２の中央に位置する部分を、中央部２１と称し図示する。チップ２において、中央部２１よりも外側に位置し、チップ２の縁を含む部分を、縁部２２と称し図示する。チップ２の縁部２２は、チップ２の表面２ａにおいてラウンド形状を有する。なお、縁部２２は、ラウンド形状以外の形状を有してもよい。他の形状の一例は、テーパー形状である。 A portion located at the center of the chip 2 in the XY plane direction is referred to as a central portion 21 and illustrated. In the chip 2, a portion located outside the center portion 21 and including the edge of the chip 2 is referred to as an edge portion 22 and illustrated. The edge 22 of the chip 2 has a round shape on the surface 2a of the chip 2. Note that the edge portion 22 may have a shape other than a round shape. An example of another shape is a tapered shape.
　埋め込み層３は、チップ２を覆うように設けられる。シーム部４は、チップ２から埋め込み層３の表面３ａまで延在する。チップ２の表面２ａ側の幅が狭くなっていることで、シーム部４は、チップ２の高さ方向に沿って延在、すなわち縦方向に延在する。これは、チップ２の周辺、より具体的にこの例では隣り合うチップ２どうしの間の部分における底部への埋め込み層３の埋め込み性が改善されるためである。シーム部４が縦方向に延在することのメリットについては先に述べたとおりである。 The buried layer 3 is provided to cover the chip 2. Seam portion 4 extends from chip 2 to surface 3a of buried layer 3. Since the width of the chip 2 on the front surface 2a side is narrow, the seam portion 4 extends along the height direction of the chip 2, that is, extends in the vertical direction. This is because the embeddability of the embedding layer 3 in the bottom of the periphery of the chip 2, more specifically in the area between adjacent chips 2 in this example, is improved. The advantage of the seam portion 4 extending in the vertical direction is as described above.
＜製造方法の例＞
　図６０～図６４は、光検出装置の製造方法の例を示す図である。図６０に示されるように、基板１上に、表面２ａ側の幅が狭くなっているチップ２を設ける。例えば、チップ２の縁部２２の角の角度が９０度未満となるように、チップ２が加工される。加工の一例は、チップ２の表面２ａの面取りである。面取りの例は、プラズマエッチング等によるＣ面取り、Ｒ面取り等である。図６１に示されるように、基板１及びチップ２を覆うように、埋め込み層３を設ける。チップ２が上記のように加工されている分だけ、チップ２どうしの間の部分における底部への埋め込み層３の埋め込み性が改善されている。発生するシーム部４の延在方向は、チップ２の高さ方向（Ｚ軸正方向）に近づけられる。この時点では、シーム部４は空隙である。 <Example of manufacturing method>
60 to 64 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As shown in FIG. 60, a chip 2 is provided on a substrate 1, the width of which is narrower on the front surface 2a side. For example, the chip 2 is processed so that the angle of the edge 22 of the chip 2 is less than 90 degrees. An example of processing is chamfering the surface 2a of the chip 2. Examples of chamfering include C chamfering, R chamfering, etc. by plasma etching or the like. As shown in FIG. 61, a buried layer 3 is provided to cover the substrate 1 and chip 2. To the extent that the chips 2 are processed as described above, the embedding property of the embedding layer 3 to the bottom of the portion between the chips 2 is improved. The extending direction of the generated seam portion 4 is brought closer to the height direction of the chip 2 (positive Z-axis direction). At this point, the seam portion 4 is a void.
　図６２に示されるように、埋め込み層３の上部を研磨し、洗浄する。シーム部４の上部が開口する。図６３に示されるように、埋め込み層３及びシーム部４を覆うように封止層５を設ける。シーム部４が縦方向に延在しているので、封止層５がシーム部４内まで延在し易くなっており、その部分が、封止層５の延在部５ａになる。図６４に示されるように、封止層５を覆うように補助層６を設ける。補助層６の研磨及び洗浄の際も、シーム部４が封止層５で覆われているので、シーム部４は広がらない。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図５９の構成が得られる。 As shown in FIG. 62, the upper part of the buried layer 3 is polished and cleaned. The upper part of the seam part 4 is open. As shown in FIG. 63, a sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4. Since the seam portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 64, an auxiliary layer 6 is provided to cover the sealing layer 5. Even during polishing and cleaning of the auxiliary layer 6, the seam portion 4 is covered with the sealing layer 5, so the seam portion 4 does not widen. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 59 described above is obtained.
１９．第１５実施形態
　図６５は、第１５実施形態に係る光検出装置の概略構成の例を示す図である。シーム部４は、延在方向に進むにつれて幅（ＸＹ平面方向の長さ）が変化する形状を有する。シーム部４の形状は、局所的に膨らみを有する形状であってよい。 19. 15th Embodiment FIG. 65 is a diagram showing an example of a schematic configuration of a photodetection device according to a 15th embodiment. The seam portion 4 has a shape in which the width (length in the XY plane direction) changes as it progresses in the extending direction. The shape of the seam portion 4 may have a locally bulged shape.
　シーム部４は、端部４１と、中央部４２と、端部４３とを含む。中央部４２は、シーム部４の延在方向においてシーム部４の中央に位置する部分である。端部４１及び端部４３は、シーム部４の延在方向においてシーム部４の端に位置する部分である。端部４１及び端部４３は、中央部４２を挟んで互いに反対側に位置する。この例では、Ｚ軸正方向に沿って、端部４１、中央部４２及び端部４３がこの順に位置する。 The seam portion 4 includes an end portion 41, a center portion 42, and an end portion 43. The center portion 42 is a portion located at the center of the seam portion 4 in the direction in which the seam portion 4 extends. The end portion 41 and the end portion 43 are portions located at the ends of the seam portion 4 in the extending direction of the seam portion 4. The end portion 41 and the end portion 43 are located on opposite sides of the center portion 42 . In this example, the end portion 41, the center portion 42, and the end portion 43 are located in this order along the Z-axis positive direction.
　中央部４２は、端部４１及び端部４３の少なくとも一方の幅よりも大きい幅を有する。この例では、中央部４２の幅は、端部４１の幅よりも大きく、また、端部４３の幅よりも大きい。シーム部４は、その延在方向において、中央部４２が膨らんだ形状を有する。 The central portion 42 has a width larger than the width of at least one of the end portions 41 and 43. In this example, the width of the central portion 42 is greater than the width of the end portions 41 and also greater than the width of the end portions 43. The seam portion 4 has a shape in which a central portion 42 is bulged in its extending direction.
　なお、図６５に示される例では、基板１上にダミーチップ２Ｄが設けられているが、ダミーチップ２Ｄが設けられていない場合でも、局所的に膨らみを有するような形状のシーム部４は発生し得る。ダミーチップ２Ｄを設けることにより、シーム部４の延在方向を、チップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に近づけることができる。また、ダミーチップ２Ｄを設ける代わりに、先に説明した図５９のように表面２ａ側の幅が狭くなっているチップ２を用いても、同様の効果が得られる。 In the example shown in FIG. 65, the dummy chip 2D is provided on the substrate 1, but even if the dummy chip 2D is not provided, the seam portion 4 having a locally bulged shape may occur. It is possible. By providing the dummy chip 2D, the extending direction of the seam portion 4 can be made closer to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. Furthermore, instead of providing the dummy chip 2D, the same effect can be obtained by using the chip 2 whose width on the front surface 2a side is narrower as shown in FIG. 59 described above.
＜製造方法の例＞
　図６６～図６９は、光検出装置の製造方法の例を示す図である。前提として、先に説明した図５４と同様の製造プロセスが完了しているものとする。図６６に示されるように、基板１、チップ２及びダミーチップ２Ｄを覆うように、埋め込み層３を設ける（例えば成膜する）。成膜時のオーバーハングにより、シーム部４が発生する。チップ２とダミーチップ２Ｄとの間の部分における底部の成膜速度に対して、チップ２上部が早く成膜される。オーバーハングにより成膜途中で埋め込み層３の材料が閉塞し、チップ２とダミーチップ２Ｄとの間は途中で成膜されずに局所的に空隙となる。この空隙が、シーム部４になる。ダミーチップ２Ｄを設けた分だけチップ２の周辺間隔が狭くなっているので、シーム部４の延在方向は、チップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に近づけられる。 <Example of manufacturing method>
66 to 69 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As a premise, it is assumed that a manufacturing process similar to that shown in FIG. 54 described above has been completed. As shown in FIG. 66, a buried layer 3 is provided (for example, formed into a film) so as to cover the substrate 1, chip 2, and dummy chip 2D. Seam portions 4 occur due to overhang during film formation. The film is formed on the upper part of the chip 2 faster than the film on the bottom part between the chip 2 and the dummy chip 2D. Due to the overhang, the material of the buried layer 3 is blocked during the film formation, and a gap is locally formed between the chip 2 and the dummy chip 2D without the film being formed midway. This gap becomes the seam portion 4. Since the peripheral interval of the chips 2 is narrowed by the provision of the dummy chips 2D, the extending direction of the seam portion 4 is brought closer to the height direction (Z-axis positive direction) of the chips 2 and the dummy chips 2D.
　図６７に示されるように、埋め込み層３の上部を研磨し、洗浄する。シーム部４の上部が開口する。図６８に示されるように、埋め込み層３及びシーム部４を覆うように封止層５を設ける。シーム部４が縦方向に延在しているので、封止層５がシーム部４内まで延在し易くなり、その部分が、封止層５の延在部５ａになる。図６９に示されるように、封止層５を覆うように補助層６を設ける。その後、補助層６に支持基板７を貼り合わせることで、先に説明した図６５の構成が得られる。 As shown in FIG. 67, the upper part of the buried layer 3 is polished and cleaned. The upper part of the seam part 4 is open. As shown in FIG. 68, a sealing layer 5 is provided to cover the embedded layer 3 and the seam portion 4. Since the seam portion 4 extends in the vertical direction, the sealing layer 5 easily extends into the seam portion 4, and that portion becomes an extension portion 5a of the sealing layer 5. As shown in FIG. 69, an auxiliary layer 6 is provided to cover the sealing layer 5. Thereafter, by bonding the support substrate 7 to the auxiliary layer 6, the configuration shown in FIG. 65 described above is obtained.
＜小結＞
　上記の第１３実施形態～第１５実施形態に係る光検出装置１００は、例えば次のように特定される。図５３等を参照して説明したように、光検出装置１００は、チップ２と間隔をあけて隣り合うように配置されたダミーチップ２Ｄを備え、埋め込み層３は、チップ２及びダミーチップ２Ｄを覆うように設けられ、シーム部４は、チップ２とダミーチップ２Ｄとの間の部分において、埋め込み層３の表面３ａまで延在してよい。シーム部４は、チップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に沿って延在してよい。チップ２は、互いに離間して設けられた２つのチップ２を含み、ダミーチップ２Ｄは、２つのチップ２どうしの間に設けられてよい。これにより、埋め込み層３及びシーム部４を覆うように封止層５を設けた際に、封止層５がシーム部４内まで延在し易くなる。封止層５の延在部５ａによるメリットが得られ易くなる。 <Small conclusion>
The photodetecting device 100 according to the thirteenth to fifteenth embodiments described above is specified, for example, as follows. As described with reference to FIG. 53 etc., the photodetecting device 100 includes the dummy chip 2D that is arranged adjacent to the chip 2 with a space therebetween, and the buried layer 3 supports the chip 2 and the dummy chip 2D. The seam portion 4 may extend to the surface 3a of the buried layer 3 in a portion between the chip 2 and the dummy chip 2D. The seam portion 4 may extend along the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. The chips 2 include two chips 2 provided apart from each other, and the dummy chip 2D may be provided between the two chips 2. Thereby, when the sealing layer 5 is provided so as to cover the embedded layer 3 and the seam part 4, the sealing layer 5 can easily extend into the seam part 4. The advantages of the extending portion 5a of the sealing layer 5 can be easily obtained.
　図５９等を参照して説明したように、チップ２は、チップ２の表面２ａに向かうにつれて（Ｚ軸正方向に進むにつれて）幅が小さくなる形状を有してよい。チップ２の縁部２２は、チップ２の表面２ａにおいて、テーパー形状又はラウンド形状を有してよい。シーム部４は、チップ２の高さ方向（Ｚ軸方向）に沿って延在してよい。このような構成によっても、埋め込み層３及びシーム部４を覆うように封止層５を設けた際に、封止層５がシーム部４内まで延在し易くなる。 As described with reference to FIG. 59 and the like, the chip 2 may have a shape in which the width becomes smaller toward the surface 2a of the chip 2 (as it progresses in the positive direction of the Z-axis). The edge 22 of the chip 2 may have a tapered shape or a round shape on the surface 2a of the chip 2. The seam portion 4 may extend along the height direction (Z-axis direction) of the chip 2. Such a configuration also allows the sealing layer 5 to easily extend into the seam portion 4 when the sealing layer 5 is provided to cover the buried layer 3 and the seam portion 4 .
　図６５等を参照して説明したように、シーム部４は、その延在方向に進むにつれて幅が変化する形状を有してよい。シーム部４は、シーム部４の延在方向において中央に位置する中央部４２と、シーム部４の延在方向において端に位置する端部４１（端部４３でもよい）と、を含み、中央部４２は、端部４１（端部４３でもよい）の幅よりも大きい幅を有してよい。このような形状をシーム部４が有する場合でも、シーム部４の外部への連通を抑制することができる。また、例えばダミーチップ２Ｄを設けたり、或いは、表面２ａ側の幅が狭くなっているチップ２を用いたりすることで、シーム部４の延在方向をチップ２の高さ方向（Ｚ軸方向）に近づけることができる。 As described with reference to FIG. 65 and the like, the seam portion 4 may have a shape in which the width changes as it progresses in its extending direction. The seam portion 4 includes a center portion 42 located at the center in the extending direction of the seam portion 4, and an end portion 41 (or may be an end portion 43) located at an end in the extending direction of the seam portion 4. The portion 42 may have a width greater than the width of the end portion 41 (which may also be the end portion 43). Even when the seam portion 4 has such a shape, communication of the seam portion 4 to the outside can be suppressed. In addition, for example, by providing a dummy chip 2D or using a chip 2 whose width is narrower on the surface 2a side, the extending direction of the seam portion 4 can be set in the height direction of the chip 2 (Z-axis direction). can be approached.
２０．ダミーチップの配置の例
　先の第１３実施形態で説明したダミーチップ２Ｄのいくつかの配置の例について説明する。 20. Examples of Arrangement of Dummy Chips Several examples of arrangement of the dummy chips 2D described in the thirteenth embodiment will be described.
＜第１配置例＞
　図７０及び図７１は、ダミーチップの第１配置例を示す図である。図７０には、光検出装置１００の断面が模式的に示される。図７１には、図７０のＩ－Ｉ線に沿ってみたときの光検出装置１００の断面（平面レイアウト）が模式的に示される。なお、図７０に示される例では、シーム部４は延在部５ａで埋められている。図７１において、シーム部４は、簡素化され、幅を有さないように描かれる。 <First arrangement example>
70 and 71 are diagrams showing a first arrangement example of dummy chips. FIG. 70 schematically shows a cross section of the photodetector 100. FIG. 71 schematically shows a cross section (planar layout) of the photodetector 100 taken along the line II in FIG. 70. Note that in the example shown in FIG. 70, the seam portion 4 is filled with the extension portion 5a. In FIG. 71, the seam portion 4 is simplified and depicted as having no width.
　チップ２は、側面２ｃ、側面２ｄ、側面２ｅ及び側面２ｆを有する。側面２ｃ及び側面２ｄは、互いに対向する一対の側面である。側面２ｅ及び側面２ｆは、互いに対向するとともに側面２ｃ及び側面２ｄを接続する一対の側面である。なお、チップ２の側面２ｃ、側面２ｄ、側面２ｅ及び側面２ｆをとくに区別しない場合は、単にチップ２の側面とも呼ぶ。 The chip 2 has a side surface 2c, a side surface 2d, a side surface 2e, and a side surface 2f. The side surface 2c and the side surface 2d are a pair of side surfaces facing each other. The side surface 2e and the side surface 2f are a pair of side surfaces that face each other and connect the side surface 2c and the side surface 2d. In addition, when the side surface 2c, the side surface 2d, the side surface 2e, and the side surface 2f of the chip 2 are not particularly distinguished, they are also simply referred to as the side surface of the chip 2.
　図７１に示されるように、平面視したときに、ダミーチップ２Ｄは、チップ２の側面に対向するように延在する。ダミーチップ２Ｄは、各々がチップ２の異なる側面に対向する複数のダミーチップ２Ｄであってよい。 As shown in FIG. 71, the dummy chip 2D extends to face the side surface of the chip 2 when viewed in plan. The dummy chips 2D may be a plurality of dummy chips 2D, each facing a different side surface of the chip 2.
　１つのチップ２に対して２つ以上のダミーチップ２Ｄが設けられてよい。ダミーチップ２Ｄの材料は、チップ２の材料と同じ材料を含んでよい。また、ダミーチップ２Ｄは、チップ２の高さと同じ高さを有してよい。ＸＹ平面方向において、チップ２及びダミーチップ２Ｄは交互に設けられてよい。 Two or more dummy chips 2D may be provided for one chip 2. The material of the dummy chip 2D may include the same material as the material of the chip 2. Further, the dummy chip 2D may have the same height as the chip 2. In the XY plane direction, the chips 2 and the dummy chips 2D may be provided alternately.
　チップ２の周辺にダミーチップ２Ｄを設けることで、ダミーチップ２Ｄを設けない場合よりも、埋め込み層３を設ける際に（例えば成膜時に）にチップ２からその周辺に向かって埋め込み層３の材料に作用する応力を抑制することができる。 By providing the dummy chip 2D around the chip 2, the material of the buried layer 3 is reduced from the chip 2 toward the periphery when the buried layer 3 is provided (for example, during film formation), compared to when the dummy chip 2D is not provided. It is possible to suppress the stress that acts on the
　ダミーチップ２Ｄは、２つ以上のダミーチップ２Ｄを含んでよい。図７１に示される例では、ダミーチップ２Ｄは、４つのダミーチップ２Ｄを含む。チップ２の側面２ｃに対向するダミーチップ２Ｄを、ダミーチップ２Ｄ－１と称し図示する。チップ２の側面２ｄに対向するダミーチップ２Ｄを、ダミーチップ２Ｄ－２と称し図示する。チップ２の側面２ｅに対向するダミーチップ２Ｄを、ダミーチップ２Ｄ－３と称し図示する。チップ２の側面２ｆに対向するダミーチップ２Ｄを、ダミーチップ２Ｄ－４と称し図示する。図７１に示される例では、各ダミーチップ２Ｄは、互いに間隔をあけて配置されている。チップ２の角の近くにおいて、ダミーチップ２Ｄどうしが離間している。 The dummy chip 2D may include two or more dummy chips 2D. In the example shown in FIG. 71, the dummy chips 2D include four dummy chips 2D. The dummy chip 2D facing the side surface 2c of the chip 2 is shown as a dummy chip 2D-1. The dummy chip 2D facing the side surface 2d of the chip 2 is shown as a dummy chip 2D-2. The dummy chip 2D facing the side surface 2e of the chip 2 is shown as a dummy chip 2D-3. The dummy chip 2D facing the side surface 2f of the chip 2 is shown as a dummy chip 2D-4. In the example shown in FIG. 71, the dummy chips 2D are arranged at intervals from each other. Near the corners of the chip 2, the dummy chips 2D are spaced apart from each other.
　図７２は、ダミーチップの効果を示す図である。図７２の（Ａ）には、チップ２だけを設けた場合に発生し得るシーム部４Ｅ１の範囲が模式的に示される。図７２の（Ｂ）には、ダミーチップ２Ｄだけを設けた場合に発生し得るシーム部４Ｅ２の範囲が模式的に示される。図７２の（Ｃ）には、チップ２及びダミーチップ２Ｄを設けた場合に発生するシーム部４の範囲が模式的に示される。ダミーチップ２Ｄを設けることで、平面視したときのシーム部４の範囲が狭くなる。このことは、シーム部４の延在方向がチップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に近づけられること、すなわち縦方向に延在するシーム部４が得られることを意味している。 FIG. 72 is a diagram showing the effect of the dummy chip. FIG. 72A schematically shows the range of the seam portion 4E1 that may occur when only the chip 2 is provided. FIG. 72(B) schematically shows the range of the seam portion 4E2 that may occur when only the dummy chip 2D is provided. FIG. 72C schematically shows the range of the seam portion 4 that occurs when the chip 2 and the dummy chip 2D are provided. By providing the dummy chip 2D, the range of the seam portion 4 when viewed from above becomes narrower. This means that the extending direction of the seam portion 4 is brought closer to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D, that is, the seam portion 4 extending in the vertical direction is obtained. ing.
　再び図７１に戻り、ダミーチップ２Ｄは、その延在方向において、対向するチップ２の側面の長さの２分の１以上の長さを有してよい。例として、チップ２の側面２ｃの長さを、長さＨと称し図示する。チップ２の側面２ｅの長さを、長さＷと称し図示する。チップ２の側面２ｃに対向するダミーチップ２Ｄ－１の延在方向の長さを、長さＨＤと称し図示する。チップ２の側面２ｅに対向するダミーチップ２Ｄ－３の延在方向の長さを、長さＷＤと称し図示する。 Returning to FIG. 71 again, the dummy chip 2D may have a length equal to or more than half the length of the side surface of the opposing chip 2 in its extending direction. As an example, the length of the side surface 2c of the chip 2 is shown as a length H. The length of the side surface 2e of the chip 2 is shown as a length W. The length of the dummy chip 2D-1 in the extending direction facing the side surface 2c of the chip 2 is referred to as length HD in the drawing. The length of the dummy chip 2D-3 in the extending direction facing the side surface 2e of the chip 2 is referred to as a length W D in the drawing.
　ダミーチップ２Ｄ－１の長さＨＤは、下記の式（１）を満たすように設計されてよい。
　　ＨＤ≧Ｈ／２　　　（１）
　ダミーチップ２Ｄ－２も同様に設計されてよい。 The length HD of the dummy chip 2D-1 may be designed to satisfy the following formula (1).
H D ≧H/2 (1)
Dummy chip 2D-2 may be designed similarly.
　ダミーチップ２Ｄ－３は、下記の式（２）を満たすように設計されてよい。
　　ＷＤ≧Ｗ／２　　　（２）
　ダミーチップ２Ｄ－４も同様に設計されてよい。 The dummy chip 2D-3 may be designed to satisfy the following formula (2).
W D ≧W/2 (2)
Dummy chip 2D-4 may be designed similarly.
　上記のようにダミーチップ２Ｄがある程度の長さを有することで、ダミーチップ２Ｄによる効果、すなわちシーム部４の延在方向をチップ２及びダミーチップ２Ｄの高さ方向（Ｚ軸正方向）に近づけるという効果が得られ易くなる。 As described above, by having the dummy chip 2D having a certain length, the effect of the dummy chip 2D, that is, the extending direction of the seam portion 4 is brought closer to the height direction (Z-axis positive direction) of the chip 2 and the dummy chip 2D. This effect becomes easier to obtain.
　また、図７１に示される例では、ダミーチップ２Ｄは、チップ２を挟み込むように配置される。具体的に、ダミーチップ２Ｄ－１及びダミーチップ２Ｄ－２が、チップ２を挟み込むように、チップ２を挟んで互いに反対側に配置される。また、ダミーチップ２Ｄ－３及びダミーチップ２Ｄ－４が、チップ２を挟み込むように、チップ２を挟んで互いに反対側に配置される。例えばチップ２の１つの側面に対向するダミーチップ２Ｄだけを設ける場合よりも、ダミーチップ２Ｄの効果が得られる領域を広げることができる。 Furthermore, in the example shown in FIG. 71, the dummy chip 2D is arranged so as to sandwich the chip 2. Specifically, the dummy chip 2D-1 and the dummy chip 2D-2 are arranged on opposite sides of the chip 2 so as to sandwich the chip 2 therebetween. Furthermore, the dummy chip 2D-3 and the dummy chip 2D-4 are arranged on opposite sides of the chip 2 so as to sandwich the chip 2 therebetween. For example, the area where the effect of the dummy chip 2D can be obtained can be expanded compared to the case where only the dummy chip 2D is provided facing one side of the chip 2.
　チップ２、ダミーチップ２Ｄ等の光検出装置１００の構成要素は、例えば、ウェハ上のスクライブラインで区画された領域ごとに設けられてよい。スクライブラインに沿ってウェハをダイシング（切断）することで、光検出装置１００が得られる。図７３を参照して説明する。 The components of the photodetector 100, such as the chip 2 and the dummy chip 2D, may be provided in each region defined by a scribe line on the wafer, for example. The photodetector 100 is obtained by dicing (cutting) the wafer along the scribe lines. This will be explained with reference to FIG. 73.
　図７３は、ウェハの概略構成の例を示す図である。ウェアを、ウェハ２００と称し図示する。図７３には、平面視したときの（Ｚ軸負方向にみたときの）ウェハ２００の一部が模式的に示される。ウェハ２００上には、互いに直交するスクライブラインＳＬ－Ｈ及びスクライブラインＳＬ－Ｖが形成される。これらをとくに区別しない場合は、単にスクライブラインＳＬと呼ぶ。 FIG. 73 is a diagram showing an example of a schematic configuration of a wafer. The ware is referred to as a wafer 200 and illustrated. FIG. 73 schematically shows a part of the wafer 200 when viewed from above (when viewed in the negative Z-axis direction). A scribe line SL-H and a scribe line SL-V are formed on the wafer 200, which are perpendicular to each other. When these are not particularly distinguished, they are simply referred to as scribe lines SL.
　スクライブラインＳＬ－Ｈ及びスクライブラインＳＬ－Ｖで囲まれた１つの領域が、１つの光検出装置１００に相当する。この例では、光検出装置１００のチップ２及びダミーチップ２Ｄは、スクライブラインＳＬよりも内側に位置している（スクライブラインＳＬ上には位置していない）。スクライブラインＳＬに沿ってウェハ２００をダイシングして得られる１つの個片（１ｓｈｏｔ）が、光検出装置１００になる。 One area surrounded by scribe line SL-H and scribe line SL-V corresponds to one photodetector 100. In this example, the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL (not located on the scribe line SL). One piece (1 shot) obtained by dicing the wafer 200 along the scribe line SL becomes the photodetecting device 100.
　この後で説明する第２配置例～第７配置例については、主に、第１配置例との相違について述べる。矛盾の無い範囲において、第１配置例の説明が適宜援用されてよい。例えば、ダミーチップ２Ｄの材料は、チップ２の材料と同じ材料を含んでよい。ダミーチップ２Ｄは、チップ２の高さと同じ高さを有してよい。また、ダミーチップ２Ｄは、チップ２を挟み込むように配置されてよい。 Regarding the second to seventh layout examples that will be explained later, the differences from the first layout example will be mainly described. The description of the first arrangement example may be used as appropriate to the extent that there is no contradiction. For example, the material of the dummy chip 2D may include the same material as the material of the chip 2. The dummy chip 2D may have the same height as the chip 2. Further, the dummy chip 2D may be arranged to sandwich the chip 2.
＜第２配置例＞
　図７４は、ダミーチップの第２配置例を示す図である。ダミーチップ２Ｄは、チップ２を取り囲むように連続して延在する。この例では、ダミーチップ２Ｄ－１～ダミーチップ２Ｄ－４が、チップ２を取り囲むように配置されており、また、それらは連接している。チップ２の周囲がすべてダミーチップ２Ｄで囲まれており、ダミーチップ２Ｄの効果が最大限に発揮され得る。 <Second arrangement example>
FIG. 74 is a diagram showing a second arrangement example of dummy chips. The dummy chip 2D extends continuously to surround the chip 2. In this example, dummy chips 2D-1 to 2D-4 are arranged to surround chip 2, and are connected to each other. The entire periphery of the chip 2 is surrounded by the dummy chip 2D, and the effect of the dummy chip 2D can be maximized.
　図７５は、ダミーチップの効果を示す図である。説明は先の図７２と同様であるので省略する。 FIG. 75 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
　図７６は、ウェハの概略構成の例を示す図である。光検出装置１００のチップ２及びダミーチップ２Ｄは、スクライブラインＳＬよりも内側に位置している。スクライブラインＳＬに沿ってウェハ２００をダイシングすることで、光検出装置１００が得られる。 FIG. 76 is a diagram showing an example of a schematic configuration of a wafer. The chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL. The photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
＜第３配置例＞
　図７７は、ダミーチップの第３配置例を示す図である。ダミーチップ２Ｄ－１、ダミーチップ２Ｄ－２、ダミーチップ２Ｄ－３及びダミーチップ２Ｄ－４が、チップ２を取り囲むように配置されており、また、それらは離間している。 <Third arrangement example>
FIG. 77 is a diagram showing a third arrangement example of dummy chips. Dummy chip 2D-1, dummy chip 2D-2, dummy chip 2D-3, and dummy chip 2D-4 are arranged so as to surround chip 2, and are spaced apart from each other.
　ダミーチップ２Ｄ－１の側面、ダミーチップ２Ｄ－２の側面、ダミーチップ２Ｄ－３の側面及びダミーチップ２Ｄ－４の側面のうち、チップ２とは反対側に位置する側面を、側面２Ｄ－１ａ、側面２Ｄ－２ａ、側面２Ｄ－３ａ及び側面２Ｄ－４ａと称し図示する。これらの側面は、光検出装置１００の側面の一部を構成する。光検出装置１００を側方からみたときに（Ｘ軸方向又はＹ軸方向にみたときに）、側面２Ｄ－１ａ、側面２Ｄ－２ａ、側面２Ｄ－３ａ及び側面２Ｄ－４ａは、埋め込み層３から露出している（埋め込み層３によって覆われてはいない）。ダミーチップ２Ｄを光検出装置１００の最も外側に配置できる分だけ、例えばチップ２を設ける領域を確保し易くなる。 The side surface of the dummy chip 2D-1, the side surface of the dummy chip 2D-2, the side surface of the dummy chip 2D-3, and the side surface of the dummy chip 2D-4, which is located on the opposite side to the chip 2, is the side surface 2D-1a. , side surface 2D-2a, side surface 2D-3a, and side surface 2D-4a. These side surfaces constitute part of the side surfaces of the photodetector 100. When the photodetecting device 100 is viewed from the side (when viewed in the X-axis direction or the Y-axis direction), the side surface 2D-1a, the side surface 2D-2a, the side surface 2D-3a, and the side surface 2D-4a are separated from the buried layer 3. Exposed (not covered by buried layer 3). By arranging the dummy chip 2D at the outermost position of the photodetecting device 100, it becomes easier to secure an area for the chip 2, for example.
　図７８は、ダミーチップの効果を示す図である。説明は先の図７２と同様であるので省略する。 FIG. 78 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
　図７９は、ウェハの概略構成の例を示す図である。光検出装置１００のチップ２は、スクライブラインＳＬよりも内側に位置している。一方で、隣り合う光検出装置１００のダミーチップ２Ｄどうしは、スクライブラインＳＬを跨いで連接して設けられる。それらのダミーチップ２ＤがスクライブラインＳＬ上に設けられるともいえる。スクライブラインＳＬに沿ってウェハ２００及びダミーチップ２Ｄをダイシングすることで、光検出装置１００が得られる。隣り合う光検出装置１００のダミーチップ２Ｄどうしをまとめて設けることができるので、製造が容易になる。 FIG. 79 is a diagram showing an example of a schematic configuration of a wafer. The chip 2 of the photodetector 100 is located inside the scribe line SL. On the other hand, the dummy chips 2D of adjacent photodetecting devices 100 are provided in a continuous manner across the scribe line SL. It can also be said that these dummy chips 2D are provided on the scribe line SL. The photodetector 100 is obtained by dicing the wafer 200 and the dummy chips 2D along the scribe line SL. Since the dummy chips 2D of adjacent photodetecting devices 100 can be provided together, manufacturing becomes easier.
＜第４配置例＞
　図８０は、ダミーチップの第４配置例を示す図である。チップ２は、光検出装置１００の角付近に配置される。この例では、チップ２の側面２ｃ及び側面２ｅが光検出装置１００の側面の近くに位置するように、チップ２が配置される。チップ２の他の２つの側面に対向する２つのダミーチップ２Ｄが配置される。この例では、チップ２の側面２ｄに対向するダミーチップ２Ｄ－２と、チップ２の側面２ｆに対向するダミーチップ２Ｄ－４とが配置される。 <Fourth arrangement example>
FIG. 80 is a diagram showing a fourth example of arrangement of dummy chips. The chip 2 is placed near a corner of the photodetector 100. In this example, the chip 2 is arranged such that the side surface 2c and the side surface 2e of the chip 2 are located near the side surface of the photodetecting device 100. Two dummy chips 2D facing the other two sides of the chip 2 are arranged. In this example, a dummy chip 2D-2 facing the side surface 2d of the chip 2 and a dummy chip 2D-4 facing the side surface 2f of the chip 2 are arranged.
　図８１は、ダミーチップの効果を示す図である。説明は先の図７２と同様であるので省略する。 FIG. 81 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
　図８２は、ウェハの概略構成の例を示す図である。この例では、光検出装置１００のチップ２及びダミーチップ２Ｄは、スクライブラインＳＬよりも内側に位置している。スクライブラインＳＬに沿ってウェハ２００をダイシングすることで、光検出装置１００が得られる。 FIG. 82 is a diagram showing an example of a schematic configuration of a wafer. In this example, the chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL. The photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
＜第５配置例＞
　図８３は、ダミーチップの第５配置例を示す図である。ダミーチップ２Ｄ－１、ダミーチップ２Ｄ－２、ダミーチップ２Ｄ－３及びダミーチップ２Ｄ－４が、チップ２を取り囲むように配置されており、また、それらは離間している。先に説明した図７７とは異なり、光検出装置１００を側方からみたときに、ダミーチップ２Ｄ－１の側面２Ｄ－１ａ、ダミーチップ２Ｄ－２の側面２Ｄ－２ａ、ダミーチップ２Ｄ－３の側面２Ｄ－３ａ及びダミーチップ２Ｄ－４の側面２Ｄ－４ａは、埋め込み層３から露出していない（埋め込み層３によって覆われている）。 <Fifth arrangement example>
FIG. 83 is a diagram showing a fifth arrangement example of dummy chips. Dummy chip 2D-1, dummy chip 2D-2, dummy chip 2D-3, and dummy chip 2D-4 are arranged so as to surround chip 2, and are spaced apart from each other. Unlike FIG. 77 described above, when the photodetector 100 is viewed from the side, the side surface 2D-1a of the dummy chip 2D-1, the side surface 2D-2a of the dummy chip 2D-2, and the side surface 2D-2a of the dummy chip 2D-3 are The side surface 2D-3a and the side surface 2D-4a of the dummy chip 2D-4 are not exposed from the buried layer 3 (covered by the buried layer 3).
　図８４は、ダミーチップ２Ｄの効果を示す図である。説明は先の図７２と同様であるので省略する。 FIG. 84 is a diagram showing the effect of the dummy chip 2D. The explanation will be omitted since it is the same as that of FIG. 72 above.
　図８５は、ウェハの概略構成の例を示す図である。光検出装置１００のチップ２及びダミーチップ２Ｄは、スクライブラインＳＬよりも内側に位置している。先に説明した図７９とは異なり、隣り合う光検出装置１００のダミーチップ２Ｄは、スクライブラインＳＬを跨ぐことなく、互いに離れている。スクライブラインＳＬに沿ってウェハ２００をダイシングすることで、光検出装置１００が得られる。 FIG. 85 is a diagram showing an example of a schematic configuration of a wafer. The chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL. Unlike FIG. 79 described above, the dummy chips 2D of adjacent photodetecting devices 100 do not straddle the scribe line SL and are separated from each other. The photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
＜第６配置例＞
　図８６は、ウェハの概略構成の例を示す図である。チップ２は２つ以上のチップ２を含み、図８６には２つのチップ２が例示される。一方のチップ２の側面２ｅと、他方のチップ２の側面２ｆとが、互いに対向している。 <Sixth arrangement example>
FIG. 86 is a diagram showing an example of a schematic configuration of a wafer. The chip 2 includes two or more chips 2, and two chips 2 are illustrated in FIG. A side surface 2e of one chip 2 and a side surface 2f of the other chip 2 face each other.
　２つのダミーチップ２Ｄが配置される。そのうちの１つのダミーチップ２Ｄは、２つのチップ２どうしの間に配置される。このダミーチップ２Ｄを、ダミーチップ２Ｄ－３４と称し図示する。もう１つのダミーチップ２Ｄは、２つのチップ２の側面２ｄに沿って延在するように配置されるダミーチップ２Ｄ－２である。 Two dummy chips 2D are arranged. One of the dummy chips 2D is placed between the two chips 2. This dummy chip 2D is shown as a dummy chip 2D-34. Another dummy chip 2D is a dummy chip 2D-2 arranged so as to extend along the side surfaces 2d of the two chips 2.
　図８７は、ダミーチップの効果を示す図である。説明は先の図７２と同様であるので省略する。 FIG. 87 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
　図８８は、ウェハの概略構成の例を示す図である。光検出装置１００のチップ２及びダミーチップ２Ｄは、スクライブラインＳＬよりも内側に位置している。スクライブラインＳＬに沿ってウェハ２００をダイシングすることで、光検出装置１００が得られる。 FIG. 88 is a diagram showing an example of a schematic configuration of a wafer. The chip 2 and the dummy chip 2D of the photodetector 100 are located inside the scribe line SL. The photodetecting device 100 is obtained by dicing the wafer 200 along the scribe line SL.
＜第７配置例＞
　図８９は、ダミーチップの第７配置例を示す図である。先に説明した第２配置例（図７４）及び第３配置例（図７７）の利点が組み合わされる。ダミーチップ２Ｄは、チップ２を取り囲むように連続して延在する。この例では、ダミーチップ２Ｄ－１～ダミーチップ２Ｄ－４が、チップ２を取り囲むように配置されており、また、それらは連接している。加えて、光検出装置１００を側方からみたときに（Ｘ軸方向又はＹ軸方向にみたときに）、ダミーチップ２Ｄ－１の側面２Ｄ－１ａ、ダミーチップ２Ｄ－２の側面２Ｄ－２ａ、ダミーチップ２Ｄ－３の側面２Ｄ－３ａ及びダミーチップ２Ｄ－４の側面２Ｄ－４ａは、埋め込み層３から露出している。 <Seventh arrangement example>
FIG. 89 is a diagram showing a seventh example of arrangement of dummy chips. The advantages of the second arrangement example (FIG. 74) and the third arrangement example (FIG. 77) described above are combined. The dummy chip 2D extends continuously to surround the chip 2. In this example, dummy chips 2D-1 to 2D-4 are arranged to surround chip 2, and are connected to each other. In addition, when the photodetecting device 100 is viewed from the side (when viewed in the X-axis direction or Y-axis direction), the side surface 2D-1a of the dummy chip 2D-1, the side surface 2D-2a of the dummy chip 2D-2, The side surface 2D-3a of the dummy chip 2D-3 and the side surface 2D-4a of the dummy chip 2D-4 are exposed from the buried layer 3.
　図９０は、ダミーチップの効果を示す図である。説明は先の図７２と同様であるので省略する。 FIG. 90 is a diagram showing the effect of the dummy chip. The explanation will be omitted since it is the same as that of FIG. 72 above.
　図９１は、ウェハの概略構成の例を示す図である。光検出装置１００のチップ２は、スクライブラインＳＬよりも内側に位置している。一方で、隣り合う光検出装置１００のダミーチップ２Ｄどうしは、スクライブラインＳＬを跨いで連接して設けられる。スクライブラインＳＬに沿ってウェハ２００及びダミーチップ２Ｄをダイシングすることで、光検出装置１００が得られる。 FIG. 91 is a diagram showing an example of a schematic configuration of a wafer. The chip 2 of the photodetector 100 is located inside the scribe line SL. On the other hand, the dummy chips 2D of adjacent photodetecting devices 100 are provided so as to be connected across the scribe line SL. The photodetector 100 is obtained by dicing the wafer 200 and the dummy chips 2D along the scribe line SL.
＜変形例＞
　図９２及び図９３は、変形例を示す図である。。図９２には、光検出装置１００の断面が模式的に示される。図９３には、図９２のＩＩ－ＩＩ線に沿ってみたときの光検出装置１００の断面（平面レイアウト）が模式的に示される。ダミーチップ２Ｄの配置は、先に説明した第１配置例（図７０及び図７１）と同じである。ただしこの例では、封止層５は延在部５ａを有さず、シーム部４は空隙となっている。この場合でもダミーチップ２Ｄによる効果が得られる。同様に、先に説明した第２配置例から第７配置例においても、シーム部４は空隙であってよい。 <Modified example>
FIGS. 92 and 93 are diagrams showing modified examples. . FIG. 92 schematically shows a cross section of the photodetector 100. FIG. 93 schematically shows a cross section (planar layout) of the photodetector 100 taken along line II-II in FIG. 92. The arrangement of the dummy chips 2D is the same as the first arrangement example (FIGS. 70 and 71) described above. However, in this example, the sealing layer 5 does not have the extending portion 5a, and the seam portion 4 is a void. Even in this case, the effect of the dummy chip 2D can be obtained. Similarly, the seam portion 4 may be a void in the second to seventh arrangement examples described above as well.
＜小結＞
　以上で説明したようにダミーチップ２Ｄが配置された光検出装置１００は、例えば次のように特定される。図７１、図７４、図７７、図８０、図８３、図８６、図８９及び図９３等を参照して説明したように、平面視したときに（Ｚ軸負方向にみたときに）、ダミーチップ２Ｄは、チップ２の側面に対向するように延在し、延在方向において、対向するチップ２の側面の長さ（長さＨ、長さＷ）の２分の１以上の長さ（長さＨＤ、長さＷＤ）を有してよい（ＨＤ≧Ｈ／２、ＷＤ≧Ｗ／２）。このようにダミーチップ２Ｄがある程度の長さを有することで、ダミーチップ２Ｄによる効果、すなわちシーム部４の延在方向をチップ２及びダミーチップ２Ｄのチップ２の高さ方向（Ｚ軸正方向）に近づけるという効果が得られ易くなる。 <Small conclusion>
The photodetecting device 100 in which the dummy chip 2D is arranged as described above is specified, for example, as follows. As explained with reference to FIG. 71, FIG. 74, FIG. 77, FIG. 80, FIG. 83, FIG. 86, FIG. 89, FIG. The chip 2D extends so as to face the side surface of the chip 2, and has a length (in the extending direction) that is at least half the length (length H, length W) of the side surface of the chip 2 that faces the chip 2D. (H D ≧H/2, W D ≧ W/ 2 ). By having the dummy chip 2D have a certain length in this way, the effect of the dummy chip 2D, that is, the extending direction of the seam portion 4 can be adjusted in the height direction of the chip 2 (Z-axis positive direction) of the chip 2 and the dummy chip 2D. It becomes easier to obtain the effect of bringing the distance closer to .
　図７１、図７４、図７７、図８３、図８９及び図９３等を参照して説明したように、平面視したときに、ダミーチップ２Ｄは、チップ２を挟み込むように配置されてよい。ダミーチップ２Ｄは、２つ以上のダミーチップ２Ｄを含んでよい。これにより、例えばチップ２の１つの側面に対向する１つのダミーチップ２Ｄだけを設ける場合よりも、ダミーチップ２Ｄの効果が得られる領域を広げることができる。 As described with reference to FIGS. 71, 74, 77, 83, 89, and 93, the dummy chip 2D may be arranged to sandwich the chip 2 when viewed from above. The dummy chip 2D may include two or more dummy chips 2D. As a result, the area where the effect of the dummy chip 2D can be obtained can be expanded, for example, compared to the case where only one dummy chip 2D facing one side of the chip 2 is provided.
　図７０及び図７１等を参照して説明したように、ダミーチップ２Ｄの材料は、チップ２の材料と同じ材料を含んでよい。また、ダミーチップ２Ｄは、チップ２の高さ（Ｚ軸方向の長さ）と同じ高さを有してよい。例えばこのようなダミーチップ２Ｄを用いて、シーム部４の延在方向をチップ２及びダミーチップ２Ｄのチップ２の高さ方向（Ｚ軸方向）に近づけることができる。 As described with reference to FIGS. 70, 71, etc., the material of the dummy chip 2D may include the same material as the material of the chip 2. Furthermore, the dummy chip 2D may have the same height as the chip 2 (length in the Z-axis direction). For example, by using such a dummy chip 2D, the extending direction of the seam portion 4 can be brought closer to the height direction (Z-axis direction) of the chip 2 and the chip 2 of the dummy chip 2D.
　図８６等を参照して説明したように、前記チップは、２つ以上のチップを含む。例えばこのようなマルチチップ構成においても、ダミーチップ２Ｄによる効果を得ることができる。 As described with reference to FIG. 86 and the like, the chip includes two or more chips. For example, even in such a multi-chip configuration, the effect of the dummy chip 2D can be obtained.
　図７４及び図８９等を参照して説明したように、平面視したときに、ダミーチップ２Ｄは、チップ２を取り囲むように連続して延在してよい。これにより、ダミーチップ２Ｄの効果が最大限に発揮され得る。 As described with reference to FIGS. 74 and 89, the dummy chip 2D may continuously extend to surround the chip 2 when viewed in plan. Thereby, the effect of the dummy chip 2D can be maximized.
　図７７及び図８９等を参照して説明したように、光検出装置１００を側方からみたとき（Ｘ軸方向又はＹ軸方向にみたとき）に、ダミーチップ２Ｄ（例えばダミーチップ２Ｄ－１、ダミーチップ２Ｄ－２、ダミーチップ２Ｄ－３、ダミーチップ２Ｄ－４）は、埋め込み層３から露出する側面（例えば側面２Ｄ－１ａ、側面２Ｄ－２ａ、側面２Ｄ－３ａ、側面２Ｄ－４ａ）を有してよい。これにより、ダミーチップ２Ｄを光検出装置１００の最も外側に配置できる。例えばチップ２を設ける領域を確保し易くなる。また、ウェハ２００上では、隣り合う光検出装置１００のダミーチップ２Ｄどうしをまとめて設けることができるので、製造が容易になる。 As described with reference to FIGS. 77 and 89, when the photodetecting device 100 is viewed from the side (when viewed in the X-axis direction or the Y-axis direction), the dummy chips 2D (for example, the dummy chips 2D-1, Dummy chip 2D-2, dummy chip 2D-3, dummy chip 2D-4) have side surfaces exposed from buried layer 3 (for example, side surface 2D-1a, side surface 2D-2a, side surface 2D-3a, side surface 2D-4a). may have. Thereby, the dummy chip 2D can be placed at the outermost position of the photodetector 100. For example, it becomes easier to secure a region where the chip 2 is to be provided. Moreover, since the dummy chips 2D of adjacent photodetecting devices 100 can be provided together on the wafer 200, manufacturing becomes easier.
２１．第１６実施形態
　図９４は、第１６実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、封止層５に代えて、封止層５－２を含む。この例では、光検出装置１００は、補助層６は含まない。封止層５－２を介して支持基板７が接合される（貼り合わされる）。 21. 16th Embodiment FIG. 94 is a diagram showing an example of a schematic configuration of a photodetection device according to a 16th embodiment. The photodetecting device 100 includes a sealing layer 5-2 instead of the sealing layer 5. In this example, photodetector 100 does not include auxiliary layer 6. The support substrate 7 is joined (bonded) via the sealing layer 5-2.
　埋め込み層３は、チップ２の側面を覆うように設けられる。チップ２の表面２ａは、埋め込み層３から露出している。シーム部４の少なくとも一部は、埋め込み層３の材料とは異なる材料で埋められている。この例では、これまで説明した延在部５ａが、シーム部４の少なくとも一部を埋めるようにシーム部４内を延在している。 The buried layer 3 is provided to cover the side surface of the chip 2. A surface 2a of the chip 2 is exposed from the buried layer 3. At least a portion of the seam portion 4 is filled with a material different from the material of the buried layer 3. In this example, the extending portion 5a described above extends within the seam portion 4 so as to fill at least a portion of the seam portion 4.
　封止層５－２は、埋め込み層３、シーム部４、及びチップ２の表面２ａを覆うように設けられる。封止層５－２は、埋め込み層３の表面３ａだけでなくチップ２の表面２ａにも接触している。 The sealing layer 5-2 is provided to cover the buried layer 3, the seam portion 4, and the surface 2a of the chip 2. The sealing layer 5-2 is in contact not only with the surface 3a of the buried layer 3 but also with the surface 2a of the chip 2.
　封止層５－２は、シリコン（Ｓｉ）の熱伝導率よりも高い熱伝導率を有する。チップ２からの熱が伝わる部分が、封止層５－２を介して外部と熱的に接続され易くなり（熱的に露出し易くなり、熱消散等の放熱性を高めることができる。例えば埋め込み層３による放熱性の向上を狙って埋め込み層３に金属材料を用いると、チップ２との間でリークが生じて装置の信頼性が低下する可能性がある。そうではなく、封止層５－２を用いて放熱性を向上させることで、リークを抑制し、装置の信頼性を向上させることができる。 The sealing layer 5-2 has a higher thermal conductivity than that of silicon (Si). The portion to which heat from the chip 2 is transmitted is more likely to be thermally connected to the outside through the sealing layer 5-2 (easier to be thermally exposed, and heat dissipation and other heat dissipation properties can be improved. For example, If a metal material is used for the buried layer 3 with the aim of improving heat dissipation by the buried layer 3, there is a possibility that leakage may occur between the buried layer 3 and the chip 2, reducing the reliability of the device. By improving heat dissipation using 5-2, leakage can be suppressed and reliability of the device can be improved.
２２．第１７実施形態
　図９５は、第１７実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、これまで説明した補助層６に代えて、上述の封止層５－２を含む。封止層５及び封止層５－２の２つの封止層が設けられる。封止層５は、埋め込み層３及びシーム部４を覆うように設けられた第１の封止層である。封止層５－２は、封止層５を覆うように設けられた第２の封止層である。封止層５－２を介して支持基板７が接合される。このように封止層５－２を設けて放熱性を向上させることもできる。 22. 17th Embodiment FIG. 95 is a diagram showing an example of a schematic configuration of a photodetecting device according to a 17th embodiment. The photodetecting device 100 includes the above-described sealing layer 5-2 instead of the auxiliary layer 6 described above. Two sealing layers are provided: sealing layer 5 and sealing layer 5-2. The sealing layer 5 is a first sealing layer provided so as to cover the embedded layer 3 and the seam portion 4 . The sealing layer 5-2 is a second sealing layer provided to cover the sealing layer 5. Support substrate 7 is bonded via sealing layer 5-2. It is also possible to improve heat dissipation by providing the sealing layer 5-2 in this manner.
２３．第１８実施形態
　図９６は、第１８実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、先に説明した図９４の構成と比較して、封止層５－２を含まない一方で、封止層５－３を含む点において相違する。 23. 18th Embodiment FIG. 96 is a diagram showing an example of a schematic configuration of a photodetection device according to an 18th embodiment. The photodetecting device 100 differs from the configuration of FIG. 94 described above in that it does not include the sealing layer 5-2 but includes the sealing layer 5-3.
　封止層５－３は、金属層である。金属層の材料の例は、銅（Ｃｕ）、アルミニウム（Ａｌ）、タングステン（Ｗ）、チタン（Ｔｉ）、タンタル（Ｔａ）、金（Ａｕ）、銀（Ａｇ）、白金（Ｐｔ）、パラジウム（Ｐｄ）等である。封止層５－３を介して、支持基板７が接合される。このように金属層である封止層５－３を設けて放熱性を向上させることもできる。 The sealing layer 5-3 is a metal layer. Examples of materials for the metal layer include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), and palladium ( Pd) etc. Support substrate 7 is bonded via sealing layer 5-3. In this way, the sealing layer 5-3, which is a metal layer, can be provided to improve heat dissipation.
２４．第１９実施形態
　図９７は、第１９実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、先に説明した図９４の構成と比較して、封止層５－２を含まない一方で、封止層５－４を含む。 24. Nineteenth Embodiment FIG. 97 is a diagram showing an example of a schematic configuration of a photodetection device according to a nineteenth embodiment. The photodetecting device 100 does not include the sealing layer 5-2, but does include the sealing layer 5-4, compared to the configuration of FIG. 94 described above.
　封止層５－４は、封止層５－４の面方向（ＸＹ平面方向）に連接して延在する絶縁層５０及び封止層５－２を含む。絶縁層５０は、封止層５－４において、埋め込み層３及びチップ２のうちの埋め込み層３を覆う第１の部分である。封止層５－２は、埋め込み層３及びチップ２のうちの埋め込み層３を覆うように設けられる第２の部分である。 The sealing layer 5-4 includes an insulating layer 50 and a sealing layer 5-2 that extend continuously in the plane direction (XY plane direction) of the sealing layer 5-4. The insulating layer 50 is a first portion of the sealing layer 5-4 that covers the buried layer 3 and the buried layer 3 of the chip 2. The sealing layer 5-2 is a second portion provided to cover the buried layer 3 and the buried layer 3 of the chip 2.
　絶縁層５０は、その名称のとおり、絶縁性を有する。絶縁層５０の材料の例は、ＳｉＯｘ、ＳｉＮｘ、ＳｉＯＮ、ＳｉＯＣ、ＳｉＣＮ，ＳｉＣ等である。封止層５－２は、先にも述べたように、シリコンの熱伝導率よりも高い熱伝導率を有する。封止層５－２は、チップ２の表面２ａに接触するように設けられてよい。このように封止層５－２を設けて放熱性を向上させることもできる。 As its name suggests, the insulating layer 50 has insulating properties. Examples of materials for the insulating layer 50 include SiOx, SiNx, SiON, SiOC, SiCN, and SiC. As mentioned earlier, the sealing layer 5-2 has a higher thermal conductivity than that of silicon. The sealing layer 5-2 may be provided so as to be in contact with the surface 2a of the chip 2. It is also possible to improve heat dissipation by providing the sealing layer 5-2 in this manner.
２５．第２０実施形態
　図９８は、第２０実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、先に説明した図９４の構成と比較して、封止層５－２を含まない一方で、追加層９を含む点において相違する。なお、ここでの追加層９は、先に説明した第７実施形態（図７）の追加層９とは区別して解されてよい。 25. 20th Embodiment FIG. 98 is a diagram showing an example of a schematic configuration of a photodetection device according to a 20th embodiment. The photodetecting device 100 differs from the configuration of FIG. 94 described above in that it does not include the sealing layer 5-2 but includes the additional layer 9. Note that the additional layer 9 here may be understood separately from the additional layer 9 of the seventh embodiment (FIG. 7) described above.
　追加層９は、チップ２と埋め込み層３との間に設けられる。より具体的に、追加層９は、基板１及びチップ２を覆うように設けられる。埋め込み層３は、追加層９のうちのチップ２の上部に位置する部分を除き、追加層９を覆うように設けられる。 The additional layer 9 is provided between the chip 2 and the buried layer 3. More specifically, the additional layer 9 is provided to cover the substrate 1 and the chip 2. The buried layer 3 is provided to cover the additional layer 9 except for the portion of the additional layer 9 located above the chip 2 .
　この実施形態における追加層９は、金属層（バリアメタルとも呼べる）である。金属層の材料の例は、チタン（Ｔｉ）、タンタル（Ｔａ）等である。 The additional layer 9 in this embodiment is a metal layer (also called a barrier metal). Examples of materials for the metal layer are titanium (Ti), tantalum (Ta), and the like.
　シーム部４内は延在部５ａで埋められ、シーム部４は追加層９によって覆われる。埋め込み層３及び追加層９を介して支持基板７が接合される。支持基板７及び追加層９が、埋め込み層３、シーム部４及びチップ２を覆う封止層として機能し得る。このように金属層である追加層９を設けて放熱性を向上させることもできる。補助層６を設けなくてもよい分だけ、製造プロセス数を削減したり、装置の厚さを小さく（低背化）したりすることができる。 The interior of the seam portion 4 is filled with an extension portion 5a, and the seam portion 4 is covered with an additional layer 9. Support substrate 7 is bonded via buried layer 3 and additional layer 9 . The support substrate 7 and the additional layer 9 can serve as a sealing layer covering the buried layer 3 , the seam 4 and the chip 2 . It is also possible to improve heat dissipation by providing the additional layer 9, which is a metal layer, in this way. Since it is not necessary to provide the auxiliary layer 6, the number of manufacturing processes can be reduced and the thickness of the device can be reduced (lower height).
２６．第２１実施形態
　図９９は、第２１実施形態に係る光検出装置の概略構成の例を示す図である。先に説明した図９４の構成と比較して、シーム部４の一部は延在部５ａで埋められているが、残部は空隙４ａである。このような構成においても、封止層５－２を設けて放熱性を向上させることができる。空隙４ａがある分だけ、チップ２間応力が緩和され得る。先に説明した図９５～図９８の構成においても、シーム部４の一部が延在部５ａが埋められており残部が空隙４ａであってよい。 26. 21st Embodiment FIG. 99 is a diagram illustrating an example of a schematic configuration of a photodetection device according to a 21st embodiment. Compared to the configuration shown in FIG. 94 described above, a part of the seam part 4 is filled with an extension part 5a, but the remaining part is a void 4a. Even in such a configuration, the sealing layer 5-2 can be provided to improve heat dissipation. The stress between the chips 2 can be relaxed by the amount of the gap 4a. Also in the configurations of FIGS. 95 to 98 described above, part of the seam portion 4 may be filled with the extension portion 5a, and the remaining portion may be the void 4a.
２７．第２２実施形態
　図１００は、第２２実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、先に説明した図９４の構成と比較して、化合物層１４を含む点において相違する。 27. 22nd Embodiment FIG. 100 is a diagram showing an example of a schematic configuration of a photodetecting device according to a 22nd embodiment. The photodetecting device 100 differs from the configuration of FIG. 94 described above in that it includes a compound layer 14.
　化合物層１４は、チップ２と封止層５－２との間に設けられ、また、封止層５－２上にも設けられる。化合物層１４は、例えばシリサイド層であってよい。化合物層１４の材料の例は、シリコン（Ｓｉ）等の半導体材料及び金属材料を含んでよい。 The compound layer 14 is provided between the chip 2 and the sealing layer 5-2, and is also provided on the sealing layer 5-2. The compound layer 14 may be, for example, a silicide layer. Examples of materials for the compound layer 14 may include semiconductor materials such as silicon (Si) and metal materials.
　２つの化合物層１４が設けられる。１つ目の化合物層１４は、チップ２の表面２ａ上に設けられる。封止層５－２は、埋め込み層３、シーム部４及び１つ目の化合物層１４を覆うように設けられる。２つ目の化合物層１４は、封止層５－２を覆うように設けられる。この化合物層１４を介して、支持基板７が接合される。このように金属材料を含む化合物層１４を設けて放熱性を向上させることもできる。 Two compound layers 14 are provided. The first compound layer 14 is provided on the surface 2a of the chip 2. The sealing layer 5-2 is provided so as to cover the buried layer 3, the seam portion 4, and the first compound layer 14. The second compound layer 14 is provided to cover the sealing layer 5-2. The support substrate 7 is bonded via this compound layer 14. It is also possible to improve heat dissipation by providing the compound layer 14 containing a metal material in this way.
２８．第２３実施形態
　図１０１は、第２３実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、先に説明した図９４の構成と比較して、封止層５－２を含まない一方で、封止層５－５を含む点において相違する。封止層５－５は、絶縁体内に配線（ビアを含む）等の金属構造体が設けられた層である。金属構造体は、放熱経路を与えるとともに、配線として利用したりパッドとして利用したりすることができる。金属構造体の一例が、ビア５－５ｖとして符号を付して示される。このように封止層５－５を設けて放熱性を向上させることもできる。また、埋め込み層３と支持基板７との接合面部分に配線を形成することができる。 28. 23rd Embodiment FIG. 101 is a diagram showing an example of a schematic configuration of a photodetection device according to a 23rd embodiment. The photodetecting device 100 differs from the configuration of FIG. 94 described above in that it does not include the sealing layer 5-2 but includes the sealing layer 5-5. The sealing layer 5-5 is a layer in which metal structures such as wiring (including vias) are provided within an insulator. The metal structure provides a heat dissipation path and can be used as wiring or as a pad. An example of a metal structure is shown labeled as via 5-5v. Heat dissipation can also be improved by providing the sealing layer 5-5 in this manner. Furthermore, wiring can be formed on the bonding surface between the buried layer 3 and the support substrate 7.
２９．撮像装置への応用例
　上記の第１６実施形態から第２３実施形態に係る光検出装置１００の応用の一例は、撮像装置である。撮像装置については、先に図２０～図２３を参照して説明したので、詳細な説明は繰り返さない。例えば、第１６実施形態に係る光検出装置１００を撮像装置として用いる場合には、図２０～図２２における封止層５及び補助層６に代えて封止層５－２を含む構成を採用することができる。 29. Example of Application to Imaging Device An example of application of the photodetecting device 100 according to the sixteenth to twenty-third embodiments described above is an imaging device. The imaging device was previously described with reference to FIGS. 20 to 23, so detailed description will not be repeated. For example, when the photodetection device 100 according to the sixteenth embodiment is used as an imaging device, a configuration including a sealing layer 5-2 in place of the sealing layer 5 and the auxiliary layer 6 in FIGS. 20 to 22 is adopted. be able to.
３０．製造方法の例
　図１０２～図１０７は、光検出装置の製造方法の例を示す図である。図１０２～図１０５には、先に説明した図９４の構成を得るための製造方法の例が示される。前提として、先に説明した図９～図１２と同様の製造プロセスが完了しているものとする。 30. Example of Manufacturing Method FIGS. 102 to 107 are diagrams showing an example of a method of manufacturing a photodetector. 102 to 105 show an example of a manufacturing method for obtaining the structure shown in FIG. 94 described above. It is assumed that a manufacturing process similar to that shown in FIGS. 9 to 12 described above has been completed.
　図１０２に示されるように、封止層５及び埋め込み層３を研磨し、洗浄する。チップ２の表面２ａが埋め込み層３から露出する。図１０３に示されるように、埋め込み層３、シーム部４及びチップ２を覆うように、封止層５－２を設ける。図１０４に示されるように、封止層５－２を介して支持基板７を接合することで、先に説明した図９４の構成が得られる。 As shown in FIG. 102, the sealing layer 5 and the buried layer 3 are polished and cleaned. The surface 2a of the chip 2 is exposed from the buried layer 3. As shown in FIG. 103, a sealing layer 5-2 is provided to cover the buried layer 3, seam portion 4, and chip 2. As shown in FIG. 104, by bonding the support substrate 7 through the sealing layer 5-2, the configuration shown in FIG. 94 described above can be obtained.
　上記の図１０３の製造プロセスにおいてシーム部４内が封止層５によっては完全に埋め込まれずシーム部４が空隙４ａを有する場合は、先に説明した図９９の構成が得られる。上記の図１０２の製造プロセスにおいて、チップ２上に埋め込み層３が残るように研磨、洗浄し、その後に封止層５を設けた場合は、先に説明した図９５の構成が得られる。上記の図１０３の製造プロセスにおいて、封止層５－２の代わりに封止層５－３（金属層）を設けた場合は、先に説明した図９６の構成が得られる。 In the manufacturing process shown in FIG. 103 above, if the inside of the seam portion 4 is not completely filled with the sealing layer 5 and the seam portion 4 has a void 4a, the configuration shown in FIG. 99 described earlier is obtained. In the manufacturing process shown in FIG. 102 above, if the chip 2 is polished and cleaned so that the buried layer 3 remains, and then the sealing layer 5 is provided, the structure shown in FIG. 95 described above is obtained. If the sealing layer 5-3 (metal layer) is provided in place of the sealing layer 5-2 in the manufacturing process shown in FIG. 103 above, the structure shown in FIG. 96 described above is obtained.
　支持基板７の接合面の位置にはいくつかのバリエーションが存在し得る。具体的に、図１０５の（Ａ）には、接合面Ｂ、接合面Ｃ及び接合面Ｄの３通りの接合面が例示される。接合面Ｂは、支持基板７と封止層５－２との間に位置する。接合面Ｃは、封止層５－２中に位置する。接合面Ｄは、封止層５－２と埋め込み層３との間に位置する。 There may be several variations in the position of the bonding surface of the support substrate 7. Specifically, in (A) of FIG. 105, three types of bonding surfaces, bonding surface B, bonding surface C, and bonding surface D, are illustrated. Bonding surface B is located between support substrate 7 and sealing layer 5-2. The bonding surface C is located in the sealing layer 5-2. The bonding surface D is located between the sealing layer 5-2 and the buried layer 3.
　図１０５の（Ｂ）、（Ｃ）及び（Ｄ）には、接合面Ｂ、接合面Ｃ及び接合面Ｄにおいて、支持基板７、封止層５－２及び埋め込み層３をＺ軸方向に分解した図が模式的に示される。接合の過程で化合物（シリサイド）が生じ、その場合は、先に説明した図１００の構成が得られる。 In (B), (C), and (D) of FIG. 105, the supporting substrate 7, the sealing layer 5-2, and the buried layer 3 are disassembled in the Z-axis direction at the bonding surface B, bonding surface C, and bonding surface D. The diagram is shown schematically. A compound (silicide) is generated during the bonding process, and in that case, the configuration shown in FIG. 100 described above is obtained.
　図１０６及び図１０７には、先に説明した図１０１の構成を得るための製造方法の例が示される。前提として、先に説明した図１０２までの製造プロセスが完了しているものとする。 FIGS. 106 and 107 show an example of a manufacturing method for obtaining the configuration shown in FIG. 101 described above. As a premise, it is assumed that the manufacturing process up to FIG. 102 described above has been completed.
　図１０６に示されるように、埋め込み層３、シーム部４及びチップ２を覆うように、封止層５－５を設ける。図１０７に示されるように、封止層５－５を介して支持基板７を接合することで、先に説明した図１０１の構成が得られる。 As shown in FIG. 106, a sealing layer 5-5 is provided to cover the buried layer 3, seam portion 4, and chip 2. As shown in FIG. 107, the structure shown in FIG. 101 described above can be obtained by bonding the support substrate 7 through the sealing layer 5-5.
＜小結＞
　以上で説明した第１６実施形態から第２３実施形態に係る光検出装置１００は、例えば次のように特定される。図９４及び図９９等を参照して説明したように、シーム部４の少なくとも一部は、埋め込み層３の材料とは異なる材料（例えば延在部５ａ）で埋められており、封止層５－２は、シリコン（Ｓｉ）の熱伝導率よりも高い熱伝導率を有する層である。このような構成においても、シーム部４の外部への連通を抑制することができる。また、放熱性を向上させることができる。 <Small conclusion>
The photodetecting device 100 according to the sixteenth to twenty-third embodiments described above is specified, for example, as follows. As described with reference to FIGS. 94 and 99, at least a portion of the seam portion 4 is filled with a material (for example, the extension portion 5a) different from the material of the buried layer 3, and the sealing layer 5 -2 is a layer having a thermal conductivity higher than that of silicon (Si). Even in such a configuration, communication of the seam portion 4 to the outside can be suppressed. Moreover, heat dissipation can be improved.
　図９５等を参照して説明したように、光検出装置１００は、埋め込み層３及びシーム部４を覆うように設けられた封止層５（第１の封止層）と、封止層５を覆うように設けられた封止層５－２（第２の封止層）と、を備え、封止層５－２は、シリコン（Ｓｉ）の熱伝導率よりも高い熱伝導率を有してよい。このような構成によっても、放熱性を向上させることができる。 As described with reference to FIG. 95 etc., the photodetector 100 includes the sealing layer 5 (first sealing layer) provided so as to cover the embedded layer 3 and the seam portion 4, and the sealing layer 5. A sealing layer 5-2 (second sealing layer) provided to cover the silicon (Si), and the sealing layer 5-2 has a thermal conductivity higher than that of silicon (Si). You may do so. Such a configuration can also improve heat dissipation.
　図９６等を参照して説明したように、封止層５－３は、金属層であってよい。このような構成によっても、放熱性を向上させることができる。 As described with reference to FIG. 96 and the like, the sealing layer 5-3 may be a metal layer. Such a configuration can also improve heat dissipation.
　図９７等を参照して説明したように、封止層５－４は、埋め込み層３及びチップ２のうちの埋め込み層３を覆う絶縁層５０（第１の部分）と、埋め込み層３及びチップ２のうちのチップ２を覆う封止層５－２（第２の部分）と、を含み、絶縁層５０は、絶縁性を有し、封止層５－２は、シリコン（Ｓｉ）の熱伝導率よりも高い熱伝導率を有してよい。このような構成によっても、放熱性を向上させることができる。 As described with reference to FIG. 97 etc., the sealing layer 5-4 includes an insulating layer 50 (first portion) that covers the buried layer 3 of the buried layer 3 and the chip 2, and an insulating layer 50 (first portion) that covers the buried layer 3 and the chip 2. The insulating layer 50 has an insulating property, and the sealing layer 5-2 includes a sealing layer 5-2 (second portion) that covers the chip 2 of the silicon (Si). It may have higher thermal conductivity than conductivity. Such a configuration can also improve heat dissipation.
　図９８等を参照して説明したように、光検出装置１００は、チップ２と埋め込み層３との間に設けられた追加層９を備え、追加層９は、金属層であってよい。このような構成によっても、放熱性を向上させることができる。 As described with reference to FIG. 98 and the like, the photodetector 100 includes the additional layer 9 provided between the chip 2 and the buried layer 3, and the additional layer 9 may be a metal layer. Such a configuration can also improve heat dissipation.
　図１００等を参照して説明したように、光検出装置１００は、チップ２と封止層５－２との間に設けられた化合物層１４を備え、化合物層１４は、シリサイド層であってよい。このような構成によっても、放熱性を向上させることができる。 As described with reference to FIG. 100 etc., the photodetector 100 includes the compound layer 14 provided between the chip 2 and the sealing layer 5-2, and the compound layer 14 is a silicide layer. good. Such a configuration can also improve heat dissipation.
　図１０１等を参照して説明したように、封止層５－５は、絶縁体内に金属構造体（例えばビア５－５ｖ等）が設けられた層であってよい。このような構成によっても、放熱性を向上させることができる。支持基板７が接合される場合には、その接合面部分に配線を形成することもできる。 As described with reference to FIG. 101 and the like, the sealing layer 5-5 may be a layer in which a metal structure (for example, a via 5-5v, etc.) is provided within an insulator. Such a configuration can also improve heat dissipation. When the support substrate 7 is bonded, wiring can also be formed on the bonding surface portion.
３１．第２４実施形態
　図１０８及び図１０９は、第２４実施形態に係る光検出装置の概略構成の例を示す図である。なお、支持基板７の図示は省略し、この点は以降の図も同様である。光検出装置１００は、封止層５に代えて、封止層５－６を含む。封止層５－６は、樹脂層である。封止層５－６の面のうち、Ｚ軸正方向側の面を、表面５－６ａと称し図示する。 31. 24th Embodiment FIGS. 108 and 109 are diagrams showing an example of a schematic configuration of a photodetection device according to a 24th embodiment. Note that illustration of the support substrate 7 is omitted, and this point is also the same in subsequent figures. The photodetecting device 100 includes a sealing layer 5-6 instead of the sealing layer 5. The sealing layer 5-6 is a resin layer. Among the surfaces of the sealing layer 5-6, the surface on the Z-axis positive direction side is referred to as a surface 5-6a in the drawing.
　図１０９には、チップ２とその上部に位置する埋め込み層３及び封止層５を含む部分の拡大図が模式的に示される。埋め込み層３は、表面３ａにおいて凹凸形状を有する。具体的に、埋め込み層３の表面３ａは、凹部３ｃ１及び凸部３ｃ２を有する。凹部３ｃ１は、下方（Ｚ軸正方向）に向かってへこむ凹形状を有する。凸部３ｃ２は、上方（Ｚ軸正方向）に向かって突出する凸形状を有する。 FIG. 109 schematically shows an enlarged view of a portion including the chip 2, the buried layer 3 located above it, and the sealing layer 5. The buried layer 3 has an uneven shape on the surface 3a. Specifically, the surface 3a of the buried layer 3 has a concave portion 3c1 and a convex portion 3c2. The recessed portion 3c1 has a concave shape that is recessed downward (in the Z-axis positive direction). The convex portion 3c2 has a convex shape that protrudes upward (in the Z-axis positive direction).
　封止層５－６は、凹部３ｃ１を埋めるとともに、凹部３ｃ１及び凸部３ｃ２を覆うように設けられた樹脂層である。樹脂層は、酸化層又は有機層であってよい。酸化層は、例えば酸化膜系の絶縁膜であってもよいし、酸化膜系の接合膜であってもよい。有機層は、例えば４００℃以上の耐熱性を有してよい。そのような有機層の材料の例は、ポリイミド、シロキサン、シリコーン等である。後工程において４００℃程度の熱に晒された場合でも熱に耐えることができる。 The sealing layer 5-6 is a resin layer provided to fill the recess 3c1 and cover the recess 3c1 and the projection 3c2. The resin layer may be an oxidized layer or an organic layer. The oxide layer may be, for example, an oxide-based insulating film or an oxide-based bonding film. The organic layer may have a heat resistance of, for example, 400° C. or higher. Examples of materials for such organic layers are polyimides, siloxanes, silicones, etc. It can withstand heat even when exposed to heat of about 400°C in a post-process.
　封止層５－６は、製造時には、塗布液の形態で埋め込み層３上に塗布されてよい。これにより、凹部３ｃ１が封止層５－６によって埋められ易くなり、また、封止層５－６がシーム部４内まで延在し易くなる。コンフォーマルな成膜方法ではないため、塗布後の表面は、塗布前よりも平坦な面になる。図１０９に示される例では、封止層５－６の表面５－６ａは、平坦面である。すなわち、封止層５－６によって、埋め込み層３の表面３ａの凹部３ｃ１及び凸部３ｃ２の形状が吸収され、平坦な表面５－６ａが得られる。 The sealing layer 5-6 may be coated on the buried layer 3 in the form of a coating liquid during manufacturing. This makes it easier to fill the recess 3c1 with the sealing layer 5-6, and also makes it easier for the sealing layer 5-6 to extend into the seam portion 4. Since it is not a conformal film formation method, the surface after application is flatter than before application. In the example shown in FIG. 109, the surface 5-6a of the sealing layer 5-6 is a flat surface. That is, the sealing layer 5-6 absorbs the shapes of the concave portions 3c1 and convex portions 3c2 on the surface 3a of the buried layer 3, resulting in a flat surface 5-6a.
＜製造方法の例＞
　図１１０～図１１４は、光検出装置の製造方法の例を示す図である。図１１０に示されるように、基板１上にチップ２を設け、また、それらを覆うように埋め込み層３を設ける。埋め込み層３内にシーム部４が発生する。図１１１に示されるように、ドライエッチング等を含むリソグラフィのプロセスにより、チップ２の角の上部を残し、チップ２上の埋め込み層３を取り除く。チップ２の角の上部に残る埋め込み層３を、角部３ｈと称し図示する。角部３ｈを残すことで、チップ２の外側部分を保護し、チップ２の外側の埋め込み層３が抜けてしまうのを防ぐことができる。 <Example of manufacturing method>
110 to 114 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As shown in FIG. 110, chips 2 are provided on a substrate 1, and a buried layer 3 is provided to cover them. A seam portion 4 is generated within the buried layer 3. As shown in FIG. 111, the buried layer 3 on the chip 2 is removed by a lithography process including dry etching, leaving the upper part of the corner of the chip 2. The buried layer 3 remaining above the corner of the chip 2 is shown as a corner 3h. By leaving the corner portion 3h, the outer portion of the chip 2 can be protected and the embedded layer 3 on the outer side of the chip 2 can be prevented from falling out.
　図１１２に示されるように、埋め込み層３をさらに設ける。この例では、チップ２の上部における埋め込み層３内にもシーム部４が発生する。図１１３に示されるように、ＣＭＰにより、角部３ｈを取り除く。ここでのＣＭＰは、通常のＣＭＰとはスラリーの組成等が異なり、ある程度平坦になった段階で終了する（Ｓｅｌｆ－ｓｔｏｐ　ＣＭＰ）。図１１４に示されるように、埋め込み層３及びシーム部４を覆うように封止層５－６を設ける。封止層５－６は、その材料（樹脂材料）を塗布することによって設けられる。その際に、封止層５－６の材料がシーム部４内まで延在し、その部分が封止層５－６の延在部５ａになる。また、先に図１０９を参照して説明した埋め込み層３の表面３ａの凹部３ｃ１が、封止層５－６で埋められる。その後、封止層５を覆うように補助層６を設けることで、先に説明した図１０８及び図１０９の構成が得られる。 As shown in FIG. 112, a buried layer 3 is further provided. In this example, a seam 4 also occurs within the buried layer 3 at the top of the chip 2. As shown in FIG. 113, the corner 3h is removed by CMP. The CMP here differs from normal CMP in the slurry composition, etc., and ends when the slurry becomes somewhat flat (Self-stop CMP). As shown in FIG. 114, a sealing layer 5-6 is provided to cover the buried layer 3 and the seam portion 4. The sealing layer 5-6 is provided by applying the material (resin material). At this time, the material of the sealing layer 5-6 extends into the seam portion 4, and that portion becomes the extended portion 5a of the sealing layer 5-6. Furthermore, the recess 3c1 in the surface 3a of the buried layer 3, which was previously explained with reference to FIG. 109, is filled with the sealing layer 5-6. Thereafter, by providing the auxiliary layer 6 to cover the sealing layer 5, the configurations shown in FIGS. 108 and 109 described above are obtained.
　なお、上記の製造方法において、リソグラフィとその後の埋め込み層３の成膜のプロセス（図１１１及び図１１２のプロセス）は省略してもよい。 Note that in the above manufacturing method, the lithography and subsequent process of forming the buried layer 3 (the process shown in FIGS. 111 and 112) may be omitted.
＜製造方法の例＞
　図１１５～図１１９は、光検出装置の製造方法の例を示す図である。前述の図１１０～図１１４の製造方法と比較して、封止層５－６を設ける前にＣＭＰのプロセスが加えられる。前提として、先に説明した図１１１の製造プロセスが完了しているものとする。 <Example of manufacturing method>
115 to 119 are diagrams illustrating an example of a method for manufacturing a photodetecting device. Compared to the manufacturing method shown in FIGS. 110 to 114 described above, a CMP process is added before providing the sealing layer 5-6. As a premise, it is assumed that the manufacturing process shown in FIG. 111 described above has been completed.
　図１１５に示されるように、埋め込み層３をさらに設ける。ここで追加される埋め込み層３の厚さ（Ｚ軸方向の長さ）は、先に説明した図１１２の埋め込み層３の厚さよりも大きくてよい。図１１６に示されるように、Ｓｅｌｆ－ｓｔｏｐ　ＣＭＰにより、角部３ｈを取り除く。図１１７に示されるように、ＣＭＰにより、埋め込み層３の上部を研磨、洗浄する。このＣＭＰに際して、チップ２の角に対応する部分の埋め込み層３が丸みを有する（Ｒができる）。 As shown in FIG. 115, a buried layer 3 is further provided. The thickness (length in the Z-axis direction) of the buried layer 3 added here may be greater than the thickness of the buried layer 3 in FIG. 112 described above. As shown in FIG. 116, the corner 3h is removed by self-stop CMP. As shown in FIG. 117, the upper part of the buried layer 3 is polished and cleaned by CMP. During this CMP, the portions of the buried layer 3 corresponding to the corners of the chip 2 are rounded (rounded).
　図１１８に示されるように、埋め込み層３及びシーム部４を覆うように封止層５－６を設ける。図１１９に示されるように、封止層５を覆うように補助層６を設ける。チップ２の角に対応する部分の埋め込み層３が丸みを有する点を除き、先に説明した図１０８及び図１０９と同様の構成が得られる。 As shown in FIG. 118, a sealing layer 5-6 is provided to cover the buried layer 3 and seam portion 4. As shown in FIG. 119, an auxiliary layer 6 is provided to cover the sealing layer 5. A structure similar to that shown in FIGS. 108 and 109 described above is obtained, except that the buried layer 3 in the portions corresponding to the corners of the chip 2 are rounded.
　なお、上記の製造方法において、リソグラフィとその後の埋め込み層３の成膜さらにはＳｅｌｆ－ｓｔｏｐ　ＣＭＰのプロセス（図１１１、図１１５及び図１１６のプロセス）は省略してよい。 Note that in the above manufacturing method, the lithography, the subsequent film formation of the buried layer 3, and the self-stop CMP process (the processes in FIGS. 111, 115, and 116) may be omitted.
　ＣＭＰによって埋め込み層３の上部を研磨した際に、埋め込み層３の表面３ａが凹部３ｃ１及び凸部３ｃ２を有し得る。図１２０及び図１２１を参照して説明する。 When the upper part of the buried layer 3 is polished by CMP, the surface 3a of the buried layer 3 may have a concave portion 3c1 and a convex portion 3c2. This will be explained with reference to FIGS. 120 and 121.
　図１２０及び図１２１は、ＣＭＰの例を示す図である。なお、理解を容易にするため、シーム部４の図示は省略する。 120 and 121 are diagrams showing examples of CMP. Note that for ease of understanding, illustration of the seam portion 4 is omitted.
　図１２０には、先に説明した図１１３及び図１１６において行われるＳｅｌｆ－ｓｔｏｐ　ＣＭＰが模式に示される。この例では、セリア砥粒Ｐａ及び添加剤Ａｄを含むスラリーを用いて、埋め込み層３（例えばＳｉＯ２等の酸化膜）の上部が研磨され、角部３ｈが取り除かれる。完全な平坦化が難しい場合もあり、この例では、埋め込み層３が凹部３ｃ１及び凸部３ｃ２を有する。例えば、削られずに残った角部３ｈの残部（角残り）、角残りどうしの間に生じるスリット、シーム部４等が、凹部３ｃ１及び凸部３ｃ２になり得る。 FIG. 120 schematically shows the Self-stop CMP performed in FIGS. 113 and 116 described above. In this example, the upper part of the buried layer 3 (for example, an oxide film such as SiO2) is polished using a slurry containing ceria abrasive grains Pa and an additive Ad, and the corner portion 3h is removed. In some cases, complete planarization is difficult, and in this example, the buried layer 3 has a concave portion 3c1 and a convex portion 3c2. For example, the remaining portions of the corner portions 3h (remaining corners) that are not cut, the slits that occur between the remaining corner portions, the seam portions 4, etc. may become the recessed portions 3c1 and the convex portions 3c2.
　図１２１には、先に説明した図１１７において行われるＣＭＰが模式的に示される。図１２１の（Ａ）に示されるように、研磨ＰＡＤを用いて、埋め込み層３の上部が研磨される。セリア砥粒Ｐａは埋め込み層３に吸着せずに遊離して存在する。図１２１の（Ｂ）に示されるように、チップ２の角の上方に位置する埋め込み層３の凹部３ｃ１及び凸部３ｃ２においてスラリー溜りが生じ、局所応力が大きくなり、研磨が進行する。比較的広い幅（ＸＹ平面方向の長さ）を有する凸部３ｃ２の先端の平坦部分は、添加剤Ａｄの効果で研磨が阻害される。 FIG. 121 schematically shows the CMP performed in FIG. 117 described above. As shown in FIG. 121(A), the upper part of the buried layer 3 is polished using a polishing PAD. The ceria abrasive grains Pa are not adsorbed to the buried layer 3 and exist freely. As shown in FIG. 121(B), slurry pools are generated in the concave portions 3c1 and convex portions 3c2 of the buried layer 3 located above the corners of the chip 2, local stress increases, and polishing progresses. Polishing of the flat portion at the tip of the convex portion 3c2 having a relatively wide width (length in the XY plane direction) is inhibited by the effect of the additive Ad.
　例えば上記のような理由から、製造プロセスにおいて、埋め込み層３が凹部３ｃ１及び凸部３ｃ２を有するようになる。凹部３ｃ１を埋めるとともに凹部３ｃ１及び凸部３ｃ２を覆うように封止層５－６（樹脂層）を設けることで、凹部３ｃ１及び凸部３ｃ２が吸収され、平坦な表面５－６ａが得られる。 For example, for the reasons mentioned above, the buried layer 3 comes to have a recess 3c1 and a projection 3c2 in the manufacturing process. By providing the sealing layer 5-6 (resin layer) so as to fill the recess 3c1 and cover the recess 3c1 and the projection 3c2, the recess 3c1 and the projection 3c2 are absorbed and a flat surface 5-6a is obtained.
３２．第２５実施形態
　図１２２は、第２５実施形態に係る光検出装置の概略構成の例を示す図である。光検出装置１００は、封止層５に代えて、樹脂層１５を含む。樹脂層１５は、先に説明した封止層５－６と同様に、酸化層又は有機層である。樹脂層１５の材料は、封止層５－６の材料と同じであってよい。 32. 25th Embodiment FIG. 122 is a diagram showing an example of a schematic configuration of a photodetection device according to a 25th embodiment. The photodetecting device 100 includes a resin layer 15 instead of the sealing layer 5. The resin layer 15 is an oxidized layer or an organic layer, similar to the sealing layer 5-6 described above. The material of the resin layer 15 may be the same as the material of the sealing layer 5-6.
　樹脂層１５は、チップ２と埋め込み層３との間に設けられる。この例では、樹脂層１５は、基板１と、チップ２の側面とを覆うように設けられる。ただし、チップ２の側面だけでなく表面２ａも樹脂層１５で覆われていてよい。 The resin layer 15 is provided between the chip 2 and the buried layer 3. In this example, the resin layer 15 is provided to cover the substrate 1 and the side surfaces of the chip 2. However, not only the side surface of the chip 2 but also the surface 2a may be covered with the resin layer 15.
　チップ２を樹脂層１５で覆うことにより、チップ２部分の形状、例えば基板１との段差部分の形状が緩やかになる。その分、シーム部４が発生しにくくなる。仮にシーム部４が発生した場合でも、補助層６が埋め込み層３及びシーム部４を覆う封止層として機能することで、これまで説明したように、シーム部４の外部への連通を抑制することができる。 By covering the chip 2 with the resin layer 15, the shape of the chip 2 portion, for example, the shape of the stepped portion with respect to the substrate 1 becomes gentle. Accordingly, the seam portion 4 is less likely to occur. Even if a seam portion 4 occurs, the auxiliary layer 6 functions as a sealing layer that covers the buried layer 3 and the seam portion 4, thereby suppressing communication of the seam portion 4 to the outside, as explained above. be able to.
＜製造方法の例＞
　図１２３～図１２８は、光検出装置の製造方法の例を示す図である。図１２３に示されるように、基板１上にチップ２を設け、それらを覆うように樹脂層１５を設ける。図１２４に示されるように、樹脂層１５（この例ではチップ２の表面２ａも）を覆うように、埋め込み層３を設ける。この例では埋め込み層３内にはシーム部４は発生しない。図１２５に示されるように、ドライエッチング等を含むリソグラフィのプロセスにより、角部３ｈを残すように埋め込み層３を取り除く。 <Example of manufacturing method>
123 to 128 are diagrams illustrating an example of a method for manufacturing a photodetecting device. As shown in FIG. 123, chips 2 are provided on a substrate 1, and a resin layer 15 is provided to cover them. As shown in FIG. 124, the buried layer 3 is provided so as to cover the resin layer 15 (also the surface 2a of the chip 2 in this example). In this example, no seam portion 4 is generated within the buried layer 3. As shown in FIG. 125, the buried layer 3 is removed by a lithography process including dry etching or the like so as to leave the corner 3h.
　図１２６に示されるように、埋め込み層３をさらに設ける。図１２７に示されるように、ＣＭＰにより、角部３ｈを取り除く（Ｓｅｌｆ－ｓｔｏｐ　ＣＭＰ）。図１２８に示されるように、ＣＭＰにより、埋め込み層３の上部を研磨、洗浄する。その後、埋め込み層３を覆うように補助層６を設けることで、先に説明した図１２２の構成が得られる。 As shown in FIG. 126, a buried layer 3 is further provided. As shown in FIG. 127, the corner 3h is removed by CMP (Self-stop CMP). As shown in FIG. 128, the upper part of the buried layer 3 is polished and cleaned by CMP. Thereafter, by providing the auxiliary layer 6 so as to cover the buried layer 3, the structure shown in FIG. 122 described above is obtained.
　なお、上記の製造方法において、リソグラフィとその後の埋め込み層３の成膜さらにはＳｅｌｆ－ｓｔｏｐ　ＣＭＰのプロセス（図１２５～図１２７のプロセス）は省略してよい。 Note that in the above manufacturing method, the lithography, the subsequent film formation of the buried layer 3, and the self-stop CMP process (the processes shown in FIGS. 125 to 127) may be omitted.
＜小結＞
　以上で説明した第２４実施形態及び第２５実施形態に係る光検出装置１００は、例えば次のように特定される。図１０８及び図１０９等を参照して説明したように、封止層５－６は、樹脂層（例えば酸化層又は有機層）であってよい。埋め込み層３の表面３ａは、凹部３ｃ１を有し、封止層５－６は、凹部３ｃ１を埋めるように設けられてよい。封止層５－６の表面５－６ａは、平坦面であってよい。これにより、埋め込み層３の表面３ａが有する凹部３ｃ１を吸収し、平坦な表面（表面５－６ａ）を得ることができる。 <Small conclusion>
The photodetecting device 100 according to the twenty-fourth embodiment and the twenty-fifth embodiment described above is specified, for example, as follows. As described with reference to FIGS. 108 and 109, the sealing layer 5-6 may be a resin layer (for example, an oxide layer or an organic layer). The surface 3a of the buried layer 3 may have a recess 3c1, and the sealing layer 5-6 may be provided to fill the recess 3c1. The surface 5-6a of the sealing layer 5-6 may be a flat surface. As a result, the recesses 3c1 of the surface 3a of the buried layer 3 can be absorbed, and a flat surface (surface 5-6a) can be obtained.
　有機層である封止層５－６は、４００℃以上の耐熱性を有してよい。有機層の材料は、ポリイミド、シロキサン及びシリコーンの少なくとも１つを含んでよい。これにより、例えば後工程において４００℃程度の熱に晒された場合でも熱に耐えることができる。 The sealing layer 5-6, which is an organic layer, may have heat resistance of 400° C. or higher. The material of the organic layer may include at least one of polyimide, siloxane, and silicone. This makes it possible to withstand heat, for example, even when exposed to heat of about 400° C. in a post-process.
　図１２２等を参照して説明したように、光検出装置１００は、チップ２と埋め込み層３との間に設けられた樹脂層１５（例えば酸化層又は有機層）を備えてよい。これにより、シーム部４の発生を抑制することができる。 As described with reference to FIG. 122 and the like, the photodetector 100 may include the resin layer 15 (for example, an oxide layer or an organic layer) provided between the chip 2 and the buried layer 3. Thereby, the occurrence of seam portions 4 can be suppressed.
　樹脂層１５は、上述の封止層５－６と同様の特性を有してよい。例えば、有機層である樹脂層１５は、４００℃以上の耐熱性を有してよい。有機層の材料は、ポリイミド、シロキサン及びシリコーンの少なくとも１つを含んでよい。これにより、例えば後工程において４００℃程度の熱に晒された場合でも熱に耐えることができる。 The resin layer 15 may have the same characteristics as the sealing layer 5-6 described above. For example, the resin layer 15, which is an organic layer, may have heat resistance of 400° C. or higher. The material of the organic layer may include at least one of polyimide, siloxane, and silicone. This makes it possible to withstand heat, for example, even when exposed to heat of about 400° C. in a post-process.
　以上、本開示の実施形態について説明したが、本開示の技術的範囲は、上述の実施形態そのままに限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。また、異なる実施形態及び変形例にわたる構成要素を適宜組み合わせてもよい。 Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments as they are, and various changes can be made without departing from the gist of the present disclosure. Furthermore, components of different embodiments and modifications may be combined as appropriate.
　なお、本技術は以下のような構成も取ることができる。
（１）
　光検出素子を含む基板と、
　前記基板に対して設けられたチップと、
　前記チップを覆うように設けられた埋め込み層と、
　前記埋め込み層内に発生し、前記埋め込み層の表面まで延在しているシーム部と、
　前記埋め込み層及び前記シーム部を覆うように設けられた封止層と、
　を備える、
　光検出装置。
（２）
　前記封止層を挟んで前記基板とは反対側に位置し、前記封止層を直接的又は間接的に支持する支持基板を備える、
　（１）に記載の光検出装置。
（３）
　前記シーム部の少なくとも一部は、空隙である、
　（１）又は（２）に記載の光検出装置。
（４）
　前記封止層は、前記シーム部の少なくとも一部を埋めるように前記シーム部内まで延在する延在部を含む、
　（１）～（３）のいずれかに記載の光検出装置。
（５）
　前記封止層の材料は、低浸透性材料を含む、
　（１）～（４）のいずれかに記載の光検出装置。
（６）
　前記封止層の材料は、低ヤング率材料を含む、
　（１）～（５）のいずれかに記載の光検出装置。
（７）
　前記チップの側面を覆うように設けられた側壁部を備える、
　（１）～（６）のいずれかに記載の光検出装置。
（８）
　前記チップは、互いに離間して設けられた第１のチップ及び第２のチップを含み、
　前記シーム部は、前記第１のチップに起因して発生した第１のシーム部及び前記第２のチップに起因して発生した第２のシーム部を含み、
　前記第１のシーム部及び前記第２のシーム部は、互いにつながっている、
　（１）～（７）のいずれかに記載の光検出装置。
（９）
　前記チップと前記埋め込み層との間に設けられた追加層を備える、
　（１）～（８）のいずれかに記載の光検出装置。
（１０）
　前記封止層を覆うように設けられた補助層を備える、
　（１）～（９）のいずれかに記載の光検出装置。
（１１）
　前記補助層は、積層構造を有する、
　（１０）に記載の光検出装置。
（１２）
　前記チップは、ロジックチップ、メモリチップ及びＡＩ（Artificial　Intelligence）チップの少なくとも１つを含む、
　（１）～（１１）のいずれかに記載の光検出装置。
（１３）
　複数の画素を含むように構成された撮像装置である、
　（１）～（１２）のいずれかに記載の光検出装置。
（１４）
　前記基板を挟んで前記チップ及び前記埋め込み層とは反対側に設けられたフィルタ層と、
　前記フィルタ層を挟んで前記基板とは反対側に設けられたレンズ層と、
　を備える、
　（１３）に記載の光検出装置。
（１５）
　前記基板と前記埋め込み層との間に設けられた追加基板を備える、
　（１）～（１４）のいずれかに記載の光検出装置。
（１６）
　前記チップは、間隔をあけて隣り合うように配置された２つのチップを含み、
　前記埋め込み層は、前記２つのチップどうしの間に設けられた配線を含む、
　（１）～（１５）のいずれかに記載の光検出装置。
（１７）
　前記封止層を挟んで前記基板とは反対側に設けられ、前記封止層を直接的又は間接的に支持する支持基板と、
　前記埋め込み層、前記封止層及び前記支持基板を貫通する貫通ビアと、
　を備える、
　（１）～（１６）のいずれかに記載の光検出装置。
（１８）
　前記チップは、
　第1のチップと、
　前記第１のチップの厚さよりも大きい厚さを有する第２のチップと、
　を含み、
　前記シーム部は、
　前記第１のチップから前記埋め込み層の表面に向かって延在する第１のシーム部と、
　前記第２のチップから前記埋め込み層の表面に向かって延在する第２のシーム部と、
　を含み、
　前記第２のシーム部は、前記第１のシーム部よりも、前記埋め込み層の表面の近くまで延在している、
　（１）～（１７）のいずれかに記載の光検出装置。
（１９）
　前記チップは、
　第１のチップと、
　順に積層された第２のチップ及び第３のチップを含み、
　前記第２のチップ及び前記第３のチップは、全体として、前記第１のチップの厚さよりも大きい厚さを有し、
　前記シーム部は、
　前記第１のチップから前記埋め込み層の表面に向かって延在する第１のシーム部と、
　前記第２のチップから前記埋め込み層の表面に向かって延在する第２のシーム部と、
　を含み、
　前記第２のシーム部は、前記第１のシーム部よりも、前記埋め込み層の表面の近くまで延在している、
　（１）～（１８）のいずれかに記載の光検出装置。
（２０）
　前記封止層は、前記第２のシーム部の少なくとも一部を埋めるように前記第２のシーム部内まで延在する延在部を含む、
　（１８）又は（１９）に記載の光検出装置。
（２１）
　前記第１のシーム部は、前記埋め込み層の表面に到達しておらず、
　前記第２のシーム部は、前記埋め込み層の表面に到達している、
　（１８）～（２０）のいずれかに記載の光検出装置。
（２２）
　前記チップは、高さ方向に並んで位置する下方チップ及び上方チップを含み、
　前記光検出装置は、前記下方チップと前記上方チップとの間に設けられた接合層をさらに備え、
　前記埋め込み層は、
　前記下方チップの側面を覆うように設けられた下方埋め込み層と、
　前記上方チップ及び前記接合層を覆うように設けられた上方埋め込み層と、
　を含み、
　前記シーム部は、
　前記下方埋め込み層内に発生し、前記下方埋め込み層の表面まで延在する下方シーム部と、
　前記上方埋め込み層内に発生し、前記上方埋め込み層の表面まで延在する上方シーム部と、
　を含み、
　前記接合層は、前記下方埋め込み層及び前記下方シーム部を覆うように設けられ、
　前記封止層は、前記上方埋め込み層及び前記上方シーム部を覆うように設けられる、
　（１）～（２１）のいずれかに記載の光検出装置。
（２３）
　前記チップは、前記接合層を挟んで互いに反対側に設けられた下方チップ及びダミーチップをさらに含み、
　前記上方埋め込み層は、前記上方チップ、前記ダミーチップ及び前記接合層を覆うように設けられる、
　（２２）に記載の光検出装置。
（２４）
　前記封止層は、
　前記シーム部を覆う第１の部分と、
　前記シーム部を覆わない第２の部分と、
　を含み、
　前記第１の部分の裏面は、前記第２の部分の裏面よりも下方に位置している、
　（１）～（２３）のいずれかに記載の光検出装置。
（２５）
　前記第１の部分の表面は、前記第２の部分の表面と同じ高さに位置している、
　（２４）に記載の光検出装置。
（２６）
　前記封止層を覆うように設けられた補助層を備え、
　前記第２の部分の表面は、前記第１の部分の表面よりも上方に位置しており、
　前記補助層の表面は、平坦面である、
　（２４）に記載の光検出装置。
（２７）
　前記封止層は、複数の層が積層された積層構造を有する、
　（１）～（２６）のいずれかに記載の光検出装置。
（２８）
　前記封止層の前記複数の層は、無機層及び有機層を含む、
　（２７）に記載の光検出装置。
（２９）
　前記チップと間隔をあけて隣り合うように配置されたダミーチップを備え、
　前記埋め込み層は、前記チップ及び前記ダミーチップを覆うように設けられ、
　前記シーム部は、前記チップと前記ダミーチップとの間の部分において、前記埋め込み層の表面まで延在する、
　（１）～（２８）のいずれかに記載の光検出装置。
（３０）
　前記シーム部は、前記チップ及び前記ダミーチップの高さ方向に沿って延在する、
　（２９）に記載の光検出装置。
（３１）
　前記チップは、互いに離間して設けられた２つのチップを含み、
　前記ダミーチップは、前記２つのチップどうしの間に設けられる、
　（２９）又は（３０）に記載の光検出装置。
（３２）
　前記チップは、前記チップの表面に向かうにつれて幅が小さくなる形状を有する、
　（１）～（３１）のいずれかに記載の光検出装置。
（３３）
　前記チップの縁部は、前記チップの表面において、テーパー形状又はラウンド形状を有する、
　（３２）に記載の光検出装置。
（３４）
　前記シーム部は、前記チップの高さ方向に沿って延在する、
　（３２）又は（３３）に記載の光検出装置。
（３５）
　前記シーム部は、その延在方向に進むにつれて幅が変化する形状を有する、
　（１）～（３４）のいずれかに記載の光検出装置。
（３６）
　前記シーム部は、
　前記シーム部の延在方向において中央に位置する中央部と、
　前記シーム部の延在方向において端に位置する端部と、
　を含み、
　前記中央部は、前記端部の幅よりも大きい幅を有する、
　（３５）に記載の光検出装置。
（３７）
　平面視したときに、前記ダミーチップは、前記チップの側面に対向するように延在し、延在方向において、対向する前記チップの側面の長さの２分の１以上の長さを有する、
　（２９）～（３６）のいずれかに記載の光検出装置。
（３８）
　平面視したときに、前記ダミーチップは、前記チップを挟み込むように配置される、
　（２９）～（３７）のいずれかに記載の光検出装置。
（３９）
　前記ダミーチップは、２つ以上のダミーチップを含む、
　（２９）～（３８）のいずれかに記載の光検出装置。
（４０）
　前記ダミーチップの材料は、前記チップの材料と同じ材料を含む、
　（２９）～（３９）のいずれかに記載の光検出装置。
（４１）
　前記ダミーチップは、前記チップの高さと同じ高さを有する、
　（２９）～（４０）のいずれかに記載の光検出装置。
（４２）
　前記チップは、２つ以上のチップを含む、
　（２９）～（４１）のいずれかに記載の光検出装置。
（４３）
　平面視したときに、前記ダミーチップは、前記チップを取り囲むように連続して延在する、
　（２９）～（４２）のいずれかに記載の光検出装置。
（４４）
　前記光検出装置を側方からみたときに、前記ダミーチップは、前記埋め込み層から露出する側面を有する、
　（２９）～（４３）のいずれかに記載の光検出装置。
（４５）
　前記シーム部の少なくとも一部は、前記埋め込み層の材料とは異なる材料で埋められており、
　前記封止層は、シリコンの熱伝導率よりも高い熱伝導率を有する層である、
　（１）～（４４）のいずれかに記載の光検出装置。
（４６）
　前記埋め込み層及び前記シーム部を覆うように設けられた第１の封止層と、
　前記第１の封止層を覆うように設けられた第２の封止層と、
　を備え、
　前記第２の封止層は、シリコンの熱伝導率よりも高い熱伝導率を有する、
　（４５）に記載の光検出装置。
（４７）
　前記封止層は、金属層である、
　（４５）又は（４６）に記載の光検出装置。
（４８）
　前記封止層は、
　前記埋め込み層及び前記チップのうちの前記埋め込み層を覆う第１の部分と、
　前記埋め込み層及び前記チップのうちの前記チップを覆う第２の部分と、
　を含み、
　前記第１の部分は、絶縁性を有し、
　前記第２の部分は、シリコンの熱伝導率よりも高い熱伝導率を有する、
　（４５）～（４７）のいずれかに記載の光検出装置。
（４９）
　前記チップと前記埋め込み層との間に設けられた追加層を備え、
　前記追加層は、金属層である、
　（４５）～（４８）のいずれかに記載の光検出装置。
（５０）
　前記チップと前記封止層との間に設けられた化合物層を備え、
　前記化合物層は、シリサイド層である、
　（４５）～（４９）のいずれかに記載の光検出装置。
（５１）
　前記封止層は、絶縁体内に金属構造体が設けられた層である、
　請求項（４５）～（５０）のいずれかに記載の光検出装置。
（５２）
　前記封止層は、樹脂層である、
　（１）～（５１）のいずれかに記載の光検出装置。
（５３）
　前記埋め込み層の表面は、凹部を有し、
　前記封止層は、前記凹部を埋めるように設けられる、
　（５２）に記載の光検出装置。
（５４）
　前記封止層の表面は、平坦面である、
　（５２）又は（５３）に記載の光検出装置。
（５５）
　前記樹脂層は、酸化層又は有機層である、
　（５２）～（５４）のいずれかに記載の光検出装置。
（５６）
　前記有機層は、４００℃以上の耐熱性を有する、
　（５５）に記載の光検出装置。
（５７）
　前記有機層の材料は、ポリイミド、シロキサン及びシリコーンの少なくとも１つを含む、
　（５６）に記載の光検出装置。
（５８）
　前記チップと前記埋め込み層との間に設けられた樹脂層を備える、
　（１）～（５７）のいずれかに記載の光検出装置。
（５９）
　前記樹脂層は、酸化層又は有機層である、
　（５８）に記載の光検出装置。
（６０）
　前記有機層は、４００℃以上の耐熱性を有する、
　（５９）に記載の光検出装置。
（６１）
　前記有機層の材料は、ポリイミド、シロキサン及びシリコーンの少なくとも１つを含む、
　（６０）に記載の光検出装置。 Note that the present technology can also have the following configuration.
(1)
a substrate including a photodetector;
a chip provided on the substrate;
a buried layer provided to cover the chip;
a seam generated within the buried layer and extending to the surface of the buried layer;
a sealing layer provided to cover the embedded layer and the seam portion;
Equipped with
Photodetection device.
(2)
a support substrate located on the opposite side of the substrate across the sealing layer and directly or indirectly supporting the sealing layer;
The photodetection device according to (1).
(3)
at least a portion of the seam portion is a void;
The photodetector according to (1) or (2).
(4)
The sealing layer includes an extension portion that extends into the seam portion so as to fill at least a portion of the seam portion.
The photodetector according to any one of (1) to (3).
(5)
The material of the sealing layer includes a low permeability material.
The photodetector according to any one of (1) to (4).
(6)
The material of the sealing layer includes a low Young's modulus material.
The photodetector according to any one of (1) to (5).
(7)
comprising a side wall portion provided to cover a side surface of the chip;
The photodetector according to any one of (1) to (6).
(8)
The chip includes a first chip and a second chip that are spaced apart from each other,
The seam part includes a first seam part caused by the first chip and a second seam part caused by the second chip,
the first seam part and the second seam part are connected to each other,
The photodetector according to any one of (1) to (7).
(9)
an additional layer provided between the chip and the buried layer;
The photodetector according to any one of (1) to (8).
(10)
comprising an auxiliary layer provided to cover the sealing layer;
The photodetector according to any one of (1) to (9).
(11)
The auxiliary layer has a laminated structure,
The photodetector according to (10).
(12)
The chip includes at least one of a logic chip, a memory chip, and an AI (Artificial Intelligence) chip.
The photodetector according to any one of (1) to (11).
(13)
An imaging device configured to include a plurality of pixels,
The photodetector according to any one of (1) to (12).
(14)
a filter layer provided on the opposite side of the chip and the buried layer with the substrate in between;
a lens layer provided on the opposite side of the substrate with the filter layer in between;
Equipped with
The photodetector according to (13).
(15)
an additional substrate provided between the substrate and the buried layer;
The photodetector according to any one of (1) to (14).
(16)
The chip includes two chips arranged adjacent to each other with an interval,
The buried layer includes wiring provided between the two chips,
The photodetector according to any one of (1) to (15).
(17)
a supporting substrate that is provided on the opposite side of the substrate with the sealing layer in between and directly or indirectly supports the sealing layer;
a through via that penetrates the buried layer, the sealing layer, and the support substrate;
Equipped with
The photodetector according to any one of (1) to (16).
(18)
The chip is
a first chip;
a second chip having a thickness greater than the thickness of the first chip;
including;
The seam portion is
a first seam extending from the first chip toward the surface of the buried layer;
a second seam extending from the second chip toward the surface of the buried layer;
including;
The second seam portion extends closer to the surface of the buried layer than the first seam portion.
The photodetector according to any one of (1) to (17).
(19)
The chip is
a first chip;
including a second chip and a third chip stacked in order,
The second chip and the third chip have an overall thickness greater than the thickness of the first chip,
The seam portion is
a first seam extending from the first chip toward the surface of the buried layer;
a second seam extending from the second chip toward the surface of the buried layer;
including;
The second seam portion extends closer to the surface of the buried layer than the first seam portion.
The photodetector according to any one of (1) to (18).
(20)
The sealing layer includes an extension portion that extends into the second seam portion so as to fill at least a portion of the second seam portion.
The photodetector according to (18) or (19).
(21)
the first seam portion does not reach the surface of the buried layer;
the second seam reaches a surface of the buried layer;
The photodetector according to any one of (18) to (20).
(22)
The chips include a lower chip and an upper chip located side by side in the height direction,
The photodetecting device further includes a bonding layer provided between the lower chip and the upper chip,
The embedded layer is
a lower buried layer provided to cover a side surface of the lower chip;
an upper buried layer provided to cover the upper chip and the bonding layer;
including;
The seam portion is
a lower seam generated within the lower buried layer and extending to a surface of the lower buried layer;
an upper seam occurring within the upper buried layer and extending to a surface of the upper buried layer;
including;
The bonding layer is provided to cover the lower buried layer and the lower seam portion,
The sealing layer is provided to cover the upper buried layer and the upper seam part,
The photodetector according to any one of (1) to (21).
(23)
The chip further includes a lower chip and a dummy chip provided on opposite sides of the bonding layer,
The upper buried layer is provided to cover the upper chip, the dummy chip, and the bonding layer.
The photodetector according to (22).
(24)
The sealing layer is
a first portion covering the seam portion;
a second portion that does not cover the seam portion;
including;
The back surface of the first portion is located below the back surface of the second portion.
The photodetector according to any one of (1) to (23).
(25)
a surface of the first portion is located at the same height as a surface of the second portion;
The photodetector according to (24).
(26)
comprising an auxiliary layer provided to cover the sealing layer,
The surface of the second portion is located above the surface of the first portion,
The surface of the auxiliary layer is a flat surface.
The photodetector according to (24).
(27)
The sealing layer has a laminated structure in which a plurality of layers are laminated.
The photodetector according to any one of (1) to (26).
(28)
The plurality of layers of the sealing layer include an inorganic layer and an organic layer.
The photodetector according to (27).
(29)
a dummy chip arranged adjacent to the chip with a space therebetween;
The buried layer is provided to cover the chip and the dummy chip,
The seam portion extends to the surface of the buried layer in a portion between the chip and the dummy chip.
The photodetector according to any one of (1) to (28).
(30)
The seam portion extends along the height direction of the chip and the dummy chip.
The photodetector according to (29).
(31)
The chip includes two chips spaced apart from each other,
The dummy chip is provided between the two chips,
The photodetector according to (29) or (30).
(32)
The chip has a shape whose width decreases toward the surface of the chip,
The photodetector according to any one of (1) to (31).
(33)
The edge of the chip has a tapered shape or a round shape on the surface of the chip,
The photodetector according to (32).
(34)
The seam portion extends along the height direction of the chip.
The photodetector according to (32) or (33).
(35)
The seam portion has a shape whose width changes as it progresses in its extending direction.
The photodetection device according to any one of (1) to (34).
(36)
The seam portion is
a central portion located at the center in the extending direction of the seam portion;
an end located at the end in the extending direction of the seam part;
including;
The central portion has a width greater than the width of the end portions.
The photodetector according to (35).
(37)
When viewed in plan, the dummy chip extends so as to face the side surface of the chip, and has a length in the extending direction that is at least half the length of the side surface of the opposing chip.
The photodetector according to any one of (29) to (36).
(38)
When viewed from above, the dummy chip is arranged to sandwich the chip,
The photodetector according to any one of (29) to (37).
(39)
The dummy chip includes two or more dummy chips.
The photodetector according to any one of (29) to (38).
(40)
The material of the dummy chip includes the same material as the material of the chip,
The photodetector according to any one of (29) to (39).
(41)
the dummy chip has the same height as the chip;
The photodetector according to any one of (29) to (40).
(42)
The chip includes two or more chips.
The photodetector according to any one of (29) to (41).
(43)
When viewed in plan, the dummy chip extends continuously so as to surround the chip,
The photodetector according to any one of (29) to (42).
(44)
When the photodetection device is viewed from the side, the dummy chip has a side surface exposed from the buried layer.
The photodetector according to any one of (29) to (43).
(45)
At least a portion of the seam portion is filled with a material different from the material of the buried layer,
The sealing layer is a layer having a thermal conductivity higher than that of silicon,
The photodetector according to any one of (1) to (44).
(46)
a first sealing layer provided to cover the embedded layer and the seam portion;
a second sealing layer provided to cover the first sealing layer;
Equipped with
The second sealing layer has a thermal conductivity higher than that of silicon.
The photodetector according to (45).
(47)
the sealing layer is a metal layer,
The photodetector according to (45) or (46).
(48)
The sealing layer is
a first portion of the buried layer and the chip that covers the buried layer;
a second portion of the embedded layer and the chip that covers the chip;
including;
The first portion has insulating properties,
the second portion has a thermal conductivity higher than that of silicon;
The photodetector according to any one of (45) to (47).
(49)
an additional layer provided between the chip and the buried layer;
the additional layer is a metal layer;
The photodetector according to any one of (45) to (48).
(50)
comprising a compound layer provided between the chip and the sealing layer,
the compound layer is a silicide layer,
The photodetector according to any one of (45) to (49).
(51)
The sealing layer is a layer in which a metal structure is provided within an insulator.
The photodetection device according to any one of claims (45) to (50).
(52)
The sealing layer is a resin layer.
The photodetector according to any one of (1) to (51).
(53)
The surface of the buried layer has a recess,
The sealing layer is provided to fill the recess,
The photodetector according to (52).
(54)
The surface of the sealing layer is a flat surface.
The photodetector according to (52) or (53).
(55)
The resin layer is an oxidized layer or an organic layer,
The photodetector according to any one of (52) to (54).
(56)
The organic layer has heat resistance of 400° C. or higher,
The photodetector according to (55).
(57)
The material of the organic layer includes at least one of polyimide, siloxane, and silicone.
The photodetector according to (56).
(58)
comprising a resin layer provided between the chip and the buried layer;
The photodetector according to any one of (1) to (57).
(59)
The resin layer is an oxidized layer or an organic layer,
The photodetector according to (58).
(60)
The organic layer has heat resistance of 400° C. or higher,
The photodetector according to (59).
(61)
The material of the organic layer includes at least one of polyimide, siloxane, and silicone.
The photodetector according to (60).
　１００　光検出装置
　　　１　基板
　　１ａ　表面
　　１ｂ　裏面
　　１ｐ　光検出素子
　　　２　チップ
　　２ａ　表面
　　２ｂ　実装面
　　２ｃ　側面
　　２ｄ　側面
　　２ｅ　側面
　　２ｆ　側面
　　２ｖ　貫通ビア
　　２１　中央部
　　２２　縁部
　　２Ｄ　ダミーチップ
　　　３　埋め込み層
　　３ａ　表面
　　３ｂ　裏面
　　３ｈ　角部
　　３ｖ　貫通ビア
　３ｃ１　凹部
　３ｃ２　凸部
　　　４　シーム部
　　４１　端部
　　４２　中央部
　　４３　端部
　　４ａ　空隙
　　　５　封止層
　　５ａ　延在部
　　５１　第１の部分
　５１ａ　表面
　５１ｂ　裏面
　　５２　第２の部分
　５２ａ　表面
　５２ｂ　裏面
　　５３　無機層
　　５４　有機層
　５－２　封止層
　５－３　封止層
　５－４　封止層
　５－５　封止層
５－５ｖ　ビア
　５－６　封止層
　　　６　補助層
　　６１　層
　　６２　層
　　６３　層
　　６ａ　表面
　　　７　支持基板
　　７ａ　表面
　　７ｂ　裏面
　　　８　側壁部
　　　９　追加層
　　　Ｌ　配線
　　１０　フィルタ層
　　１１　レンズ層
　１１ａ　レンズ
　　１２　追加基板
　１２ａ　表面
　１２ｂ　裏面
　１２ｖ　貫通ビア
　　　Ｖ　貫通ビア
　　１３　接合層
　　１４　化合物層
　　１５　樹脂層
　２００　ウェハ
　　Ａｄ　添加剤
　　Ｐａ　セリア砥粒
　　ＳＬ　スクライブライン 100 Photodetector 1 Substrate 1a Front 1b Back 1p Photodetector element 2 Chip 2a Front 2b Mounting surface 2c Side 2d Side 2e Side 2f Side 2v Through via 21 Center 22 Edge 2D Dummy chip 3 Embedded layer 3a Front 3b Back 3h Corner Part 3v Through via 3c1 Concave part 3c2 Convex part 4 Seam part 41 End part 42 Central part 43 End part 4a Gap 5 Sealing layer 5a Extending part 51 First part 51a Front surface 51b Back surface 52 Second part 52a Front surface 52b Back surface 53 Inorganic layer 54 Organic layer 5-2 Sealing layer 5-3 Sealing layer 5-4 Sealing layer 5-5 Sealing layer 5-5v Via 5-6 Sealing layer 6 Auxiliary layer 61 layer 62 layer 63 layer 6a Surface 7 Support substrate 7a Front surface 7b Back surface 8 Side wall portion 9 Additional layer L Wiring 10 Filter layer 11 Lens layer 11a Lens 12 Additional substrate 12a Front surface 12b Back surface 12v Through via V Through via 13 Bonding layer 14 Compound layer 15 Resin layer 200 Wafer Ad Additive Pa Ceria Abrasive SL Scribe Line

Claims (61)

  1. 　光検出素子を含む基板と、
    　前記基板に対して設けられたチップと、
    　前記チップを覆うように設けられた埋め込み層と、
    　前記埋め込み層内に発生し、前記埋め込み層の表面まで延在しているシーム部と、
    　前記埋め込み層及び前記シーム部を覆うように設けられた封止層と、
    　を備える、
    　光検出装置。     a substrate including a photodetector;
    a chip provided on the substrate;
    a buried layer provided to cover the chip;
    a seam generated within the buried layer and extending to the surface of the buried layer;
    a sealing layer provided to cover the embedded layer and the seam portion;
    Equipped with
    Photodetection device.
  2. 　前記封止層を挟んで前記基板とは反対側に位置し、前記封止層を直接的又は間接的に支持する支持基板を備える、
    　請求項１に記載の光検出装置。     a support substrate located on the opposite side of the substrate across the sealing layer and directly or indirectly supporting the sealing layer;
    The photodetection device according to claim 1.
  3. 　前記シーム部の少なくとも一部は、空隙である、
    　請求項１に記載の光検出装置。     at least a portion of the seam portion is a void;
    The photodetection device according to claim 1.
  4. 　前記封止層は、前記シーム部の少なくとも一部を埋めるように前記シーム部内まで延在する延在部を含む、
    　請求項１に記載の光検出装置。     The sealing layer includes an extension portion that extends into the seam portion so as to fill at least a portion of the seam portion.
    The photodetection device according to claim 1.
  5. 　前記封止層の材料は、低浸透性材料を含む、
    　請求項１に記載の光検出装置。     The material of the sealing layer includes a low permeability material.
    The photodetection device according to claim 1.
  6. 　前記封止層の材料は、低ヤング率材料を含む、
    　請求項１に記載の光検出装置。     The material of the sealing layer includes a low Young's modulus material.
    The photodetection device according to claim 1.
  7. 　前記チップの側面を覆うように設けられた側壁部を備える、
    　請求項１に記載の光検出装置。     comprising a side wall portion provided to cover a side surface of the chip;
    The photodetection device according to claim 1.
  8. 　前記チップは、互いに離間して設けられた第１のチップ及び第２のチップを含み、
    　前記シーム部は、前記第１のチップに起因して発生した第１のシーム部及び前記第２のチップに起因して発生した第２のシーム部を含み、
    　前記第１のシーム部及び前記第２のシーム部は、互いにつながっている、
    　請求項１に記載の光検出装置。     The chip includes a first chip and a second chip that are spaced apart from each other,
    The seam part includes a first seam part caused by the first chip and a second seam part caused by the second chip,
    the first seam part and the second seam part are connected to each other,
    The photodetection device according to claim 1.
  9. 　前記チップと前記埋め込み層との間に設けられた追加層を備える、
    　請求項１に記載の光検出装置。     an additional layer provided between the chip and the buried layer;
    The photodetection device according to claim 1.
  10. 　前記封止層を覆うように設けられた補助層を備える、
    　請求項１に記載の光検出装置。     comprising an auxiliary layer provided to cover the sealing layer;
    The photodetection device according to claim 1.
  11. 　前記補助層は、積層構造を有する、
    　請求項１０に記載の光検出装置。     The auxiliary layer has a laminated structure,
    The photodetection device according to claim 10.
  12. 　前記チップは、ロジックチップ、メモリチップ及びＡＩ（Artificial　Intelligence）チップの少なくとも１つを含む、
    　請求項１に記載の光検出装置。     The chip includes at least one of a logic chip, a memory chip, and an AI (Artificial Intelligence) chip.
    The photodetection device according to claim 1.
  13. 　複数の画素を含むように構成された撮像装置である、
    　請求項１に記載の光検出装置。     An imaging device configured to include a plurality of pixels,
    The photodetection device according to claim 1.
  14. 　前記基板を挟んで前記チップ及び前記埋め込み層とは反対側に設けられたフィルタ層と、
    　前記フィルタ層を挟んで前記基板とは反対側に設けられたレンズ層と、
    　を備える、
    　請求項１３に記載の光検出装置。     a filter layer provided on the opposite side of the chip and the buried layer with the substrate in between;
    a lens layer provided on the opposite side of the substrate with the filter layer in between;
    Equipped with
    The photodetection device according to claim 13.
  15. 　前記基板と前記埋め込み層との間に設けられた追加基板を備える、
    　請求項１に記載の光検出装置。     an additional substrate provided between the substrate and the buried layer;
    The photodetection device according to claim 1.
  16. 　前記チップは、間隔をあけて隣り合うように配置された２つのチップを含み、
    　前記埋め込み層は、前記２つのチップどうしの間に設けられた配線を含む、
    　請求項１に記載の光検出装置。     The chip includes two chips arranged adjacent to each other with an interval,
    The buried layer includes wiring provided between the two chips,
    The photodetection device according to claim 1.
  17. 　前記封止層を挟んで前記基板とは反対側に設けられ、前記封止層を直接的又は間接的に支持する支持基板と、
    　前記埋め込み層、前記封止層及び前記支持基板を貫通する貫通ビアと、
    　を備える、
    　請求項１に記載の光検出装置。     a supporting substrate that is provided on the opposite side of the substrate with the sealing layer in between and supports the sealing layer directly or indirectly;
    a through via that penetrates the buried layer, the sealing layer, and the support substrate;
    Equipped with
    The photodetection device according to claim 1.
  18. 　前記チップは、
    　第1のチップと、
    　前記第１のチップの厚さよりも大きい厚さを有する第２のチップと、
    　を含み、
    　前記シーム部は、
    　前記第１のチップから前記埋め込み層の表面に向かって延在する第１のシーム部と、
    　前記第２のチップから前記埋め込み層の表面に向かって延在する第２のシーム部と、
    　を含み、
    　前記第２のシーム部は、前記第１のシーム部よりも、前記埋め込み層の表面の近くまで延在している、
    　請求項１に記載の光検出装置。     The chip is
    a first chip;
    a second chip having a thickness greater than the thickness of the first chip;
    including;
    The seam portion is
    a first seam extending from the first chip toward the surface of the buried layer;
    a second seam extending from the second chip toward the surface of the buried layer;
    including;
    The second seam portion extends closer to the surface of the buried layer than the first seam portion.
    The photodetection device according to claim 1.
  19. 　前記チップは、
    　第１のチップと、
    　順に積層された第２のチップ及び第３のチップを含み、
    　前記第２のチップ及び前記第３のチップは、全体として、前記第１のチップの厚さよりも大きい厚さを有し、
    　前記シーム部は、
    　前記第１のチップから前記埋め込み層の表面に向かって延在する第１のシーム部と、
    　前記第２のチップから前記埋め込み層の表面に向かって延在する第２のシーム部と、
    　を含み、
    　前記第２のシーム部は、前記第１のシーム部よりも、前記埋め込み層の表面の近くまで延在している、
    　請求項１に記載の光検出装置。     The chip is
    a first chip;
    including a second chip and a third chip stacked in order,
    The second chip and the third chip have an overall thickness greater than the thickness of the first chip,
    The seam portion is
    a first seam extending from the first chip toward the surface of the buried layer;
    a second seam extending from the second chip toward the surface of the buried layer;
    including;
    The second seam portion extends closer to the surface of the buried layer than the first seam portion.
    The photodetection device according to claim 1.
  20. 　前記封止層は、前記第２のシーム部の少なくとも一部を埋めるように前記第２のシーム部内まで延在する延在部を含む、
    　請求項１８に記載の光検出装置。     The sealing layer includes an extension portion that extends into the second seam portion so as to fill at least a portion of the second seam portion.
    The photodetection device according to claim 18.
  21. 　前記第１のシーム部は、前記埋め込み層の表面に到達しておらず、
    　前記第２のシーム部は、前記埋め込み層の表面に到達している、
    　請求項１８に記載の光検出装置。     the first seam portion does not reach the surface of the buried layer;
    the second seam reaches a surface of the buried layer;
    The photodetection device according to claim 18.
  22. 　前記チップは、高さ方向に並んで位置する下方チップ及び上方チップを含み、
    　前記光検出装置は、前記下方チップと前記上方チップとの間に設けられた接合層をさらに備え、
    　前記埋め込み層は、
    　前記下方チップの側面を覆うように設けられた下方埋め込み層と、
    　前記上方チップ及び前記接合層を覆うように設けられた上方埋め込み層と、
    　を含み、
    　前記シーム部は、
    　前記下方埋め込み層内に発生し、前記下方埋め込み層の表面まで延在する下方シーム部と、
    　前記上方埋め込み層内に発生し、前記上方埋め込み層の表面まで延在する上方シーム部と、
    　を含み、
    　前記接合層は、前記下方埋め込み層及び前記下方シーム部を覆うように設けられ、
    　前記封止層は、前記上方埋め込み層及び前記上方シーム部を覆うように設けられる、
    　請求項１に記載の光検出装置。     The chips include a lower chip and an upper chip located side by side in the height direction,
    The photodetecting device further includes a bonding layer provided between the lower chip and the upper chip,
    The buried layer is
    a lower buried layer provided to cover a side surface of the lower chip;
    an upper buried layer provided to cover the upper chip and the bonding layer;
    including;
    The seam portion is
    a lower seam generated within the lower buried layer and extending to a surface of the lower buried layer;
    an upper seam occurring within the upper buried layer and extending to a surface of the upper buried layer;
    including;
    The bonding layer is provided to cover the lower buried layer and the lower seam portion,
    The sealing layer is provided to cover the upper buried layer and the upper seam part,
    The photodetection device according to claim 1.
  23. 　前記チップは、前記接合層を挟んで互いに反対側に設けられた下方チップ及びダミーチップをさらに含み、
    　前記上方埋め込み層は、前記上方チップ、前記ダミーチップ及び前記接合層を覆うように設けられる、
    　請求項２２に記載の光検出装置。     The chip further includes a lower chip and a dummy chip provided on opposite sides of the bonding layer,
    The upper buried layer is provided to cover the upper chip, the dummy chip, and the bonding layer.
    The photodetection device according to claim 22.
  24. 　前記封止層は、
    　前記シーム部を覆う第１の部分と、
    　前記シーム部を覆わない第２の部分と、
    　を含み、
    　前記第１の部分の裏面は、前記第２の部分の裏面よりも下方に位置している、
    　請求項１に記載の光検出装置。     The sealing layer is
    a first portion covering the seam portion;
    a second portion that does not cover the seam portion;
    including;
    The back surface of the first portion is located below the back surface of the second portion.
    The photodetection device according to claim 1.
  25. 　前記第１の部分の表面は、前記第２の部分の表面と同じ高さに位置している、
    　請求項２４に記載の光検出装置。     a surface of the first portion is located at the same height as a surface of the second portion;
    The photodetection device according to claim 24.
  26. 　前記封止層を覆うように設けられた補助層を備え、
    　前記第２の部分の表面は、前記第１の部分の表面よりも上方に位置しており、
    　前記補助層の表面は、平坦面である、
    　請求項２４に記載の光検出装置。     comprising an auxiliary layer provided to cover the sealing layer,
    The surface of the second portion is located above the surface of the first portion,
    The surface of the auxiliary layer is a flat surface.
    The photodetection device according to claim 24.
  27. 　前記封止層は、複数の層が積層された積層構造を有する、
    　請求項１に記載の光検出装置。     The sealing layer has a laminated structure in which a plurality of layers are laminated.
    The photodetection device according to claim 1.
  28. 　前記封止層の前記複数の層は、無機層及び有機層を含む、
    　請求項２７に記載の光検出装置。     The plurality of layers of the sealing layer include an inorganic layer and an organic layer.
    The photodetection device according to claim 27.
  29. 　前記チップと間隔をあけて隣り合うように配置されたダミーチップを備え、
    　前記埋め込み層は、前記チップ及び前記ダミーチップを覆うように設けられ、
    　前記シーム部は、前記チップと前記ダミーチップとの間の部分において、前記埋め込み層の表面まで延在する、
    　請求項１に記載の光検出装置。     a dummy chip arranged adjacent to the chip with a space therebetween;
    The buried layer is provided to cover the chip and the dummy chip,
    The seam portion extends to the surface of the buried layer in a portion between the chip and the dummy chip.
    The photodetection device according to claim 1.
  30. 　前記シーム部は、前記チップ及び前記ダミーチップの高さ方向に沿って延在する、
    　請求項２９に記載の光検出装置。     The seam portion extends along the height direction of the chip and the dummy chip.
    The photodetection device according to claim 29.
  31. 　前記チップは、互いに離間して設けられた２つのチップを含み、
    　前記ダミーチップは、前記２つのチップどうしの間に設けられる、
    　請求項２９に記載の光検出装置。     The chip includes two chips spaced apart from each other,
    The dummy chip is provided between the two chips,
    The photodetection device according to claim 29.
  32. 　前記チップは、前記チップの表面に向かうにつれて幅が小さくなる形状を有する、
    　請求項１に記載の光検出装置。     The chip has a shape whose width decreases toward the surface of the chip,
    The photodetection device according to claim 1.
  33. 　前記チップの縁部は、前記チップの表面において、テーパー形状又はラウンド形状を有する、
    　請求項３２に記載の光検出装置。     The edge of the chip has a tapered shape or a round shape on the surface of the chip,
    The photodetection device according to claim 32.
  34. 　前記シーム部は、前記チップの高さ方向に沿って延在する、
    　請求項３２に記載の光検出装置。     The seam portion extends along the height direction of the chip.
    The photodetection device according to claim 32.
  35. 　前記シーム部は、その延在方向に進むにつれて幅が変化する形状を有する、
    　請求項１に記載の光検出装置。     The seam portion has a shape whose width changes as it progresses in its extending direction.
    The photodetection device according to claim 1.
  36. 　前記シーム部は、
    　前記シーム部の延在方向において中央に位置する中央部と、
    　前記シーム部の延在方向において端に位置する端部と、
    　を含み、
    　前記中央部は、前記端部の幅よりも大きい幅を有する、
    　請求項３５に記載の光検出装置。     The seam portion is
    a central portion located at the center in the extending direction of the seam portion;
    an end located at the end in the extending direction of the seam part;
    including;
    The central portion has a width greater than the width of the end portions.
    The photodetection device according to claim 35.
  37. 　平面視したときに、前記ダミーチップは、前記チップの側面に対向するように延在し、延在方向において、対向する前記チップの側面の長さの２分の１以上の長さを有する、
    　請求項２９に記載の光検出装置。     When viewed in plan, the dummy chip extends to face the side surface of the chip, and has a length in the extending direction that is at least half the length of the side surface of the opposing chip.
    The photodetection device according to claim 29.
  38. 　平面視したときに、前記ダミーチップは、前記チップを挟み込むように配置される、
    　請求項２９に記載の光検出装置。     When viewed from above, the dummy chip is arranged to sandwich the chip,
    The photodetection device according to claim 29.
  39. 　前記ダミーチップは、２つ以上のダミーチップを含む、
    　請求項２９に記載の光検出装置。     The dummy chip includes two or more dummy chips.
    The photodetection device according to claim 29.
  40. 　前記ダミーチップの材料は、前記チップの材料と同じ材料を含む、
    　請求項２９に記載の光検出装置。     The material of the dummy chip includes the same material as the material of the chip,
    The photodetection device according to claim 29.
  41. 　前記ダミーチップは、前記チップの高さと同じ高さを有する、
    　請求項２９に記載の光検出装置。     the dummy chip has the same height as the chip;
    The photodetection device according to claim 29.
  42. 　前記チップは、２つ以上のチップを含む、
    　請求項２９に記載の光検出装置。     The chip includes two or more chips.
    The photodetection device according to claim 29.
  43. 　平面視したときに、前記ダミーチップは、前記チップを取り囲むように連続して延在する、
    　請求項２９に記載の光検出装置。     When viewed in plan, the dummy chip extends continuously so as to surround the chip,
    The photodetection device according to claim 29.
  44. 　前記光検出装置を側方からみたときに、前記ダミーチップは、前記埋め込み層から露出する側面を有する、
    　請求項２９に記載の光検出装置。     When the photodetection device is viewed from the side, the dummy chip has a side surface exposed from the buried layer.
    The photodetection device according to claim 29.
  45. 　前記シーム部の少なくとも一部は、前記埋め込み層の材料とは異なる材料で埋められており、
    　前記封止層は、シリコンの熱伝導率よりも高い熱伝導率を有する層である、
    　請求項１に記載の光検出装置。     At least a portion of the seam portion is filled with a material different from the material of the buried layer,
    The sealing layer is a layer having a thermal conductivity higher than that of silicon,
    The photodetection device according to claim 1.
  46. 　前記埋め込み層及び前記シーム部を覆うように設けられた第１の封止層と、
    　前記第１の封止層を覆うように設けられた第２の封止層と、
    　を備え、
    　前記第２の封止層は、シリコンの熱伝導率よりも高い熱伝導率を有する、
    　請求項４５に記載の光検出装置。     a first sealing layer provided to cover the embedded layer and the seam portion;
    a second sealing layer provided to cover the first sealing layer;
    Equipped with
    The second sealing layer has a thermal conductivity higher than that of silicon.
    The photodetection device according to claim 45.
  47. 　前記封止層は、金属層である、
    　請求項４５に記載の光検出装置。     the sealing layer is a metal layer,
    The photodetection device according to claim 45.
  48. 　前記封止層は、
    　前記埋め込み層及び前記チップのうちの前記埋め込み層を覆う第１の部分と、
    　前記埋め込み層及び前記チップのうちの前記チップを覆う第２の部分と、
    　を含み、
    　前記第１の部分は、絶縁性を有し、
    　前記第２の部分は、シリコンの熱伝導率よりも高い熱伝導率を有する、
    　請求項４５に記載の光検出装置。     The sealing layer is
    a first portion of the buried layer and the chip that covers the buried layer;
    a second portion of the embedded layer and the chip that covers the chip;
    including;
    The first portion has insulating properties,
    the second portion has a thermal conductivity higher than that of silicon;
    The photodetection device according to claim 45.
  49. 　前記チップと前記埋め込み層との間に設けられた追加層を備え、
    　前記追加層は、金属層である、
    　請求項４５に記載の光検出装置。     an additional layer provided between the chip and the buried layer;
    the additional layer is a metal layer;
    The photodetection device according to claim 45.
  50. 　前記チップと前記封止層との間に設けられた化合物層を備え、
    　前記化合物層は、シリサイド層である、
    　請求項４５に記載の光検出装置。     comprising a compound layer provided between the chip and the sealing layer,
    the compound layer is a silicide layer,
    The photodetection device according to claim 45.
  51. 　前記封止層は、絶縁体内に金属構造体が設けられた層である、
    　請求項４５に記載の光検出装置。     The sealing layer is a layer in which a metal structure is provided within an insulator.
    The photodetection device according to claim 45.
  52. 　前記封止層は、樹脂層である、
    　請求項１に記載の光検出装置。     The sealing layer is a resin layer.
    The photodetection device according to claim 1.
  53. 　前記埋め込み層の表面は、凹部を有し、
    　前記封止層は、前記凹部を埋めるように設けられる、
    　請求項５２に記載の光検出装置。     The surface of the buried layer has a recess,
    The sealing layer is provided to fill the recess,
    The photodetection device according to claim 52.
  54. 　前記封止層の表面は、平坦面である、
    　請求項５２に記載の光検出装置。     The surface of the sealing layer is a flat surface.
    The photodetection device according to claim 52.
  55. 　前記樹脂層は、酸化層又は有機層である、
    　請求項５２に記載の光検出装置。     The resin layer is an oxidized layer or an organic layer,
    The photodetection device according to claim 52.
  56. 　前記有機層は、４００℃以上の耐熱性を有する、
    　請求項５５に記載の光検出装置。     The organic layer has heat resistance of 400° C. or higher,
    The photodetection device according to claim 55.
  57. 　前記有機層の材料は、ポリイミド、シロキサン及びシリコーンの少なくとも１つを含む、
    　請求項５６に記載の光検出装置。     The material of the organic layer includes at least one of polyimide, siloxane, and silicone.
    The photodetection device according to claim 56.
  58. 　前記チップと前記埋め込み層との間に設けられた樹脂層を備える、
    　請求項１に記載の光検出装置。     comprising a resin layer provided between the chip and the buried layer;
    The photodetection device according to claim 1.
  59. 　前記樹脂層は、酸化層又は有機層である、
    　請求項５８に記載の光検出装置。     The resin layer is an oxidized layer or an organic layer,
    The photodetection device according to claim 58.
  60. 　前記有機層は、４００℃以上の耐熱性を有する、
    　請求項５９に記載の光検出装置。     The organic layer has heat resistance of 400° C. or higher,
    The photodetection device according to claim 59.
  61. 　前記有機層の材料は、ポリイミド、シロキサン及びシリコーンの少なくとも１つを含む、
    　請求項６０に記載の光検出装置。     The material of the organic layer includes at least one of polyimide, siloxane, and silicone.
    The photodetection device according to claim 60.
PCT/JP2023/032601 2022-09-08 2023-09-07 Light detection device WO2024053695A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221179A (en) * 1994-02-05 1995-08-18 Nec Corp Manufacturing method of semiconductor device
JPH088341A (en) * 1994-06-21 1996-01-12 Nippon Steel Corp Fabrication of semiconductor device
WO2017183390A1 (en) * 2016-04-20 2017-10-26 ソニー株式会社 Laminate structure and method for manufacturing same
WO2020079945A1 (en) * 2018-10-15 2020-04-23 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device and electronic apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221179A (en) * 1994-02-05 1995-08-18 Nec Corp Manufacturing method of semiconductor device
JPH088341A (en) * 1994-06-21 1996-01-12 Nippon Steel Corp Fabrication of semiconductor device
WO2017183390A1 (en) * 2016-04-20 2017-10-26 ソニー株式会社 Laminate structure and method for manufacturing same
WO2020079945A1 (en) * 2018-10-15 2020-04-23 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device and electronic apparatus

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