WO2022196188A1 - Imaging device, method for manufacturing imaging device, and electronic device - Google Patents
Imaging device, method for manufacturing imaging device, and electronic device Download PDFInfo
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- WO2022196188A1 WO2022196188A1 PCT/JP2022/004899 JP2022004899W WO2022196188A1 WO 2022196188 A1 WO2022196188 A1 WO 2022196188A1 JP 2022004899 W JP2022004899 W JP 2022004899W WO 2022196188 A1 WO2022196188 A1 WO 2022196188A1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
Definitions
- the present disclosure relates to an imaging device having an imaging element, a manufacturing method thereof, and an electronic device provided with the imaging device.
- an imaging device having a structure suitable for thinning while having good imaging performance, a manufacturing method thereof, and an electronic device equipped with such an imaging device.
- An imaging device includes a first substrate, a second substrate, a chip, and an intermediate member.
- the first substrate has an imaging element that includes a plurality of pixels and can generate a pixel signal for each pixel.
- the second substrate is arranged to face the first substrate in the first direction.
- the chip is provided between the first substrate and the second substrate and has a circuit for performing signal processing of pixel signals.
- the intermediate member is located in a gap between the first substrate and the second substrate, and is provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
- the intermediate member is provided in the gap between the first substrate and the second substrate so as to be adjacent to the chip in the in-plane direction orthogonal to the first direction. Therefore, for example, the thickness of the protective layer provided in the gap between the first substrate and the second substrate so as to cover the chip may be thin.
- FIG. 1 is a cross-sectional view showing an overall configuration example of a solid-state imaging device according to a first embodiment of the present disclosure
- FIG. 1B is a plan view showing the configuration of the solid-state imaging device shown in FIG. 1A
- FIG. 1B is a schematic diagram illustrating one step of a method for manufacturing the solid-state imaging device shown in FIG. 1A
- FIG. 2A It is a schematic diagram explaining 1 process following FIG. 2B.
- FIG. 2C It is a schematic diagram explaining 1 process following FIG. 2D.
- FIG. 2E It is a schematic diagram explaining one process following FIG. 2F.
- FIG. 2A is a schematic diagram explaining 1 process following FIG. 2A
- FIG. 2C It is a schematic diagram explaining 1 process following FIG. 2C.
- FIG. 2D It is a schematic diagram explaining 1 process following FIG. 2E.
- FIG. 2F FIG.
- FIG. 10 is a cross-sectional view showing an example of the overall configuration of a solid-state imaging device according to Modification 1 of the present disclosure
- 4A and 4B are schematic diagrams for explaining a step of a method for manufacturing the solid-state imaging device shown in FIG. 3
- FIG. 4B is a schematic diagram illustrating a step following FIG. 4A
- FIG. 4B It is a schematic diagram explaining 1 process following FIG. 4B.
- FIG. 4C It is a schematic diagram explaining 1 process following FIG. 4C.
- FIG. 4D It is a schematic diagram explaining one process following FIG. 4E.
- FIG. 4A and 4B are schematic diagrams for explaining a step of a method for manufacturing the solid-state imaging device shown in FIG. 3
- FIG. 4B is a schematic diagram illustrating a step following FIG. 4A
- FIG. 4D It is a schematic diagram explaining 1
- FIG. 7 is a cross-sectional view showing an example of the overall configuration of a solid-state imaging device according to a second embodiment of the present disclosure
- 6A and 6B are schematic diagrams for explaining a step of a method for manufacturing the solid-state imaging device shown in FIG. 5
- FIG. 6B is a schematic diagram illustrating a step following FIG. 6A
- FIG. 6B is a schematic diagram illustrating a step following FIG. 6B
- FIG. 6G is a schematic diagram illustrating a step following FIG. 6G.
- FIG. 6H is a schematic diagram illustrating a step following FIG. 6H;
- FIG. 11 is a schematic diagram showing an example of the overall configuration of an electronic device according to a third embodiment of the present disclosure
- 1 is a block diagram showing an example of a schematic configuration of a vehicle control system;
- FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
- FIG. 11 is a cross-sectional view showing an example of the overall configuration of a solid-state imaging device according to a second modified example of the present disclosure;
- FIG. 11 is a cross-sectional view showing an example of the overall configuration of a solid-state imaging device according to a third modified example of the present disclosure;
- FIG. 21 is a cross-sectional view showing an example of the overall configuration of a solid-state imaging device according to Modification 4 of the present disclosure;
- FIGS. 1A and 1B show a cross-sectional configuration of the solid-state imaging device 1
- FIG. 1B shows a planar configuration of the solid-state imaging device 1.
- FIG. FIG. 1A corresponds to a cross-sectional view taken along the IA-IA line shown in FIG. 1B.
- the solid-state imaging device 1 includes, for example, a circuit board 10, a sensor board 20, a chip 30, and a protective layer 40.
- the circuit board 10 and the sensor board 20 each extend, for example, in the XY plane direction.
- the circuit board 10 and the sensor board 20 are arranged so as to face each other in the Z-axis direction.
- the lamination direction of the circuit board 10 and the sensor board 20 is the Z-axis direction
- the plane on which the circuit board 10 and the sensor board 20 spread is the XY plane.
- reference character K1 represents the outer edge of the solid-state imaging device 1.
- the outer edge K1 of the solid-state imaging device 1 coincides with, for example, the outermost edge of the circuit board 10 and the outermost edge of the sensor substrate 20 .
- the circuit board 10 and the sensor board 20 are bonded via a protective layer 40, for example.
- the sensor substrate 20 has a layered structure of an element forming substrate 21 and a wiring layer 22 .
- the wiring layer 22 is provided on the side facing the circuit board 10 when viewed from the element forming substrate 21 .
- the wiring layer 22 has a facing surface 22S that faces the circuit board 10 .
- a terminal portion 23 is embedded in the wiring layer 22 . However, the surface 23S of the terminal portion 23 is exposed to the facing surface 22S.
- the wiring layer 22 is made of an insulating material such as an insulating resin, a metal oxide, a metal nitride, or an inorganic oxide.
- the wiring layer 22 may be made of organic insulating materials such as polyimide, silicone, epoxy, and acrylic, and inorganic insulating materials such as AlOx, AlNx, SiOx, SiNx, SiON, SiCN, and SiOC.
- the terminal portion 23 is preferably made of a highly conductive material such as Cu (copper).
- the element formation substrate 21 is a substrate made of a semiconductor material such as silicon (Si).
- a solid-state imaging device 24 is provided on the device forming substrate 21 .
- an area extending in the XY plane where the solid-state imaging device 24 is provided on the sensor substrate 20 is called an effective pixel area R24 (see FIG. 1B).
- the effective pixel area R24 is, for example, an area inside the light-shielding area (OPB), that is, an area capable of receiving external light.
- the solid-state imaging device 24 is formed by arranging a plurality of pixels PX each including a photoelectric conversion unit 25 such as a photodiode, a color filter 26, and an on-chip lens 27 along the XY plane.
- the solid-state imaging device 24 can receive external light for each pixel PX and generate a pixel signal for each pixel PX.
- the terminal portion 23 is electrically connected to the terminal portion 33 of the chip 30 .
- the electrical connection between the terminal portion 23 and the terminal portion 33 establishes electrical connection between, for example, the solid-state imaging device 24 and a signal processing circuit provided in the chip 30 .
- the circuit board 10 has, for example, a support 11 and an insulating film 12 .
- the support 11 includes, for example, a support substrate 111 extending in the XY plane, and an intermediate member 112 provided on the upper surface 111S of the support substrate 111 .
- the intermediate member 112 is located in the gap between the support substrate 111 and the element forming substrate 21 and is provided so as to be adjacent to the chip 30 in the XY plane direction.
- the intermediate member 112 may have a second thermal conductivity higher than the first thermal conductivity of the protective layer 40 .
- the support substrate 111 and the intermediate member 112 are integrated.
- the constituent material of the support substrate 111 and the constituent material of the intermediate member 112 may be substantially the same.
- the constituent material of the support substrate 111 and the constituent material of the intermediate member 112 are both silicon (Si), for example.
- the insulating film 12 is provided so as to uniformly cover the support 11 .
- the insulating film 12 is made of an inorganic oxide such as silicon oxide (SiOx) or silicon nitride (SiNx).
- the insulating film 12 has a facing surface 12S facing the sensor substrate 20 .
- One or more recesses 10U are formed in the circuit board 10 on the side facing the sensor board 20 .
- FIG. 1B illustrates a configuration in which four recesses 10U are provided at positions corresponding to the effective pixel region R24 of the sensor substrate 20 in the Z-axis direction, but the present disclosure is not limited to this. do not have. That is, only one concave portion 10U may be provided, or two, three, or five or more concave portions 10U may be provided.
- the chip 30 is provided between the sensor board 20 and the support board 111 of the circuit board 10 .
- the chip 30 has, for example, a substrate 31 , a circuit forming layer 32 provided on the substrate 31 , and terminal portions 33 provided on the circuit forming layer 32 .
- the substrate 31 is a substrate made of a semiconductor material such as silicon (Si).
- the circuit formation layer 32 is provided with a signal processing circuit including, for example, semiconductor elements such as transistors and wiring.
- the signal processing circuit provided in the circuit forming layer 32 performs signal processing of pixel signals from the solid-state imaging device 24, for example.
- the circuit forming layer 32 has a facing surface 32S that faces the sensor substrate 20 . In the configuration example shown in FIG.
- the facing surface 32S protrudes from the facing surface 12S by the thickness of the protective layer 40, for example. Therefore, the distance between the facing surface 32S of the chip 30 and the element forming substrate 21 is narrower than the distance between the intermediate member 112 and the element forming substrate 21 in the Z-axis direction.
- the protection layer 40 may be extremely thin in the Z-axis direction, and the distance between the chip 30 and the element forming substrate 21 may be substantially equal to the distance between the intermediate member 112 and the element forming substrate 21 .
- the terminal portion 33 is embedded in the circuit forming layer 32 . However, the surface 33S of the terminal portion 33 is exposed to the facing surface 32S.
- the circuit forming layer 32 is made of an insulating material such as an insulating resin, metal oxide, metal nitride, or inorganic oxide.
- the constituent materials of the circuit forming layer 32 include organic insulating materials such as polyimide, silicone, epoxy, and acrylic, and inorganic insulating materials such as AlOx, AlNx, SiOx, SiNx, SiON, SiCN, and SiOC.
- the terminal portion 33 is preferably made of a highly conductive material such as Cu (copper).
- the chip 30 is housed in a recess 10U formed in the circuit board 10, for example.
- the intermediate member 112 of the circuit board 10 is in contact with the end surface 30T of the chip 30 via the insulating film 12 in the XY plane direction.
- the protective layer 40 is a member that joins the circuit board 10 and the sensor board 20 as described above.
- the protective layer 40 fills the gap between the circuit board 10 and the sensor board 20 so as to cover the chip 30 .
- constituent materials of the protective layer 40 include organic materials such as polyimide, silicone, epoxy, and acrylic, and inorganic materials such as SiOx, SiNx, SiON, SiCN, and SiOC.
- FIGS. 2A to 2G are cross-sectional views respectively showing one step of the manufacturing method of the solid-state imaging device 1, corresponding to FIG. 1A.
- a resist mask RM is formed on the upper surface of the semiconductor substrate 11Z.
- the resist mask RM is formed with an opening K in a region corresponding to the region where the recess 10U for accommodating the chip 30 is to be formed.
- recesses 10U are formed. Specifically, the portion of the semiconductor substrate 11Z that is not covered with the resist mask RM, that is, the portion corresponding to the opening K is dug down by dry etching, for example. As a result, the support 11 in which the support substrate 111 and the intermediate member 112 are integrated is completed.
- an insulating film 12 is formed to cover the entire support 11 as shown in FIG. 2C.
- the insulating film 12 can be formed by, for example, a sputtering method or a CVD method. At that time, the insulating film 12 is conformally formed so as to maintain the shape of the concave portion 10U as much as possible.
- the chip 30 is placed in the recess 10U.
- a resin adhesive may be applied to the back surface of the substrate 31 of the chip 30 to adhere and fix the chip 30 to the concave portion 10U.
- the upper surface 30S of the chip 30 protrudes above the opposing surface 12S of the insulating film 12, that is, in a direction away from the support substrate 111. It's becoming
- a protective film 40Z is formed to cover the entire circuit board 10 and the chip 30 placed in the recess 10U.
- the protective film 40Z can be formed by, for example, a coating method.
- the protective film 40Z is polished and planarized by chemical mechanical polishing (CMP), for example, to obtain the protective layer 40 as shown in FIG. 2F.
- CMP chemical mechanical polishing
- a structure 20Z is prepared.
- the structural body 20Z is obtained by laminating a wiring layer 22 on an element forming substrate 21 including a photoelectric conversion portion 25 .
- a terminal portion 23 is provided on the wiring layer 22 .
- a surface 23S of the terminal portion 23 is exposed to the facing surface 22S.
- the position of the structural body 20Z and the circuit board 10 in the XY plane is determined. Align. After that, the structure 20Z and the circuit board 10 are bonded together.
- the surface 33S of the terminal portion 33 of the chip 30 and the surface 23S of the terminal portion 23 of the sensor substrate 20 are bonded by Cu--Cu, for example. Thereby, the contact plug CP in which the terminal portion 33 and the terminal portion 23 are integrated is obtained.
- the element forming substrate 21 of the structure 20Z is thinned.
- a plurality of color filters 26 and a plurality of on-chip lenses 27 are laminated on the thinned device forming substrate 21 to form the solid-state imaging device 24 . This obtains the sensor substrate 20 (see FIG. 1A).
- the solid-state imaging device 1 is completed through the above steps.
- the intermediate member 112 is provided in the gap between the element forming substrate 21 and the support substrate 111 so as to be adjacent to the chip 30 in the XY plane direction orthogonal to the Z-axis direction. . Therefore, the protective layer 40 provided to cover the chip 30 in the gap between the element forming substrate 21 and the support substrate 111, for example, can be thin. By reducing the thickness of the protective layer 40, the stress applied to the chip 30 due to bonding of the sensor substrate 20 and the circuit substrate 10, for example, is alleviated. The stress applied to the chip 30 is due, for example, to the distortion of the protective layer 40 and its peripheral portion.
- the flatness of the protective layer 40 in the XY plane is improved. That is, for example, the inclination of the element formation substrate 21 with respect to the support substrate 111 can be sufficiently reduced. As a result, variations in the distance between the support substrate 111 and the element forming substrate 21 can be reduced, and the operational reliability of the solid-state imaging device 1 can be improved.
- the chip 30 is arranged so as to be embedded in the concave portion 10U. Therefore, the thickness of the support substrate 111 can be reduced. This is because even if the support substrate 111 is made thin, the mechanical strength of the circuit board 10 as a whole can be maintained because the intermediate member 112 is provided. By reducing the thickness of the support substrate 111, the overall thickness of the solid-state imaging device 1 can be reduced. Further, even if the entire solid-state imaging device 1 is made thinner, the thickness of the chip 30 can be maintained because the chip 30 is embedded in the concave portion 10U in the solid-state imaging device 1 . Therefore, the withstand voltage and mechanical strength required for the substrate 31 can be sufficiently secured. Therefore, long-term reliability of the solid-state imaging device 1 can be improved.
- the intermediate member 112 is arranged so as to be adjacent to the chip 30 in the XY plane direction.
- the intermediate member 112 has a second thermal conductivity higher than the first thermal conductivity of the protective layer 40 . Therefore, heat generated in the chip 30 can be efficiently released to the outside, for example, compared to the case where the protective layer 40 covers most of the chip 30 without the intermediate member 112 present. In this respect as well, the operational reliability of the solid-state imaging device 1 can be improved.
- FIG. 3 is a cross-sectional view showing an overall configuration example of a solid-state imaging device 1A according to a first modification (hereinafter referred to as modification 1) of the first embodiment.
- FIGS. 4A to 4F are cross-sectional views respectively showing one step of the manufacturing method of the solid-state imaging device 1A, corresponding to FIG. 1A.
- FIGS. 2A to 2C are sequentially performed in the same manner as in the manufacturing method of the solid-state imaging device 1 of the first embodiment.
- the chip 30 is placed in the recess 10U.
- a resin adhesive may be applied to the back surface of the substrate 31 of the chip 30 to adhere and fix the chip 30 to the concave portion 10U.
- the chip 30 is substantially the same as the chip 30 of the first embodiment.
- modification 1-1 as shown in FIG. 4A, when the chip 30 is placed in the recess 10U, the upper surface 30S of the chip 30 is positioned below the facing surface 12S of the insulating film 12, that is, on the support substrate 111. It is in a recessed state in the approaching direction.
- a protective film 40Z is formed to cover the entire circuit board 10 and the chip 30 placed in the recess 10U.
- the protective film 40Z can be formed by, for example, a coating method.
- the protective film 40Z is polished and planarized by chemical mechanical polishing (CMP), for example, to obtain the protective layer 40 as shown in FIG. 4C.
- CMP chemical mechanical polishing
- the surface 33S of the terminal portion 33 of the chip 30 is covered with the protective layer 40.
- the facing surface 12S of the insulating film 12 may be covered with the protective layer 40 without being exposed.
- a resist mask RM2 that selectively covers the protective layer 40 is formed by photolithography, for example.
- the resist mask RM2 has openings K2 at positions corresponding to the terminal portions 33 .
- dry etching for example, is performed using a resist mask RM2.
- the protective layer 40 exposed in the opening K2 is selectively etched.
- An opening K40 is formed in the protective layer 40 by etching using the resist mask RM2, and the terminal portion 33 is exposed.
- a metal film 34 is formed on the terminal portion 33 by, for example, plating.
- the metal film 34 is made of the same material as the terminal portion 33, such as Cu.
- a planarization process may be performed.
- the terminal portion 35 composed of the terminal portion 33 and the metal film 34 is obtained.
- the chip 30A including the substrate 31, the circuit forming layer 32, and the terminal portion 35 is completed.
- the terminal portion 35 includes a surface 35S.
- Surface 40S of protective layer 40 forms a common plane with surface 35S.
- a structure 20Z is prepared.
- the structural body 20Z is obtained by laminating a wiring layer 22 on an element forming substrate 21 including a photoelectric conversion portion 25 .
- a terminal portion 23 is provided on the wiring layer 22 .
- a surface 23S of the terminal portion 23 is exposed to the facing surface 22S.
- the position of the structural body 20Z and the circuit board 10 in the XY plane is determined. Align. After that, the structure 20Z and the circuit board 10 are bonded together.
- the surface 35S of the terminal portion 35 of the chip 30A and the surface 23S of the terminal portion 23 of the sensor substrate 20 are bonded by Cu--Cu, for example. Thereby, the contact plug CP2 in which the terminal portion 35 and the terminal portion 23 are integrated is obtained.
- the element forming substrate 21 of the structure 20Z is thinned.
- a plurality of color filters 26 and a plurality of on-chip lenses 27 are laminated on the thinned device forming substrate 21 to form the solid-state imaging device 24 .
- the sensor substrate 20 is obtained (see FIG. 3).
- (Effect) Modification 1 has a terminal portion 35 obtained by forming an additional metal film 34 on the terminal portion 33, for example.
- the terminal portion 35 includes a surface 35S protruding from both the facing surface 32S and the facing surface 12S. Therefore, the heights of the plurality of terminal portions 35 can be easily aligned by, for example, CMP. Therefore, the solid-state imaging device 1A having higher dimensional accuracy can be realized.
- FIG. 5 is a cross-sectional view showing an overall configuration example of the solid-state imaging device 2 according to the second embodiment of the present disclosure.
- the solid-state imaging device 2 is different from the solid-state imaging device 1 in that it includes a circuit board 50 instead of the circuit board 10 .
- the circuit board 50 has, for example, a support substrate 111, insulating films 12 to 14, a chip 30, and an intermediate member 112.
- the insulating film 12 extends in the XY plane so as to entirely cover the upper surface of the support substrate 111 .
- the chip 30 is arranged on the insulating film 12 .
- the intermediate member 112 is arranged on the support substrate 111 with the insulating films 14 and 13 interposed therebetween. The intermediate member 112 and the chip 30 are provided adjacent to each other in the XY plane.
- the intermediate member 112 is in contact with the end face 30T of the chip 30 via the insulating film 13 .
- the insulating films 13 and 14 are made of inorganic oxides such as silicon oxide (SiOx) and silicon nitride (SiNx).
- the facing surface 20S of the sensor substrate 20 and the facing surface 50S of the circuit board 50 are joined.
- the facing surface 20S of the sensor substrate 20 includes the facing surface 22S of the wiring layer 22 and the surface 23S of the terminal portion 23 .
- the facing surface 50 ⁇ /b>S of the circuit board 50 includes the surface 112 ⁇ /b>S of the intermediate member 112 , the facing surface 32 ⁇ /b>S of the circuit forming layer 32 , and the surface 33 ⁇ /b>S of the terminal portion 33 .
- FIGS. 6A to 6I are cross-sectional views showing one step of the manufacturing method of the solid-state imaging device 2, respectively, and correspond to FIG.
- a resist mask RM3 is formed on the upper surface of the semiconductor substrate 112Z.
- the resist mask RM3 is formed with an opening K3 in a region corresponding to the region where the recess 112U for housing the chip 30 is to be formed.
- recesses 112U are formed in the semiconductor substrate 112Z.
- the portion of the semiconductor substrate 112Z that is not covered with the resist mask RM3, that is, the portion corresponding to the opening K3 is dug down by dry etching, for example.
- an insulating film 13 is formed to cover the entire semiconductor substrate 112Z, as shown in FIG. 6C.
- the insulating film 13 can be formed by, for example, a sputtering method or a CVD method. At that time, the insulating film 13 is conformally formed so as to maintain the shape of the concave portion 112U as much as possible.
- the chip 30 is placed in the recess 112U.
- the upper surface 30S of the chip 30 may face the recess 112U, and a resin adhesive may be applied to the upper surface 30S to adhere and fix the chip 30 to the recess 112U.
- the rear surface of the chip 30 protrudes upward from the upper surface of the insulating film 13. As shown in FIG.
- an insulating film 14Z is formed so as to entirely cover the insulating film 13 and the chip 30 placed in the recess 112U.
- the insulating film 14Z can be formed by, for example, a coating method.
- the insulating film 14Z is polished and planarized by chemical mechanical polishing (CMP), for example, to obtain the insulating film 14 as shown in FIG. 6F.
- CMP chemical mechanical polishing
- CMP is performed until the back surface of the substrate 31 of the chip 30 is exposed.
- a facing surface 31S including the front surface of the insulating film 14 and the rear surface of the substrate 31 is formed.
- a structure 50Z is prepared.
- the structural body 50Z is obtained by laminating an insulating film 12 on a support substrate 111 which is a semiconductor substrate. Subsequently, the structure 50Z is attached to the facing surface 31S.
- the semiconductor substrate 112Z is polished by, for example, chemical mechanical polishing (CMP) from the side opposite to the structure 50Z, and thinned until the upper surface 30S of the chip 30 is exposed. As a result, the intermediate member 112 is formed and the circuit board 50 is completed.
- CMP chemical mechanical polishing
- a structure 20Z is prepared.
- the structural body 20Z is obtained by laminating a wiring layer 22 on an element forming substrate 21 including a photoelectric conversion portion 25 .
- a terminal portion 23 is provided on the wiring layer 22 .
- a surface 23S of the terminal portion 23 is exposed to the facing surface 22S.
- the structural body 20Z and the circuit board 50 are aligned in the XY plane with the facing surface 22S of the structural body 20Z and the facing surface 50S of the circuit board 50 facing each other.
- the structure 20Z and the circuit board 50 are bonded together.
- the surface 33S of the terminal portion 33 of the chip 30 and the surface 23S of the terminal portion 23 of the sensor substrate 20 are bonded by Cu--Cu, for example.
- the contact plug CP2 in which the terminal portion 33 and the terminal portion 23 are integrated is obtained.
- the element forming substrate 21 of the structure 20Z is thinned.
- a plurality of color filters 26 and a plurality of on-chip lenses 27 are laminated on the thinned device forming substrate 21 to form the solid-state imaging device 24 .
- the sensor substrate 20 is obtained (see FIG. 5).
- the solid-state imaging device 2 is completed through the above steps.
- FIG. 7 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.
- a camera 2000 includes an optical unit 2001 including a group of lenses and the like, and an imaging apparatus (imaging device) 2002 to which the above-described solid-state imaging devices 1, 1A to 1C, 2, 2A (hereinafter referred to as the solid-state imaging device 1 and the like) are applied. , and a DSP (Digital Signal Processor) circuit 2003 which is a camera signal processing circuit.
- the camera 2000 also includes a frame memory 2004 , a display section 2005 , a recording section 2006 , an operation section 2007 and a power supply section 2008 .
- DSP circuit 2003 , frame memory 2004 , display unit 2005 , recording unit 2006 , operation unit 2007 and power supply unit 2008 are interconnected via bus line 2009 .
- An optical unit 2001 captures incident light (image light) from a subject and forms an image on an imaging surface of an imaging device 2002 .
- the imaging device 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electric signal for each pixel, and outputs the electric signal as a pixel signal.
- the display unit 2005 is composed of, for example, a panel type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 2002 .
- a recording unit 2006 records a moving image or still image captured by the imaging device 2002 in a recording medium such as a hard disk or a semiconductor memory.
- the operation unit 2007 issues operation commands for various functions of the camera 2000 under the user's operation.
- a power supply unit 2008 appropriately supplies various power supplies as operating power supplies for the DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, and the operation unit 2007 to these supply targets.
- the technology (the present technology) according to the present disclosure can be applied to various products.
- the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
- FIG. 8 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
- a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
- the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050.
- a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
- the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
- the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
- the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
- the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
- the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
- the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
- the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
- the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
- the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
- the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
- the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
- the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
- the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
- the in-vehicle information detection unit 12040 detects in-vehicle information.
- the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
- the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
- the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
- a control command can be output to 12010 .
- the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving
- the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
- the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
- the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
- the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
- an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
- the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
- FIG. 9 is a diagram showing an example of the installation position of the imaging unit 12031.
- the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
- the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
- An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
- Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
- An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
- the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
- FIG. 9 shows an example of the imaging range of the imaging units 12101 to 12104.
- the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
- the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
- the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
- At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
- at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
- the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
- automatic brake control including following stop control
- automatic acceleration control including following start control
- the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
- At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
- the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
- recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
- the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
- the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
- the solid-state imaging device 1 or the like shown in FIG. 1A or the like can be applied to the imaging unit 12031 .
- excellent operation of the vehicle control system can be expected.
- the solid-state imaging device 1 has a structure in which the sensor substrate 20 is laminated on the circuit board 10, but the present disclosure is not limited to this.
- the present disclosure is not limited to this.
- three or more substrates may be laminated.
- another circuit board 60 is further inserted between the circuit board 10 and the sensor board 20 .
- the end face 30T of the chip 30 is brought into contact with the intermediate member 112 through the insulating film 12, but the present disclosure is limited to this. is not.
- a space may be provided between the end surface 30T of the chip 30 and the side wall of the recess 10U.
- a protective layer 40 may be filled in the gap between the end surface 30T of the chip 30 and the side wall of the recess 10U.
- the technology according to the present disclosure can also have the following configuration.
- the intermediate member is provided in the gap between the first substrate and the second substrate so as to be adjacent to the chip in the in-plane direction orthogonal to the first direction. Therefore, for example, the thickness of the protective layer provided in the gap between the first substrate and the second substrate so as to cover the chip may be thin. As a result, it is possible to realize a structure suitable for thinning while having good imaging performance.
- the effects of the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
- a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel; a second substrate arranged to face the first substrate in a first direction; a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal; an intermediate member located in a gap between the first substrate and the second substrate and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
- the imaging device according to (1) wherein the intermediate member is in contact with the chip via an insulating film in the in-plane direction.
- the chip is a third substrate; a circuit forming layer provided on the third substrate;
- the distance between the chip and the first substrate in the first direction is substantially equal to the distance between the intermediate member and the first substrate according to any one of (1) to (8) above.
- Imaging device (10) The imaging device according to any one of (1) to (8), wherein the distance between the chip and the first substrate is narrower than the distance between the intermediate member and the first substrate in the first direction. . (11) The imaging device according to any one of (1) to (8) above, wherein the distance between the chip and the first substrate is wider than the distance between the intermediate member and the first substrate in the first direction. .
- a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel; a second substrate having a recess facing the first substrate in a first direction; A chip located between the first substrate and the second substrate, partially or entirely accommodated in the recess in the first direction, and having a circuit for performing signal processing of the pixel signal.
- the imaging device according to (12) above further comprising a protective layer filled in a gap between the first substrate and the second substrate so as to cover the chip.
- the intermediate member has a second thermal conductivity higher than a first thermal conductivity of the protective layer.
- the chip has a third substrate, an insulating layer provided on the third substrate, and wiring embedded in the insulating layer, The method for manufacturing an imaging device according to (16) above, wherein the wiring is exposed from the insulating layer by planarizing the protective layer.
- the imaging device is a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel; a second substrate arranged to face the first substrate in a first direction; a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
- An electronic device comprising: an intermediate member located in a gap between the first substrate and the second substrate, and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
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Abstract
Provided is an imaging device which has good imaging performance and has a structure suitable for thickness reduction. The imaging device comprises: a first substrate; a second substrate; a chip; and an intermediate member. The first substrate has an image element which includes a plurality of pixels and is capable of generating a pixel signal for each pixel. The second substrate is disposed so as to oppose the first substrate in a first direction. The chip is disposed between the first substrate and the second substrate, and has a circuit for processing the pixel signal. The intermediate member is located in a gap between the first substrate and the second substrate, and is disposed adjacent to the chip in an in-plane direction orthogonal to the first direction.
Description
本開示は、撮像素子を有する撮像装置およびその製造方法、ならびにその撮像装置を備えた電子機器に関する。
The present disclosure relates to an imaging device having an imaging element, a manufacturing method thereof, and an electronic device provided with the imaging device.
これまでに、撮像装置の小型化を実現するため、画素信号を生成する撮像素子を含むウェハと、その撮像素子の生成する画素信号の信号処理を行う信号処理回路やメモリ回路などを含むウェハとを接合するWoW(Wafer on Wafer)積層技術が提案されている(例えば特許文献1)。
Until now, in order to reduce the size of imaging devices, wafers containing image sensors that generate pixel signals and wafers that include signal processing circuits and memory circuits for processing the pixel signals generated by the image sensors have been proposed. WoW (Wafer on Wafer) lamination technology has been proposed (for example, Patent Document 1).
ところで、このような撮像装置に対しては、さらなる薄型化が要求されている。
By the way, further reduction in thickness is required for such an imaging device.
したがって、良好な撮像性能を有しつつ、薄型化に適した構造を有する撮像装置およびその製造方法、ならびに、そのような撮像装置を備えた電子機器を提供することが望まれる。
Therefore, it is desired to provide an imaging device having a structure suitable for thinning while having good imaging performance, a manufacturing method thereof, and an electronic device equipped with such an imaging device.
本開示の一実施形態に係る撮像装置は、第1基板と、第2基板と、チップと、中間部材とを備える。第1基板は、複数の画素を含んで画素ごとに画素信号を生成可能な撮像素子を有する。第2基板は、第1方向において第1基板と対向するように配置される。チップは、第1基板と第2基板との間に設けられると共に画素信号の信号処理を行う回路を有する。中間部材は、第1基板と第2基板との隙間に位置し、第1方向と直交する面内方向においてチップと隣り合うように設けられている。
An imaging device according to an embodiment of the present disclosure includes a first substrate, a second substrate, a chip, and an intermediate member. The first substrate has an imaging element that includes a plurality of pixels and can generate a pixel signal for each pixel. The second substrate is arranged to face the first substrate in the first direction. The chip is provided between the first substrate and the second substrate and has a circuit for performing signal processing of pixel signals. The intermediate member is located in a gap between the first substrate and the second substrate, and is provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
本開示の一実施形態に係る撮像装置では、中間部材が第1基板と第2基板との隙間に、第1方向と直交する面内方向においてチップと隣り合うように設けられている。このため、例えば第1基板と第2基板と隙間にチップを覆うように設けられる保護層の厚さが薄くてすむ。
In the imaging device according to the embodiment of the present disclosure, the intermediate member is provided in the gap between the first substrate and the second substrate so as to be adjacent to the chip in the in-plane direction orthogonal to the first direction. Therefore, for example, the thickness of the protective layer provided in the gap between the first substrate and the second substrate so as to cover the chip may be thin.
以下、本開示における実施形態について、図面を参照して詳細に説明する。以下で説明する実施形態は本開示の一具体例であって、本開示にかかる技術が以下の態様に限定されるわけではない。また、本開示の各構成要素の配置、寸法、及び寸法比等についても、各図に示す様態に限定されるわけではない。
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are specific examples of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Also, the arrangement, dimensions, dimensional ratios, and the like of each component of the present disclosure are not limited to the modes shown in the drawings.
なお、説明は以下の順序で行う。
1.第1の実施形態
1.1.構成例
1.2.製造方法
1.3.作用効果
1.4.変形例
2.第2の実施形態
2.1.構成例
2.2.製造方法
2.3.作用効果
3.電子機器への適用例
4.移動体への応用例
5.その他の変形例 The description will be given in the following order.
1. First Embodiment 1.1. Configuration example 1.2. Manufacturing method 1.3. Action and effect 1.4.Modification 2. Second Embodiment 2.1. Configuration example 2.2. Manufacturing method 2.3. Action and effect 3. Application example to electronic equipment 4 . Example of application to mobile body 5 . Other variations
1.第1の実施形態
1.1.構成例
1.2.製造方法
1.3.作用効果
1.4.変形例
2.第2の実施形態
2.1.構成例
2.2.製造方法
2.3.作用効果
3.電子機器への適用例
4.移動体への応用例
5.その他の変形例 The description will be given in the following order.
1. First Embodiment 1.1. Configuration example 1.2. Manufacturing method 1.3. Action and effect 1.4.
<1.第1の実施形態>
[1.1.構成例]
(全体構成例)
まず、図1Aおよび図1Bを参照して、本開示の第1の実施形態としての固体撮像装置1の全体構成例について説明する。図1Aは、固体撮像装置1の断面構成を表し、図1Bは、固体撮像装置1の平面構成を表している。図1Aは、図1Bに示したIA-IA切断線に沿った矢視方向の断面図に相当する。 <1. First Embodiment>
[1.1. Configuration example]
(Overall configuration example)
First, an overall configuration example of a solid-state imaging device 1 as a first embodiment of the present disclosure will be described with reference to FIGS. 1A and 1B. 1A shows a cross-sectional configuration of the solid-state imaging device 1, and FIG. 1B shows a planar configuration of the solid-state imaging device 1. FIG. FIG. 1A corresponds to a cross-sectional view taken along the IA-IA line shown in FIG. 1B.
[1.1.構成例]
(全体構成例)
まず、図1Aおよび図1Bを参照して、本開示の第1の実施形態としての固体撮像装置1の全体構成例について説明する。図1Aは、固体撮像装置1の断面構成を表し、図1Bは、固体撮像装置1の平面構成を表している。図1Aは、図1Bに示したIA-IA切断線に沿った矢視方向の断面図に相当する。 <1. First Embodiment>
[1.1. Configuration example]
(Overall configuration example)
First, an overall configuration example of a solid-
固体撮像装置1は、例えば、回路基板10と、センサ基板20と、チップ30と、保護層40とを備えている。
The solid-state imaging device 1 includes, for example, a circuit board 10, a sensor board 20, a chip 30, and a protective layer 40.
回路基板10およびセンサ基板20は、それぞれ、例えばXY面内方向に広がっている。回路基板10とセンサ基板20とは、Z軸方向において互いに対向するように配置されている。本実施の形態では、回路基板10とセンサ基板20との積層方向をZ軸方向とし、回路基板10およびセンサ基板20が広がる面をXY面とする。図1Aおよび図1Bにおいて、符号K1は固体撮像装置1の外縁を表している。固体撮像装置1の外縁K1は、例えば、回路基板10の最外縁およびセンサ基板20の最外縁と一致している。回路基板10とセンサ基板20とは、例えば保護層40を介して接合されている。
The circuit board 10 and the sensor board 20 each extend, for example, in the XY plane direction. The circuit board 10 and the sensor board 20 are arranged so as to face each other in the Z-axis direction. In the present embodiment, the lamination direction of the circuit board 10 and the sensor board 20 is the Z-axis direction, and the plane on which the circuit board 10 and the sensor board 20 spread is the XY plane. 1A and 1B, reference character K1 represents the outer edge of the solid-state imaging device 1. FIG. The outer edge K1 of the solid-state imaging device 1 coincides with, for example, the outermost edge of the circuit board 10 and the outermost edge of the sensor substrate 20 . The circuit board 10 and the sensor board 20 are bonded via a protective layer 40, for example.
(センサ基板20)
センサ基板20は、素子形成基板21と配線層22との積層構造を有している。配線層22は、素子形成基板21から見て回路基板10と対向する側に設けられている。配線層22は、回路基板10と対向する対向面22Sを有している。配線層22には、端子部23が埋設されている。但し、端子部23の表面23Sは、対向面22Sに露出している。配線層22は、例えば絶縁性樹脂や金属酸化物、金属窒化物、または無機酸化物等の絶縁材料により構成されている。具体的には、配線層22の構成材料として、ポリイミド、シリコーン、エポキシ、アクリルなどの有機絶縁材料や、AlOx,AlNx,SiOx,SiNx,SiON,SiCN,SiOCなどの無機絶縁材料が挙げられる。端子部23は、例えばCu(銅)などの高導電性材料により構成されているとよい。 (Sensor substrate 20)
Thesensor substrate 20 has a layered structure of an element forming substrate 21 and a wiring layer 22 . The wiring layer 22 is provided on the side facing the circuit board 10 when viewed from the element forming substrate 21 . The wiring layer 22 has a facing surface 22S that faces the circuit board 10 . A terminal portion 23 is embedded in the wiring layer 22 . However, the surface 23S of the terminal portion 23 is exposed to the facing surface 22S. The wiring layer 22 is made of an insulating material such as an insulating resin, a metal oxide, a metal nitride, or an inorganic oxide. Specifically, the wiring layer 22 may be made of organic insulating materials such as polyimide, silicone, epoxy, and acrylic, and inorganic insulating materials such as AlOx, AlNx, SiOx, SiNx, SiON, SiCN, and SiOC. The terminal portion 23 is preferably made of a highly conductive material such as Cu (copper).
センサ基板20は、素子形成基板21と配線層22との積層構造を有している。配線層22は、素子形成基板21から見て回路基板10と対向する側に設けられている。配線層22は、回路基板10と対向する対向面22Sを有している。配線層22には、端子部23が埋設されている。但し、端子部23の表面23Sは、対向面22Sに露出している。配線層22は、例えば絶縁性樹脂や金属酸化物、金属窒化物、または無機酸化物等の絶縁材料により構成されている。具体的には、配線層22の構成材料として、ポリイミド、シリコーン、エポキシ、アクリルなどの有機絶縁材料や、AlOx,AlNx,SiOx,SiNx,SiON,SiCN,SiOCなどの無機絶縁材料が挙げられる。端子部23は、例えばCu(銅)などの高導電性材料により構成されているとよい。 (Sensor substrate 20)
The
素子形成基板21は、例えば珪素(Si)などの半導体材料からなる基板である。素子形成基板21には、固体撮像素子24が設けられている。本実施の形態では、センサ基板20に固体撮像素子24が設けられた、XY面内に広がる領域を有効画素領域R24(図1B参照)と呼ぶ。有効画素領域R24とは、例えば遮光領域(OPB)の内側の領域、すなわち、外光を受光可能な領域をいう。固体撮像素子24は、例えば、フォトダイオードなどの光電変換部25と、カラーフィルタ26と、オンチップレンズ27とをそれぞれ含む複数の画素PXがXY面に沿って配列されたものである。固体撮像素子24では、画素PXごとに外光を受光して画素PXごとに画素信号を生成可能である。端子部23は、チップ30の端子部33と電気的に接続されている。端子部23と端子部33との電気的接続により、例えば固体撮像素子24とチップ30に設けられた信号処理回路との電気的接続がなされている。
The element formation substrate 21 is a substrate made of a semiconductor material such as silicon (Si). A solid-state imaging device 24 is provided on the device forming substrate 21 . In the present embodiment, an area extending in the XY plane where the solid-state imaging device 24 is provided on the sensor substrate 20 is called an effective pixel area R24 (see FIG. 1B). The effective pixel area R24 is, for example, an area inside the light-shielding area (OPB), that is, an area capable of receiving external light. The solid-state imaging device 24 is formed by arranging a plurality of pixels PX each including a photoelectric conversion unit 25 such as a photodiode, a color filter 26, and an on-chip lens 27 along the XY plane. The solid-state imaging device 24 can receive external light for each pixel PX and generate a pixel signal for each pixel PX. The terminal portion 23 is electrically connected to the terminal portion 33 of the chip 30 . The electrical connection between the terminal portion 23 and the terminal portion 33 establishes electrical connection between, for example, the solid-state imaging device 24 and a signal processing circuit provided in the chip 30 .
(回路基板10)
回路基板10は、例えば、支持体11と、絶縁膜12とを有している。支持体11は、例えば、XY面内に広がる支持基板111と、支持基板111の上面111Sに設けられた中間部材112とを含んでいる。中間部材112は、支持基板111と素子形成基板21との隙間に位置し、XY面内方向においてチップ30と隣り合うように設けられている。中間部材112は、保護層40の第1熱伝導率よりも高い第2熱伝導率を有するとよい。本実施の形態では、支持基板111と中間部材112とは一体化されている。支持基板111の構成材料と中間部材112の構成材料とは、互いに実質的に同じであってもよい。支持基板111の構成材料および中間部材112の構成材料は、例えば、いずれも珪素(Si)である。絶縁膜12は、支持体11を一様に覆うように設けられている。絶縁膜12は、例えば酸化シリコン(SiOx)や窒化シリコン(SiNx)などの無機酸化物によって形成されている。絶縁膜12は、センサ基板20と対向する対向面12Sを有している。回路基板10には、センサ基板20と対向する側に1以上の凹部10Uが形成されている。なお、図1Bでは、センサ基板20の有効画素領域R24とZ軸方向において対応する位置に4つの凹部10Uが設けられている構成を例示しているが、本開示はこれに限定されるものではない。すなわち、凹部10Uが1個のみ設けられていてもよいし、2個、3個、もしくは5個以上の凹部10Uが設けられていてもよい。 (circuit board 10)
Thecircuit board 10 has, for example, a support 11 and an insulating film 12 . The support 11 includes, for example, a support substrate 111 extending in the XY plane, and an intermediate member 112 provided on the upper surface 111S of the support substrate 111 . The intermediate member 112 is located in the gap between the support substrate 111 and the element forming substrate 21 and is provided so as to be adjacent to the chip 30 in the XY plane direction. The intermediate member 112 may have a second thermal conductivity higher than the first thermal conductivity of the protective layer 40 . In this embodiment, the support substrate 111 and the intermediate member 112 are integrated. The constituent material of the support substrate 111 and the constituent material of the intermediate member 112 may be substantially the same. The constituent material of the support substrate 111 and the constituent material of the intermediate member 112 are both silicon (Si), for example. The insulating film 12 is provided so as to uniformly cover the support 11 . The insulating film 12 is made of an inorganic oxide such as silicon oxide (SiOx) or silicon nitride (SiNx). The insulating film 12 has a facing surface 12S facing the sensor substrate 20 . One or more recesses 10U are formed in the circuit board 10 on the side facing the sensor board 20 . Note that FIG. 1B illustrates a configuration in which four recesses 10U are provided at positions corresponding to the effective pixel region R24 of the sensor substrate 20 in the Z-axis direction, but the present disclosure is not limited to this. do not have. That is, only one concave portion 10U may be provided, or two, three, or five or more concave portions 10U may be provided.
回路基板10は、例えば、支持体11と、絶縁膜12とを有している。支持体11は、例えば、XY面内に広がる支持基板111と、支持基板111の上面111Sに設けられた中間部材112とを含んでいる。中間部材112は、支持基板111と素子形成基板21との隙間に位置し、XY面内方向においてチップ30と隣り合うように設けられている。中間部材112は、保護層40の第1熱伝導率よりも高い第2熱伝導率を有するとよい。本実施の形態では、支持基板111と中間部材112とは一体化されている。支持基板111の構成材料と中間部材112の構成材料とは、互いに実質的に同じであってもよい。支持基板111の構成材料および中間部材112の構成材料は、例えば、いずれも珪素(Si)である。絶縁膜12は、支持体11を一様に覆うように設けられている。絶縁膜12は、例えば酸化シリコン(SiOx)や窒化シリコン(SiNx)などの無機酸化物によって形成されている。絶縁膜12は、センサ基板20と対向する対向面12Sを有している。回路基板10には、センサ基板20と対向する側に1以上の凹部10Uが形成されている。なお、図1Bでは、センサ基板20の有効画素領域R24とZ軸方向において対応する位置に4つの凹部10Uが設けられている構成を例示しているが、本開示はこれに限定されるものではない。すなわち、凹部10Uが1個のみ設けられていてもよいし、2個、3個、もしくは5個以上の凹部10Uが設けられていてもよい。 (circuit board 10)
The
(チップ30)
チップ30は、センサ基板20と回路基板10の支持基板111との間に設けられている。チップ30は、例えば、基板31と、基板31上に設けられる回路形成層32と、回路形成層32に設けられる端子部33とを有している。基板31は、例えば珪素(Si)などの半導体材料からなる基板である。回路形成層32には、例えばトランジスタなどの半導体素子と、配線とを含む信号処理回路が設けられている。回路形成層32に設けられた信号処理回路は、例えば固体撮像素子24からの画素信号の信号処理を行うものである。回路形成層32は、センサ基板20と対向する対向面32Sを有している。図1Aに示した構成例では、対向面32Sは、例えば、保護層40の厚さの分だけ対向面12Sよりも突出している。したがって、Z軸方向において、チップ30の対向面32Sと素子形成基板21との間隔が、中間部材112と素子形成基板21との間隔よりも狭くなっている。但し、Z軸方向において、保護層40の厚さが極めて薄く、チップ30と素子形成基板21との間隔が中間部材112と素子形成基板21との間隔と実質的に等しくなっていてもよい。端子部33は、回路形成層32に埋設されている。但し、端子部33の表面33Sは、対向面32Sに露出している。回路形成層32は、例えば絶縁性樹脂、金属酸化物、金属窒化物、または無機酸化物等の絶縁材料により構成されている。具体的には、回路形成層32の構成材料として、ポリイミド、シリコーン、エポキシ、アクリルなどの有機絶縁材料や、AlOx,AlNx,SiOx,SiNx,SiON,SiCN,SiOCなどの無機絶縁材料が挙げられる。端子部33は、例えばCu(銅)などの高導電性材料により構成されているとよい。 (Chip 30)
Thechip 30 is provided between the sensor board 20 and the support board 111 of the circuit board 10 . The chip 30 has, for example, a substrate 31 , a circuit forming layer 32 provided on the substrate 31 , and terminal portions 33 provided on the circuit forming layer 32 . The substrate 31 is a substrate made of a semiconductor material such as silicon (Si). The circuit formation layer 32 is provided with a signal processing circuit including, for example, semiconductor elements such as transistors and wiring. The signal processing circuit provided in the circuit forming layer 32 performs signal processing of pixel signals from the solid-state imaging device 24, for example. The circuit forming layer 32 has a facing surface 32S that faces the sensor substrate 20 . In the configuration example shown in FIG. 1A, the facing surface 32S protrudes from the facing surface 12S by the thickness of the protective layer 40, for example. Therefore, the distance between the facing surface 32S of the chip 30 and the element forming substrate 21 is narrower than the distance between the intermediate member 112 and the element forming substrate 21 in the Z-axis direction. However, the protection layer 40 may be extremely thin in the Z-axis direction, and the distance between the chip 30 and the element forming substrate 21 may be substantially equal to the distance between the intermediate member 112 and the element forming substrate 21 . The terminal portion 33 is embedded in the circuit forming layer 32 . However, the surface 33S of the terminal portion 33 is exposed to the facing surface 32S. The circuit forming layer 32 is made of an insulating material such as an insulating resin, metal oxide, metal nitride, or inorganic oxide. Specifically, the constituent materials of the circuit forming layer 32 include organic insulating materials such as polyimide, silicone, epoxy, and acrylic, and inorganic insulating materials such as AlOx, AlNx, SiOx, SiNx, SiON, SiCN, and SiOC. The terminal portion 33 is preferably made of a highly conductive material such as Cu (copper).
チップ30は、センサ基板20と回路基板10の支持基板111との間に設けられている。チップ30は、例えば、基板31と、基板31上に設けられる回路形成層32と、回路形成層32に設けられる端子部33とを有している。基板31は、例えば珪素(Si)などの半導体材料からなる基板である。回路形成層32には、例えばトランジスタなどの半導体素子と、配線とを含む信号処理回路が設けられている。回路形成層32に設けられた信号処理回路は、例えば固体撮像素子24からの画素信号の信号処理を行うものである。回路形成層32は、センサ基板20と対向する対向面32Sを有している。図1Aに示した構成例では、対向面32Sは、例えば、保護層40の厚さの分だけ対向面12Sよりも突出している。したがって、Z軸方向において、チップ30の対向面32Sと素子形成基板21との間隔が、中間部材112と素子形成基板21との間隔よりも狭くなっている。但し、Z軸方向において、保護層40の厚さが極めて薄く、チップ30と素子形成基板21との間隔が中間部材112と素子形成基板21との間隔と実質的に等しくなっていてもよい。端子部33は、回路形成層32に埋設されている。但し、端子部33の表面33Sは、対向面32Sに露出している。回路形成層32は、例えば絶縁性樹脂、金属酸化物、金属窒化物、または無機酸化物等の絶縁材料により構成されている。具体的には、回路形成層32の構成材料として、ポリイミド、シリコーン、エポキシ、アクリルなどの有機絶縁材料や、AlOx,AlNx,SiOx,SiNx,SiON,SiCN,SiOCなどの無機絶縁材料が挙げられる。端子部33は、例えばCu(銅)などの高導電性材料により構成されているとよい。 (Chip 30)
The
チップ30は、例えば回路基板10に形成された凹部10Uに収容されている。回路基板10の中間部材112は、XY面内方向において絶縁膜12を介してチップ30の端面30Tと接している。
The chip 30 is housed in a recess 10U formed in the circuit board 10, for example. The intermediate member 112 of the circuit board 10 is in contact with the end surface 30T of the chip 30 via the insulating film 12 in the XY plane direction.
(保護層40)
保護層40は、上述したように、回路基板10とセンサ基板20とを接合する部材である。保護層40は、チップ30を覆うように回路基板10とセンサ基板20との隙間に充填されている。保護層40の構成材料としては、例えばポリイミド、シリコーン、エポキシ、アクリルなどの有機材料や、SiOx,SiNx,SiON,SiCN,SiOCなどの無機材料が挙げられる。 (Protective layer 40)
Theprotective layer 40 is a member that joins the circuit board 10 and the sensor board 20 as described above. The protective layer 40 fills the gap between the circuit board 10 and the sensor board 20 so as to cover the chip 30 . Examples of constituent materials of the protective layer 40 include organic materials such as polyimide, silicone, epoxy, and acrylic, and inorganic materials such as SiOx, SiNx, SiON, SiCN, and SiOC.
保護層40は、上述したように、回路基板10とセンサ基板20とを接合する部材である。保護層40は、チップ30を覆うように回路基板10とセンサ基板20との隙間に充填されている。保護層40の構成材料としては、例えばポリイミド、シリコーン、エポキシ、アクリルなどの有機材料や、SiOx,SiNx,SiON,SiCN,SiOCなどの無機材料が挙げられる。 (Protective layer 40)
The
[1.2.製造方法]
続いて、図2A~図2Gを参照して、本実施形態に係る固体撮像装置1の製造方法について説明する。図2A~図2Gは、固体撮像装置1の製造方法の一工程をそれぞれ表す断面図であり、図1Aに対応するものである。 [1.2. Production method]
Next, a method for manufacturing the solid-state imaging device 1 according to this embodiment will be described with reference to FIGS. 2A to 2G. 2A to 2G are cross-sectional views respectively showing one step of the manufacturing method of the solid-state imaging device 1, corresponding to FIG. 1A.
続いて、図2A~図2Gを参照して、本実施形態に係る固体撮像装置1の製造方法について説明する。図2A~図2Gは、固体撮像装置1の製造方法の一工程をそれぞれ表す断面図であり、図1Aに対応するものである。 [1.2. Production method]
Next, a method for manufacturing the solid-
まず、図2Aに示したように、Si基板などの半導体基板11Zを用意したのち、半導体基板11Zの上面にレジストマスクRMを形成する。例えばフォトリソグラフィ法により、レジストマスクRMには、チップ30を収容するための凹部10Uを形成すべき領域と対応する領域に開口Kを形成する。
First, as shown in FIG. 2A, after preparing a semiconductor substrate 11Z such as a Si substrate, a resist mask RM is formed on the upper surface of the semiconductor substrate 11Z. For example, by photolithography, the resist mask RM is formed with an opening K in a region corresponding to the region where the recess 10U for accommodating the chip 30 is to be formed.
次に、図2Bに示したように、凹部10Uを形成する。具体的には、半導体基板11Zのうち、レジストマスクRMにより覆われていない部分、すなわち開口Kと対応する部分を、例えばドライエッチングにより掘り下げる。その結果、支持基板111と中間部材112とが一体化した支持体11が完成する。
Next, as shown in FIG. 2B, recesses 10U are formed. Specifically, the portion of the semiconductor substrate 11Z that is not covered with the resist mask RM, that is, the portion corresponding to the opening K is dug down by dry etching, for example. As a result, the support 11 in which the support substrate 111 and the intermediate member 112 are integrated is completed.
次に、レジストマスクRMを除去したのち、図2Cに示したように、支持体11の全体を覆うように絶縁膜12を形成する。絶縁膜12は、例えばスパッタリング法やCVD法により形成することができる。その際、凹部10Uの形状をできるだけ維持するように、絶縁膜12をコンフォーマルに形成する。
Next, after removing the resist mask RM, an insulating film 12 is formed to cover the entire support 11 as shown in FIG. 2C. The insulating film 12 can be formed by, for example, a sputtering method or a CVD method. At that time, the insulating film 12 is conformally formed so as to maintain the shape of the concave portion 10U as much as possible.
次に、図2Dに示したように、凹部10Uにチップ30を載置する。その際、例えばチップ30の基板31の裏面などに樹脂接着剤を塗布し、チップ30を凹部10Uに接着して固定するようにしてもよい。図2Dに示したように、凹部10Uにチップ30を載置した段階では、チップ30の上面30Sが絶縁膜12の対向面12Sよりも上方へ、すなわち支持基板111から遠ざかる方向に突出した状態となっている。
Next, as shown in FIG. 2D, the chip 30 is placed in the recess 10U. At this time, for example, a resin adhesive may be applied to the back surface of the substrate 31 of the chip 30 to adhere and fix the chip 30 to the concave portion 10U. As shown in FIG. 2D, when the chip 30 is placed in the recess 10U, the upper surface 30S of the chip 30 protrudes above the opposing surface 12S of the insulating film 12, that is, in a direction away from the support substrate 111. It's becoming
次に、図2Eに示したように、回路基板10と、凹部10Uに載置されたチップ30との全体を覆うように保護膜40Zを形成する。保護膜40Zは、例えば塗布法により形成することができる。
Next, as shown in FIG. 2E, a protective film 40Z is formed to cover the entire circuit board 10 and the chip 30 placed in the recess 10U. The protective film 40Z can be formed by, for example, a coating method.
次に、例えば化学機械研磨(CMP)により保護膜40Zを研磨しつつ平坦化し、図2Fに示したように、保護層40を得る。その際、チップ30の端子部33の表面33Sが露出するまでCMPを行う。その結果、対向面32Sが形成される。
Next, the protective film 40Z is polished and planarized by chemical mechanical polishing (CMP), for example, to obtain the protective layer 40 as shown in FIG. 2F. At that time, CMP is performed until the surface 33S of the terminal portion 33 of the chip 30 is exposed. As a result, the facing surface 32S is formed.
次に、図2Gに示したように、構造体20Zを用意する。構造体20Zは、光電変換部25を含む素子形成基板21に配線層22が積層されたものである。配線層22には端子部23が設けられている。端子部23の表面23Sは、対向面22Sに露出している。ここで、構造体20Zの対向面22Sと、回路基板10に設けられた保護層40およびチップ30の対向面32Sとが対向した状態で、構造体20Zと回路基板10とのXY面内における位置合わせを行う。そののち、構造体20Zと回路基板10との貼り合わせを行う。ここでは、チップ30の端子部33の表面33Sとセンサ基板20の端子部23の表面23Sとを例えばCu-Cu接合する。これにより、端子部33と端子部23とが一体化されてなるコンタクトプラグCPが得られる。
Next, as shown in FIG. 2G, a structure 20Z is prepared. The structural body 20Z is obtained by laminating a wiring layer 22 on an element forming substrate 21 including a photoelectric conversion portion 25 . A terminal portion 23 is provided on the wiring layer 22 . A surface 23S of the terminal portion 23 is exposed to the facing surface 22S. Here, in a state in which the facing surface 22S of the structural body 20Z faces the protective layer 40 provided on the circuit board 10 and the facing surface 32S of the chip 30, the position of the structural body 20Z and the circuit board 10 in the XY plane is determined. Align. After that, the structure 20Z and the circuit board 10 are bonded together. Here, the surface 33S of the terminal portion 33 of the chip 30 and the surface 23S of the terminal portion 23 of the sensor substrate 20 are bonded by Cu--Cu, for example. Thereby, the contact plug CP in which the terminal portion 33 and the terminal portion 23 are integrated is obtained.
次に、構造体20Zの素子形成基板21を薄肉化する。最後に、薄肉化された素子形成基板21の上に、複数のカラーフィルタ26と複数のオンチップレンズ27とをそれぞれ積層することにより固体撮像素子24を形成する。これにより、センサ基板20を得る(図1A参照)。
Next, the element forming substrate 21 of the structure 20Z is thinned. Finally, a plurality of color filters 26 and a plurality of on-chip lenses 27 are laminated on the thinned device forming substrate 21 to form the solid-state imaging device 24 . This obtains the sensor substrate 20 (see FIG. 1A).
以上の工程により、固体撮像装置1が完成する。
The solid-state imaging device 1 is completed through the above steps.
[1.3.作用効果]
本実施の形態の固体撮像装置1では、素子形成基板21と支持基板111との隙間に、Z軸方向と直交するXY面内方向においてチップ30と隣り合うように中間部材112が設けられている。このため、例えば素子形成基板21と支持基板111との隙間に、チップ30を覆うように設けられる保護層40の厚さが薄くてすむ。保護層40の厚さが薄くなることにより、例えばセンサ基板20と回路基板10との接合に伴ってチップ30に印加される応力が緩和される。チップ30に印加される応力は、例えば、保護層40およびその周辺部分の歪みに起因するものである。さらに、保護層40の厚さが薄くなることにより、保護層40のXY面内での平坦性が向上する。すなわち、例えば支持基板111に対する素子形成基板21の傾きを十分に低減することができる。その結果、支持基板111と素子形成基板21との間隔のばらつきを低減することができ、固体撮像装置1の動作信頼性を向上させることができる。 [1.3. Action effect]
In the solid-state imaging device 1 of the present embodiment, the intermediate member 112 is provided in the gap between the element forming substrate 21 and the support substrate 111 so as to be adjacent to the chip 30 in the XY plane direction orthogonal to the Z-axis direction. . Therefore, the protective layer 40 provided to cover the chip 30 in the gap between the element forming substrate 21 and the support substrate 111, for example, can be thin. By reducing the thickness of the protective layer 40, the stress applied to the chip 30 due to bonding of the sensor substrate 20 and the circuit substrate 10, for example, is alleviated. The stress applied to the chip 30 is due, for example, to the distortion of the protective layer 40 and its peripheral portion. Furthermore, by reducing the thickness of the protective layer 40, the flatness of the protective layer 40 in the XY plane is improved. That is, for example, the inclination of the element formation substrate 21 with respect to the support substrate 111 can be sufficiently reduced. As a result, variations in the distance between the support substrate 111 and the element forming substrate 21 can be reduced, and the operational reliability of the solid-state imaging device 1 can be improved.
本実施の形態の固体撮像装置1では、素子形成基板21と支持基板111との隙間に、Z軸方向と直交するXY面内方向においてチップ30と隣り合うように中間部材112が設けられている。このため、例えば素子形成基板21と支持基板111との隙間に、チップ30を覆うように設けられる保護層40の厚さが薄くてすむ。保護層40の厚さが薄くなることにより、例えばセンサ基板20と回路基板10との接合に伴ってチップ30に印加される応力が緩和される。チップ30に印加される応力は、例えば、保護層40およびその周辺部分の歪みに起因するものである。さらに、保護層40の厚さが薄くなることにより、保護層40のXY面内での平坦性が向上する。すなわち、例えば支持基板111に対する素子形成基板21の傾きを十分に低減することができる。その結果、支持基板111と素子形成基板21との間隔のばらつきを低減することができ、固体撮像装置1の動作信頼性を向上させることができる。 [1.3. Action effect]
In the solid-
また、本実施の形態の固体撮像装置1では、凹部10Uにチップ30を埋め込むように配置している。このため、支持基板111の厚さを薄くすることができる。支持基板111の厚さを薄くした場合であっても、中間部材112を設けるようにしているので、回路基板10の全体としての機械的強度を維持することができるからである。支持基板111の厚さを薄くすることによって、固体撮像装置1の全体の薄型化が可能となる。また、固体撮像装置1の全体を薄型化したとしても、固体撮像装置1では凹部10Uにチップ30を埋め込むように配置しているので、チップ30の厚さを維持することができる。したがって、基板31に求められる絶縁耐圧や機械的強度を十分に確保することができる。よって、固体撮像装置1の長期信頼性を向上させることができる。
Further, in the solid-state imaging device 1 of the present embodiment, the chip 30 is arranged so as to be embedded in the concave portion 10U. Therefore, the thickness of the support substrate 111 can be reduced. This is because even if the support substrate 111 is made thin, the mechanical strength of the circuit board 10 as a whole can be maintained because the intermediate member 112 is provided. By reducing the thickness of the support substrate 111, the overall thickness of the solid-state imaging device 1 can be reduced. Further, even if the entire solid-state imaging device 1 is made thinner, the thickness of the chip 30 can be maintained because the chip 30 is embedded in the concave portion 10U in the solid-state imaging device 1 . Therefore, the withstand voltage and mechanical strength required for the substrate 31 can be sufficiently secured. Therefore, long-term reliability of the solid-state imaging device 1 can be improved.
また、本実施の形態の固体撮像装置1では、XY面内方向においてチップ30と隣り合うように中間部材112を配置している。中間部材112は、保護層40の第1熱伝導率よりも高い第2熱伝導率を有している。このため、例えば中間部材112が存在せずに保護層40がチップ30の大部分を覆っている場合と比較して、チップ30で生じた熱を外部に効率的に放出することができる。この点においても、固体撮像装置1の動作信頼性を向上させることができる。
Further, in the solid-state imaging device 1 of the present embodiment, the intermediate member 112 is arranged so as to be adjacent to the chip 30 in the XY plane direction. The intermediate member 112 has a second thermal conductivity higher than the first thermal conductivity of the protective layer 40 . Therefore, heat generated in the chip 30 can be efficiently released to the outside, for example, compared to the case where the protective layer 40 covers most of the chip 30 without the intermediate member 112 present. In this respect as well, the operational reliability of the solid-state imaging device 1 can be improved.
[1.4.変形例]
(全体構成例)
上記第1の実施の形態の固体撮像装置1では、素子形成基板21に対し、チップ30の対向面32Sが回路基板10の対向面12Sよりも保護層40の厚さの分だけ突出している場合を説明した。しかしながら、本開示では、例えば図3に示した固体撮像装置1Aのように、素子形成基板21に対し、チップ30Aの対向面32Sが回路基板10の対向面12Sよりも凹んでいてもよい。すなわち、Z軸方向において、チップ30Aの対向面32Sと素子形成基板21との間隔が、中間部材112と素子形成基板21との間隔よりも広くなっている。但し、固体撮像装置1Aのチップ30Aは、端子部33の代わりに端子部35を有している。端子部35は、回路形成層32の対向面32Sおよび回路基板10の対向面12Sの双方よりも突出した表面35Sを含んでいる。なお、図3は、第1の実施の形態の第1変形例(以下、変形例1という。)に係る固体撮像装置1Aの全体構成例を表す断面図である。 [1.4. Modification]
(Overall configuration example)
In the solid-state imaging device 1 of the first embodiment, when the facing surface 32S of the chip 30 protrudes from the facing surface 12S of the circuit board 10 with respect to the element forming substrate 21 by the thickness of the protective layer 40. explained. However, in the present disclosure, for example, like the solid-state imaging device 1A shown in FIG. That is, the distance between the facing surface 32S of the chip 30A and the element forming substrate 21 is wider than the distance between the intermediate member 112 and the element forming substrate 21 in the Z-axis direction. However, the chip 30A of the solid-state imaging device 1A has a terminal section 35 instead of the terminal section 33. FIG. The terminal portion 35 includes a surface 35S protruding from both the facing surface 32S of the circuit forming layer 32 and the facing surface 12S of the circuit board 10. As shown in FIG. Note that FIG. 3 is a cross-sectional view showing an overall configuration example of a solid-state imaging device 1A according to a first modification (hereinafter referred to as modification 1) of the first embodiment.
(全体構成例)
上記第1の実施の形態の固体撮像装置1では、素子形成基板21に対し、チップ30の対向面32Sが回路基板10の対向面12Sよりも保護層40の厚さの分だけ突出している場合を説明した。しかしながら、本開示では、例えば図3に示した固体撮像装置1Aのように、素子形成基板21に対し、チップ30Aの対向面32Sが回路基板10の対向面12Sよりも凹んでいてもよい。すなわち、Z軸方向において、チップ30Aの対向面32Sと素子形成基板21との間隔が、中間部材112と素子形成基板21との間隔よりも広くなっている。但し、固体撮像装置1Aのチップ30Aは、端子部33の代わりに端子部35を有している。端子部35は、回路形成層32の対向面32Sおよび回路基板10の対向面12Sの双方よりも突出した表面35Sを含んでいる。なお、図3は、第1の実施の形態の第1変形例(以下、変形例1という。)に係る固体撮像装置1Aの全体構成例を表す断面図である。 [1.4. Modification]
(Overall configuration example)
In the solid-
(製造方法)
続いて、図4A~図4Fを参照して、変形例1の固体撮像装置1Aの製造方法について説明する。図4A~図4Fは、固体撮像装置1Aの製造方法の一工程をそれぞれ表す断面図であり、図1Aに対応するものである。 (Production method)
Next, a method for manufacturing the solid-state imaging device 1A of Modification 1 will be described with reference to FIGS. 4A to 4F. 4A to 4F are cross-sectional views respectively showing one step of the manufacturing method of the solid-state imaging device 1A, corresponding to FIG. 1A.
続いて、図4A~図4Fを参照して、変形例1の固体撮像装置1Aの製造方法について説明する。図4A~図4Fは、固体撮像装置1Aの製造方法の一工程をそれぞれ表す断面図であり、図1Aに対応するものである。 (Production method)
Next, a method for manufacturing the solid-
まず、上記第1の実施の形態の固体撮像装置1の製造方法と同様にして、図2A~図2Cに示した工程を順次行う。
First, the steps shown in FIGS. 2A to 2C are sequentially performed in the same manner as in the manufacturing method of the solid-state imaging device 1 of the first embodiment.
次に、図4Aに示したように、凹部10Uにチップ30を載置する。その際、例えばチップ30の基板31の裏面などに樹脂接着剤を塗布し、チップ30を凹部10Uに接着して固定するようにしてもよい。なお、チップ30は、上記第1の実施の形態のチップ30と実質的に同じものである。変形例1-1では、図4Aに示したように、凹部10Uにチップ30を載置した段階で、チップ30の上面30Sが絶縁膜12の対向面12Sよりも下方へ、すなわち支持基板111に近づく方向にリセスした状態となっている。
Next, as shown in FIG. 4A, the chip 30 is placed in the recess 10U. At this time, for example, a resin adhesive may be applied to the back surface of the substrate 31 of the chip 30 to adhere and fix the chip 30 to the concave portion 10U. Note that the chip 30 is substantially the same as the chip 30 of the first embodiment. In modification 1-1, as shown in FIG. 4A, when the chip 30 is placed in the recess 10U, the upper surface 30S of the chip 30 is positioned below the facing surface 12S of the insulating film 12, that is, on the support substrate 111. It is in a recessed state in the approaching direction.
次に、図4Bに示したように、回路基板10と、凹部10Uに載置されたチップ30との全体を覆うように保護膜40Zを形成する。保護膜40Zは、例えば塗布法により形成することができる。
Next, as shown in FIG. 4B, a protective film 40Z is formed to cover the entire circuit board 10 and the chip 30 placed in the recess 10U. The protective film 40Z can be formed by, for example, a coating method.
次に、例えば化学機械研磨(CMP)により保護膜40Zを研磨しつつ平坦化し、図4Cに示したように、保護層40を得る。その際、チップ30の端子部33の表面33Sは保護層40に覆われた状態とする。また、絶縁膜12の対向面12Sも露出せずに保護層40により覆われた状態であってもよい。
Next, the protective film 40Z is polished and planarized by chemical mechanical polishing (CMP), for example, to obtain the protective layer 40 as shown in FIG. 4C. At that time, the surface 33S of the terminal portion 33 of the chip 30 is covered with the protective layer 40. Next, as shown in FIG. Also, the facing surface 12S of the insulating film 12 may be covered with the protective layer 40 without being exposed.
次に、図4Dに示したように、保護層40を選択的に覆うレジストマスクRM2を、例えばフォトリソグラフィ法により形成する。レジストマスクRM2は、端子部33と対応する位置に開口K2を有している。続いて、レジストマスクRM2を用い、例えばドライエッチングを行う。その際、開口K2に露出した保護層40を選択的にエッチングする。レジストマスクRM2を用いたエッチング処理により、保護層40に開口K40が形成され、端子部33が露出する。
Next, as shown in FIG. 4D, a resist mask RM2 that selectively covers the protective layer 40 is formed by photolithography, for example. The resist mask RM2 has openings K2 at positions corresponding to the terminal portions 33 . Subsequently, dry etching, for example, is performed using a resist mask RM2. At that time, the protective layer 40 exposed in the opening K2 is selectively etched. An opening K40 is formed in the protective layer 40 by etching using the resist mask RM2, and the terminal portion 33 is exposed.
次に、図4Eに示したように、レジストマスクRM2を除去したのち、例えばめっき処理を行うことで端子部33の上に金属膜34を形成する。金属膜34は、端子部33と同じ材料、例えばCuにより形成される。金属膜34を形成したのち、平坦化処理を行うようにしてもよい。金属膜34の形成により、端子部33および金属膜34からなる端子部35が得られる。これにより、基板31と回路形成層32と、端子部35とを含むチップ30Aが完成する。端子部35は、表面35Sを含んでいる。保護層40の表面40Sは、表面35Sと共通平面を形成している。
Next, as shown in FIG. 4E, after removing the resist mask RM2, a metal film 34 is formed on the terminal portion 33 by, for example, plating. The metal film 34 is made of the same material as the terminal portion 33, such as Cu. After forming the metal film 34, a planarization process may be performed. By forming the metal film 34, the terminal portion 35 composed of the terminal portion 33 and the metal film 34 is obtained. As a result, the chip 30A including the substrate 31, the circuit forming layer 32, and the terminal portion 35 is completed. The terminal portion 35 includes a surface 35S. Surface 40S of protective layer 40 forms a common plane with surface 35S.
次に、図4Fに示したように、構造体20Zを用意する。構造体20Zは、光電変換部25を含む素子形成基板21に配線層22が積層されたものである。配線層22には端子部23が設けられている。端子部23の表面23Sは、対向面22Sに露出している。ここで、構造体20Zの対向面22Sと、回路基板10に設けられた保護層40およびチップ30の対向面32Sとが対向した状態で、構造体20Zと回路基板10とのXY面内における位置合わせを行う。そののち、構造体20Zと回路基板10との貼り合わせを行う。ここでは、チップ30Aの端子部35の表面35Sとセンサ基板20の端子部23の表面23Sとを例えばCu-Cu接合する。これにより、端子部35と端子部23とが一体化されてなるコンタクトプラグCP2が得られる。
Next, as shown in FIG. 4F, a structure 20Z is prepared. The structural body 20Z is obtained by laminating a wiring layer 22 on an element forming substrate 21 including a photoelectric conversion portion 25 . A terminal portion 23 is provided on the wiring layer 22 . A surface 23S of the terminal portion 23 is exposed to the facing surface 22S. Here, in a state in which the facing surface 22S of the structural body 20Z faces the protective layer 40 provided on the circuit board 10 and the facing surface 32S of the chip 30, the position of the structural body 20Z and the circuit board 10 in the XY plane is determined. Align. After that, the structure 20Z and the circuit board 10 are bonded together. Here, the surface 35S of the terminal portion 35 of the chip 30A and the surface 23S of the terminal portion 23 of the sensor substrate 20 are bonded by Cu--Cu, for example. Thereby, the contact plug CP2 in which the terminal portion 35 and the terminal portion 23 are integrated is obtained.
次に、構造体20Zの素子形成基板21を薄肉化する。最後に、薄肉化された素子形成基板21の上に、複数のカラーフィルタ26と複数のオンチップレンズ27とをそれぞれ積層することにより固体撮像素子24を形成する。これにより、センサ基板20を得る(図3参照)。
Next, the element forming substrate 21 of the structure 20Z is thinned. Finally, a plurality of color filters 26 and a plurality of on-chip lenses 27 are laminated on the thinned device forming substrate 21 to form the solid-state imaging device 24 . Thus, the sensor substrate 20 is obtained (see FIG. 3).
(作用効果)
変形例1では、例えば端子部33の上に追加の金属膜34を形成することで得られる端子部35を有するようにしている。端子部35は、対向面32Sおよび対向面12Sの双方よりも突出した表面35Sを含んでいる。したがって、例えばCMPにより、複数の端子部35の高さを容易に揃えることができる。よって、より高い寸法精度を有する固体撮像装置1Aを実現することができる。 (Effect)
Modification 1 has a terminal portion 35 obtained by forming an additional metal film 34 on the terminal portion 33, for example. The terminal portion 35 includes a surface 35S protruding from both the facing surface 32S and the facing surface 12S. Therefore, the heights of the plurality of terminal portions 35 can be easily aligned by, for example, CMP. Therefore, the solid-state imaging device 1A having higher dimensional accuracy can be realized.
変形例1では、例えば端子部33の上に追加の金属膜34を形成することで得られる端子部35を有するようにしている。端子部35は、対向面32Sおよび対向面12Sの双方よりも突出した表面35Sを含んでいる。したがって、例えばCMPにより、複数の端子部35の高さを容易に揃えることができる。よって、より高い寸法精度を有する固体撮像装置1Aを実現することができる。 (Effect)
<2.第2の実施形態>
[2.1.構成例]
続いて、図5を参照して、本開示の第2の実施形態としての固体撮像装置2について説明する。上記第1の実施の形態の固体撮像装置1は、支持基板111および中間部材112が一体化してなる支持体11を有する回路基板10を備えるようにした。しかしながら、本開示では、支持基板111と中間部材112とが別体であってもよい。具体的には、図5に示した固体撮像装置2のように、支持基板111と中間部材112とが離間していれもよい。なお、図5は、本開示の第2の実施の形態に係る固体撮像装置2の全体構成例を表す断面図である。 <2. Second Embodiment>
[2.1. Configuration example]
Subsequently, a solid-state imaging device 2 as a second embodiment of the present disclosure will be described with reference to FIG. The solid-state imaging device 1 of the first embodiment is provided with the circuit board 10 having the support 11 formed by integrating the support substrate 111 and the intermediate member 112 . However, in the present disclosure, the support substrate 111 and the intermediate member 112 may be separate bodies. Specifically, like the solid-state imaging device 2 shown in FIG. 5, the support substrate 111 and the intermediate member 112 may be separated from each other. Note that FIG. 5 is a cross-sectional view showing an overall configuration example of the solid-state imaging device 2 according to the second embodiment of the present disclosure.
[2.1.構成例]
続いて、図5を参照して、本開示の第2の実施形態としての固体撮像装置2について説明する。上記第1の実施の形態の固体撮像装置1は、支持基板111および中間部材112が一体化してなる支持体11を有する回路基板10を備えるようにした。しかしながら、本開示では、支持基板111と中間部材112とが別体であってもよい。具体的には、図5に示した固体撮像装置2のように、支持基板111と中間部材112とが離間していれもよい。なお、図5は、本開示の第2の実施の形態に係る固体撮像装置2の全体構成例を表す断面図である。 <2. Second Embodiment>
[2.1. Configuration example]
Subsequently, a solid-
図5に示したように、固体撮像装置2は、回路基板10の代わりに回路基板50を備えている点が固体撮像装置1と異なる。回路基板50は、例えば、支持基板111と、絶縁膜12~14と、チップ30と、中間部材112とを有する。絶縁膜12は、支持基板111の上面を全面的に覆うようにXY面内に広がっている。チップ30は、絶縁膜12の上に配置されている。中間部材112は、支持基板111の上に、絶縁膜14と絶縁膜13とを介して配置されている。中間部材112とチップ30とは、XY面内において隣り合うように設けられている。中間部材112は、絶縁膜13を介してチップ30の端面30Tと接している。絶縁膜13,14は、絶縁膜12と同様、例えば酸化シリコン(SiOx)や窒化シリコン(SiNx)などの無機酸化物によって形成されている。
As shown in FIG. 5, the solid-state imaging device 2 is different from the solid-state imaging device 1 in that it includes a circuit board 50 instead of the circuit board 10 . The circuit board 50 has, for example, a support substrate 111, insulating films 12 to 14, a chip 30, and an intermediate member 112. As shown in FIG. The insulating film 12 extends in the XY plane so as to entirely cover the upper surface of the support substrate 111 . The chip 30 is arranged on the insulating film 12 . The intermediate member 112 is arranged on the support substrate 111 with the insulating films 14 and 13 interposed therebetween. The intermediate member 112 and the chip 30 are provided adjacent to each other in the XY plane. The intermediate member 112 is in contact with the end face 30T of the chip 30 via the insulating film 13 . Like the insulating film 12, the insulating films 13 and 14 are made of inorganic oxides such as silicon oxide (SiOx) and silicon nitride (SiNx).
固体撮像装置2では、センサ基板20の対向面20Sと、回路基板50の対向面50Sとが接合されている。センサ基板20の対向面20Sには、配線層22の対向面22Sおよび端子部23の表面23Sが含まれている。回路基板50の対向面50Sには、中間部材112の表面112S、回路形成層32の対向面32S、および端子部33の表面33Sが含まれている。
In the solid-state imaging device 2, the facing surface 20S of the sensor substrate 20 and the facing surface 50S of the circuit board 50 are joined. The facing surface 20S of the sensor substrate 20 includes the facing surface 22S of the wiring layer 22 and the surface 23S of the terminal portion 23 . The facing surface 50</b>S of the circuit board 50 includes the surface 112</b>S of the intermediate member 112 , the facing surface 32</b>S of the circuit forming layer 32 , and the surface 33</b>S of the terminal portion 33 .
[2.2.製造方法]
続いて、図6A~図6Iを参照して、本実施形態に係る固体撮像装置2の製造方法について説明する。図6A~図6Iは、固体撮像装置2の製造方法の一工程をそれぞれ表す断面図であり、図5に対応するものである。 [2.2. Production method]
Next, a method for manufacturing the solid-state imaging device 2 according to this embodiment will be described with reference to FIGS. 6A to 6I. 6A to 6I are cross-sectional views showing one step of the manufacturing method of the solid-state imaging device 2, respectively, and correspond to FIG.
続いて、図6A~図6Iを参照して、本実施形態に係る固体撮像装置2の製造方法について説明する。図6A~図6Iは、固体撮像装置2の製造方法の一工程をそれぞれ表す断面図であり、図5に対応するものである。 [2.2. Production method]
Next, a method for manufacturing the solid-
まず、図6Aに示したように、Si基板などの半導体基板112Zを用意したのち、半導体基板112Zの上面にレジストマスクRM3を形成する。例えばフォトリソグラフィ法により、レジストマスクRM3には、チップ30を収容するための凹部112Uを形成すべき領域と対応する領域に開口K3を形成する。
First, as shown in FIG. 6A, after preparing a semiconductor substrate 112Z such as a Si substrate, a resist mask RM3 is formed on the upper surface of the semiconductor substrate 112Z. For example, by photolithography, the resist mask RM3 is formed with an opening K3 in a region corresponding to the region where the recess 112U for housing the chip 30 is to be formed.
次に、図6Bに示したように、半導体基板112Zに凹部112Uを形成する。具体的には、半導体基板112Zのうち、レジストマスクRM3により覆われていない部分、すなわち開口K3と対応する部分を、例えばドライエッチングにより掘り下げる。
Next, as shown in FIG. 6B, recesses 112U are formed in the semiconductor substrate 112Z. Specifically, the portion of the semiconductor substrate 112Z that is not covered with the resist mask RM3, that is, the portion corresponding to the opening K3 is dug down by dry etching, for example.
次に、レジストマスクRM3を除去したのち、図6Cに示したように、半導体基板112Zの全体を覆うように絶縁膜13を形成する。絶縁膜13は、例えばスパッタリング法やCVD法により形成することができる。その際、凹部112Uの形状をできるだけ維持するように、絶縁膜13をコンフォーマルに形成する。
Next, after removing the resist mask RM3, an insulating film 13 is formed to cover the entire semiconductor substrate 112Z, as shown in FIG. 6C. The insulating film 13 can be formed by, for example, a sputtering method or a CVD method. At that time, the insulating film 13 is conformally formed so as to maintain the shape of the concave portion 112U as much as possible.
次に、図6Dに示したように、凹部112Uにチップ30を載置する。その際、例えばチップ30の上面30Sを凹部112Uに向け、上面30Sに樹脂接着剤を塗布し、チップ30を凹部112Uに接着して固定するようにしてもよい。図6Dに示したように、凹部112Uにチップ30を載置した段階では、チップ30の裏面が絶縁膜13の上面よりも上方へ突出した状態となっている。
Next, as shown in FIG. 6D, the chip 30 is placed in the recess 112U. At this time, for example, the upper surface 30S of the chip 30 may face the recess 112U, and a resin adhesive may be applied to the upper surface 30S to adhere and fix the chip 30 to the recess 112U. As shown in FIG. 6D, when the chip 30 is placed in the concave portion 112U, the rear surface of the chip 30 protrudes upward from the upper surface of the insulating film 13. As shown in FIG.
次に、図6Eに示したように、絶縁膜13と、凹部112Uに載置されたチップ30との全体を覆うように絶縁膜14Zを形成する。絶縁膜14Zは、例えば塗布法により形成することができる。
Next, as shown in FIG. 6E, an insulating film 14Z is formed so as to entirely cover the insulating film 13 and the chip 30 placed in the recess 112U. The insulating film 14Z can be formed by, for example, a coating method.
次に、例えば化学機械研磨(CMP)により絶縁膜14Zを研磨しつつ平坦化し、図6Fに示したように、絶縁膜14を得る。その際、例えば、チップ30の基板31の裏面が露出するまでCMPを行う。その結果、絶縁膜14の表面および基板31の裏面を含む対向面31Sが形成される。
Next, the insulating film 14Z is polished and planarized by chemical mechanical polishing (CMP), for example, to obtain the insulating film 14 as shown in FIG. 6F. At that time, for example, CMP is performed until the back surface of the substrate 31 of the chip 30 is exposed. As a result, a facing surface 31S including the front surface of the insulating film 14 and the rear surface of the substrate 31 is formed.
次に、図6Gに示したように、構造体50Zを用意する。構造体50Zは、半導体基板である支持基板111に絶縁膜12が積層されたものである。続いて、構造体50Zを、対向面31Sと貼り合わせる。
Next, as shown in FIG. 6G, a structure 50Z is prepared. The structural body 50Z is obtained by laminating an insulating film 12 on a support substrate 111 which is a semiconductor substrate. Subsequently, the structure 50Z is attached to the facing surface 31S.
次に、図6Hに示したように、半導体基板112Zを、構造体50Zと反対側から例えば化学機械研磨(CMP)により研磨し、チップ30の上面30Sが露出するまで薄肉化する。その結果、中間部材112が形成され、回路基板50が完成する。
Next, as shown in FIG. 6H, the semiconductor substrate 112Z is polished by, for example, chemical mechanical polishing (CMP) from the side opposite to the structure 50Z, and thinned until the upper surface 30S of the chip 30 is exposed. As a result, the intermediate member 112 is formed and the circuit board 50 is completed.
次に、図6Iに示したように、構造体20Zを用意する。構造体20Zは、光電変換部25を含む素子形成基板21に配線層22が積層されたものである。配線層22には端子部23が設けられている。端子部23の表面23Sは、対向面22Sに露出している。ここで、構造体20Zの対向面22Sと、回路基板50の対向面50Sとが対向した状態で、構造体20Zと回路基板50とのXY面内における位置合わせを行う。そののち、構造体20Zと回路基板50との貼り合わせを行う。ここでは、チップ30の端子部33の表面33Sとセンサ基板20の端子部23の表面23Sとを例えばCu-Cu接合する。これにより、端子部33と端子部23とが一体化されてなるコンタクトプラグCP2が得られる。
Next, as shown in FIG. 6I, a structure 20Z is prepared. The structural body 20Z is obtained by laminating a wiring layer 22 on an element forming substrate 21 including a photoelectric conversion portion 25 . A terminal portion 23 is provided on the wiring layer 22 . A surface 23S of the terminal portion 23 is exposed to the facing surface 22S. Here, the structural body 20Z and the circuit board 50 are aligned in the XY plane with the facing surface 22S of the structural body 20Z and the facing surface 50S of the circuit board 50 facing each other. After that, the structure 20Z and the circuit board 50 are bonded together. Here, the surface 33S of the terminal portion 33 of the chip 30 and the surface 23S of the terminal portion 23 of the sensor substrate 20 are bonded by Cu--Cu, for example. Thereby, the contact plug CP2 in which the terminal portion 33 and the terminal portion 23 are integrated is obtained.
次に、構造体20Zの素子形成基板21を薄肉化する。最後に、薄肉化された素子形成基板21の上に、複数のカラーフィルタ26と複数のオンチップレンズ27とをそれぞれ積層することにより固体撮像素子24を形成する。これにより、センサ基板20を得る(図5参照)。
Next, the element forming substrate 21 of the structure 20Z is thinned. Finally, a plurality of color filters 26 and a plurality of on-chip lenses 27 are laminated on the thinned device forming substrate 21 to form the solid-state imaging device 24 . Thus, the sensor substrate 20 is obtained (see FIG. 5).
以上の工程により、固体撮像装置2が完成する。
The solid-state imaging device 2 is completed through the above steps.
[2.3.作用効果]
本実施の形態の固体撮像装置2においても、上記第1の実施の形態の固体撮像装置1と同様の効果が期待できる。さらに本実施の形態の固体撮像装置2では、支持基板111と中間部材112とが離間している。このため、Z軸方向において、中間部材112の表面112Sの位置と、回路形成層32の対向面32S、および端子部33の表面33Sの位置とを一致させるように製造することができる。よって、より高い寸法精度を有する固体撮像装置2を実現することができる。 [2.3. Action effect]
Also in the solid-state imaging device 2 of this embodiment, the same effects as those of the solid-state imaging device 1 of the first embodiment can be expected. Furthermore, in the solid-state imaging device 2 of this embodiment, the support substrate 111 and the intermediate member 112 are separated. Therefore, the surface 112S of the intermediate member 112 can be aligned with the facing surface 32S of the circuit forming layer 32 and the surface 33S of the terminal portion 33 in the Z-axis direction. Therefore, a solid-state imaging device 2 having higher dimensional accuracy can be realized.
本実施の形態の固体撮像装置2においても、上記第1の実施の形態の固体撮像装置1と同様の効果が期待できる。さらに本実施の形態の固体撮像装置2では、支持基板111と中間部材112とが離間している。このため、Z軸方向において、中間部材112の表面112Sの位置と、回路形成層32の対向面32S、および端子部33の表面33Sの位置とを一致させるように製造することができる。よって、より高い寸法精度を有する固体撮像装置2を実現することができる。 [2.3. Action effect]
Also in the solid-
<3.電子機器への適用例>
図7は、本技術を適用した電子機器としてのカメラ2000の構成例を示すブロック図である。 <3. Examples of application to electronic devices>
FIG. 7 is a block diagram showing a configuration example of acamera 2000 as an electronic device to which the present technology is applied.
図7は、本技術を適用した電子機器としてのカメラ2000の構成例を示すブロック図である。 <3. Examples of application to electronic devices>
FIG. 7 is a block diagram showing a configuration example of a
カメラ2000は、レンズ群などからなる光学部2001、上述の固体撮像装置1,1A~1C,2,2Aなど(以下、固体撮像装置1等という。)が適用される撮像装置(撮像デバイス)2002、およびカメラ信号処理回路であるDSP(Digital Signal Processor)回路2003を備える。また、カメラ2000は、フレームメモリ2004、表示部2005、記録部2006、操作部2007、および電源部2008も備える。DSP回路2003、フレームメモリ2004、表示部2005、記録部2006、操作部2007および電源部2008は、バスライン2009を介して相互に接続されている。
A camera 2000 includes an optical unit 2001 including a group of lenses and the like, and an imaging apparatus (imaging device) 2002 to which the above-described solid- state imaging devices 1, 1A to 1C, 2, 2A (hereinafter referred to as the solid-state imaging device 1 and the like) are applied. , and a DSP (Digital Signal Processor) circuit 2003 which is a camera signal processing circuit. The camera 2000 also includes a frame memory 2004 , a display section 2005 , a recording section 2006 , an operation section 2007 and a power supply section 2008 . DSP circuit 2003 , frame memory 2004 , display unit 2005 , recording unit 2006 , operation unit 2007 and power supply unit 2008 are interconnected via bus line 2009 .
光学部2001は、被写体からの入射光(像光)を取り込んで撮像装置2002の撮像面上に結像する。撮像装置2002は、光学部2001によって撮像面上に結像された入射光の光量を画素単位で電気信号に変換して画素信号として出力する。
An optical unit 2001 captures incident light (image light) from a subject and forms an image on an imaging surface of an imaging device 2002 . The imaging device 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electric signal for each pixel, and outputs the electric signal as a pixel signal.
表示部2005は、例えば、液晶パネルや有機ELパネル等のパネル型表示装置からなり、撮像装置2002で撮像された動画または静止画を表示する。記録部2006は、撮像装置2002で撮像された動画または静止画を、ハードディスクや半導体メモリ等の記録媒体に記録する。
The display unit 2005 is composed of, for example, a panel type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 2002 . A recording unit 2006 records a moving image or still image captured by the imaging device 2002 in a recording medium such as a hard disk or a semiconductor memory.
操作部2007は、ユーザによる操作の下に、カメラ2000が持つ様々な機能について操作指令を発する。電源部2008は、DSP回路2003、フレームメモリ2004、表示部2005、記録部2006および操作部2007の動作電源となる各種の電源を、これら供給対象に対して適宜供給する。
The operation unit 2007 issues operation commands for various functions of the camera 2000 under the user's operation. A power supply unit 2008 appropriately supplies various power supplies as operating power supplies for the DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, and the operation unit 2007 to these supply targets.
上述したように、撮像装置2002として、上述した固体撮像装置1等を用いることで、良好な画像の取得が期待できる。
As described above, by using the above-described solid-state imaging device 1 or the like as the imaging device 2002, acquisition of good images can be expected.
<4.移動体への応用例>
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <4. Example of application to moving objects>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 <4. Example of application to moving objects>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
図8は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。
FIG. 8 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
車両制御システム12000は、通信ネットワーク12001を介して接続された複数の電子制御ユニットを備える。図9に示した例では、車両制御システム12000は、駆動系制御ユニット12010、ボディ系制御ユニット12020、車外情報検出ユニット12030、車内情報検出ユニット12040、及び統合制御ユニット12050を備える。また、統合制御ユニット12050の機能構成として、マイクロコンピュータ12051、音声画像出力部12052、及び車載ネットワークI/F(Interface)12053が図示されている。
A vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 9, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
駆動系制御ユニット12010は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット12010は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。
The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
ボディ系制御ユニット12020は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット12020は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット12020には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット12020は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。
The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
車外情報検出ユニット12030は、車両制御システム12000を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット12030には、撮像部12031が接続される。車外情報検出ユニット12030は、撮像部12031に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット12030は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。
The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
撮像部12031は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部12031は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部12031が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。
The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
車内情報検出ユニット12040は、車内の情報を検出する。車内情報検出ユニット12040には、例えば、運転者の状態を検出する運転者状態検出部12041が接続される。運転者状態検出部12041は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット12040は、運転者状態検出部12041から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。
The in-vehicle information detection unit 12040 detects in-vehicle information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット12010に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むADAS(Advanced Driver Assistance System)の機能実現を目的とした協調制御を行うことができる。
The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of
また、マイクロコンピュータ12051は、車外情報検出ユニット12030又は車内情報検出ユニット12040で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。
In addition, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
また、マイクロコンピュータ12051は、車外情報検出ユニット12030で取得される車外の情報に基づいて、ボディ系制御ユニット12020に対して制御指令を出力することができる。例えば、マイクロコンピュータ12051は、車外情報検出ユニット12030で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。
Also, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
音声画像出力部12052は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図12の例では、出力装置として、オーディオスピーカ12061、表示部12062及びインストルメントパネル12063が例示されている。表示部12062は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。
The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 12, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.
図9は、撮像部12031の設置位置の例を示す図である。
FIG. 9 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.
図10では、撮像部12031として、撮像部12101、12102、12103、12104、12105を有する。
In FIG. 10, the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
撮像部12101、12102、12103、12104、12105は、例えば、車両12100のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部12101及び車室内のフロントガラスの上部に備えられる撮像部12105は、主として車両12100の前方の画像を取得する。サイドミラーに備えられる撮像部12102、12103は、主として車両12100の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部12104は、主として車両12100の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部12105は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。
The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 . Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
なお、図9には、撮像部12101ないし12104の撮影範囲の一例が示されている。撮像範囲12111は、フロントノーズに設けられた撮像部12101の撮像範囲を示し、撮像範囲12112,12113は、それぞれサイドミラーに設けられた撮像部12102,12103の撮像範囲を示し、撮像範囲12114は、リアバンパ又はバックドアに設けられた撮像部12104の撮像範囲を示す。例えば、撮像部12101ないし12104で撮像された画像データが重ね合わせられることにより、車両12100を上方から見た俯瞰画像が得られる。
Note that FIG. 9 shows an example of the imaging range of the imaging units 12101 to 12104. FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
撮像部12101ないし12104の少なくとも1つは、距離情報を取得する機能を有していてもよい。例えば、撮像部12101ないし12104の少なくとも1つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。
At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を基に、撮像範囲12111ないし12114内における各立体物までの距離と、この距離の時間的変化(車両12100に対する相対速度)を求めることにより、特に車両12100の進行路上にある最も近い立体物で、車両12100と略同じ方向に所定の速度(例えば、0km/h以上)で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ12051は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御(追従停止制御も含む)や自動加速制御(追従発進制御も含む)等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。
For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
例えば、マイクロコンピュータ12051は、撮像部12101ないし12104から得られた距離情報を元に、立体物に関する立体物データを、2輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ12051は、車両12100の周辺の障害物を、車両12100のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ12051は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ12061や表示部12062を介してドライバに警報を出力することや、駆動系制御ユニット12010を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。
For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
撮像部12101ないし12104の少なくとも1つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ12051は、撮像部12101ないし12104の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部12101ないし12104の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ12051が、撮像部12101ないし12104の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部12052は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部12062を制御する。また、音声画像出力部12052は、歩行者を示すアイコン等を所望の位置に表示するように表示部12062を制御してもよい。
At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、撮像部12031に適用され得る。具体的には、図1Aなどに示した固体撮像装置1等を撮像部12031に適用することができる。撮像部12031に本開示に係る技術を適用することにより、車両制御システムの優れた動作が期待できる。
An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the solid-state imaging device 1 or the like shown in FIG. 1A or the like can be applied to the imaging unit 12031 . By applying the technology according to the present disclosure to the imaging unit 12031, excellent operation of the vehicle control system can be expected.
<5.その他の変形例>
以上、いくつかの実施の形態および変形例を挙げて、本開示にかかる技術を説明した。ただし、本開示にかかる技術は、上記実施の形態等に限定されるわけではなく、種々の変形が可能である。 <5. Other modified examples>
The technology according to the present disclosure has been described above with reference to several embodiments and modifications. However, the technology according to the present disclosure is not limited to the above embodiments and the like, and various modifications are possible.
以上、いくつかの実施の形態および変形例を挙げて、本開示にかかる技術を説明した。ただし、本開示にかかる技術は、上記実施の形態等に限定されるわけではなく、種々の変形が可能である。 <5. Other modified examples>
The technology according to the present disclosure has been described above with reference to several embodiments and modifications. However, the technology according to the present disclosure is not limited to the above embodiments and the like, and various modifications are possible.
例えば、上記第1の実施の形態では、固体撮像装置1は回路基板10にセンサ基板20を積層した構造を備えているが、本開示はこれに限定されるものではない。例えば、図10に示した第2変形例としての固体撮像装置3のように、3つ以上の基板を積層したものであってもよい。図10の固体撮像装置3では、回路基板10とセンサ基板20との間に、他の回路基板60をさらに挿入するようにしたものである。
For example, in the first embodiment, the solid-state imaging device 1 has a structure in which the sensor substrate 20 is laminated on the circuit board 10, but the present disclosure is not limited to this. For example, like a solid-state imaging device 3 as a second modified example shown in FIG. 10, three or more substrates may be laminated. In the solid-state imaging device 3 of FIG. 10, another circuit board 60 is further inserted between the circuit board 10 and the sensor board 20 .
また、例えば、上記第1の実施の形態の固体撮像装置1では、チップ30の端面30Tが絶縁膜12を介して中間部材112と接触するようにしたが、本開示はこれに限定されるものではない。例えば図11に示した第3変形例としての固体撮像装置4のように、チップ30の端面30Tと凹部10Uの側壁との間に空間が設けられていてもよい。あるいは、図12に示した第4変形例としての固体撮像装置5のように、チップ30の端面30Tと凹部10Uの側壁との隙間に保護層40が充填されていてもよい。
Further, for example, in the solid-state imaging device 1 of the first embodiment, the end face 30T of the chip 30 is brought into contact with the intermediate member 112 through the insulating film 12, but the present disclosure is limited to this. is not. For example, like a solid-state imaging device 4 as a third modified example shown in FIG. 11, a space may be provided between the end surface 30T of the chip 30 and the side wall of the recess 10U. Alternatively, like a solid-state imaging device 5 as a fourth modified example shown in FIG. 12, a protective layer 40 may be filled in the gap between the end surface 30T of the chip 30 and the side wall of the recess 10U.
さらに、各実施形態で説明した構成および動作の全てが本開示の構成および動作として必須であるとは限らない。たとえば、各実施形態における構成要素のうち、本開示の最上位概念を示す独立請求項に記載されていない構成要素は、任意の構成要素として理解されるべきである。
Furthermore, not all the configurations and operations described in each embodiment are essential as the configurations and operations of the present disclosure. For example, among the components in each embodiment, components not described in an independent claim indicating the top concept of the present disclosure should be understood as optional components.
本明細書および添付の特許請求の範囲全体で使用される用語は、「限定的でない」用語と解釈されるべきである。例えば、「含む」または「含まれる」という用語は、「含まれるとして記載された様態に限定されない」と解釈されるべきである。「有する」という用語は、「有するとして記載された様態に限定されない」と解釈されるべきである。
Terms used throughout this specification and the appended claims should be interpreted as "non-limiting" terms. For example, the terms "including" or "included" should be interpreted as "not limited to the manner in which inclusion is stated." The term "having" should be interpreted as "not limited to the manner in which it is stated to have".
本明細書で使用した用語には、単に説明の便宜のために用いており、構成及び動作を限定する目的で使用したわけではない用語が含まれる。たとえば、「右」、「左」、「上」、「下」などの用語は、参照している図面上での方向を示しているにすぎない。また、「内側」、「外側」という用語は、それぞれ、注目要素の中心に向かう方向、注目要素の中心から離れる方向を示しているにすぎない。これらに類似する用語や同様の趣旨の用語についても同様である。
The terms used in this specification include terms that are used merely for the convenience of explanation and are not used for the purpose of limiting the configuration and operation. For example, terms such as "right", "left", "upper", and "lower" merely indicate directions in the drawings to which reference is made. Also, the terms "inner" and "outer" merely indicate directions toward and away from the center of the element of interest, respectively. The same applies to terms similar to these and terms with a similar meaning.
なお、本開示にかかる技術は、以下のような構成を取ることも可能である。以下の構成を備える本開示の固体撮像装置では、中間部材が第1基板と第2基板との隙間に、第1方向と直交する面内方向においてチップと隣り合うように設けられている。このため、例えば第1基板と第2基板と隙間にチップを覆うように設けられる保護層の厚さが薄くてすむ。その結果、良好な撮像性能を有しつつ、薄型化に適した構造が実現できる。
なお、本開示にかかる技術が奏する効果は、ここに記載された効果に必ずしも限定されるわけではなく、本開示中に記載されたいずれの効果であってもよい。
(1)
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向するように配置される第2基板と、
前記第1基板と前記第2基板との間に設けられると共に前記画素信号の信号処理を行う回路を有するチップと、
前記第1基板と前記第2基板との隙間に位置し、前記第1方向と直交する面内方向において前記チップと隣り合うように設けられた中間部材と
を備える撮像装置。
(2)
前記中間部材は、前記面内方向において絶縁膜を介して前記チップと接している
上記(1)記載の撮像装置。
(3)
前記チップを覆うように前記第1基板と前記第2基板との隙間に充填される保護層をさらに備える
上記(1)または(2)に記載の撮像装置。
(4)
前記中間部材は、前記保護層の第1熱伝導率よりも高い第2熱伝導率を有する
上記(3)記載の撮像装置。
(5)
前記第2基板と前記中間部材とは一体化されている
上記(1)から(4)のいずれか1つに記載の撮像装置。
(6)
前記第2基板の構成材料および前記中間部材の構成材料は、互いに実質的に同じである
上記(1)から(5)のいずれか1つに記載の撮像装置。
(7)
前記第2基板の構成材料および前記中間部材の構成材料は、いずれも珪素(Si)である
上記(1)から(6)のいずれか1つに記載の撮像装置。
(8)
前記チップは、
第3基板と、
前記第3基板上に設けられる回路形成層と、
前記回路形成層に設けられる端子部と
を有する
上記(1)から(7)のいずれか1つに記載の撮像装置。
(9)
前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔と実質的に等しい
上記(1)から(8)のいずれか1つに記載の撮像装置。
(10)
前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔よりも狭い
上記(1)から(8)のいずれか1つに記載の撮像装置。
(11)
前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔よりも広い
上記(1)から(8)のいずれか1つに記載の撮像装置。
(12)
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向する凹部を有する第2基板と、
前記第1基板と前記第2基板との間に位置し、前記第1方向の一部または全部が前記凹部に収容され、前記画素信号の信号処理を行う回路を有するチップと
を備える撮像装置。
(13)
前記チップを覆うように前記第1基板と前記第2基板との隙間に充填される保護層をさらに備える
上記(12)記載の撮像装置。
(14)
前記中間部材は、前記保護層の第1熱伝導率よりも高い第2熱伝導率を有する
上記(13)記載の撮像装置。
(15)
前記凹部の側壁と前記チップの端面とが離間している
上記(12)記載の撮像装置。
(16)
画素信号を生成可能な撮像素子を有する第1基板と、第2基板と、前記画素信号の信号処理を行う回路を有するチップとを用意することと、
前記第2基板に収容部を形成することと、
前記収容部に前記チップを配置することと、
前記第2基板および前記チップを覆うように保護層を形成することと、
前記第2基板との間に前記チップを挟持するように、前記第2基板に前記第1基板を接合することと
を含む
撮像装置の製造方法。
(17)
前記保護層を平坦化することをさらに含む
上記(16)記載の撮像装置の製造方法。
(18)
前記チップは、第3基板と、前記第3基板上に設けられた絶縁層と、前記絶縁層に埋設された配線とを有し、
前記保護層を平坦化することにより、前記配線を前記絶縁層から露出させる
上記(16)記載の撮像装置の製造方法。
(19)
撮像装置を備え、
前記撮像装置は、
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向するように配置される第2基板と、
前記第1基板と前記第2基板との間に設けられると共に前記画素信号の信号処理を行う回路を有するチップと、
前記第1基板と前記第2基板との隙間に位置し、前記第1方向と直交する面内方向において前記チップと隣り合うように設けられた中間部材と
を備える電子機器。 Note that the technology according to the present disclosure can also have the following configuration. In the solid-state imaging device of the present disclosure having the following configuration, the intermediate member is provided in the gap between the first substrate and the second substrate so as to be adjacent to the chip in the in-plane direction orthogonal to the first direction. Therefore, for example, the thickness of the protective layer provided in the gap between the first substrate and the second substrate so as to cover the chip may be thin. As a result, it is possible to realize a structure suitable for thinning while having good imaging performance.
Note that the effects of the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
(1)
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate arranged to face the first substrate in a first direction;
a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
an intermediate member located in a gap between the first substrate and the second substrate and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
(2)
The imaging device according to (1), wherein the intermediate member is in contact with the chip via an insulating film in the in-plane direction.
(3)
The imaging device according to (1) or (2) above, further comprising a protective layer filled in a gap between the first substrate and the second substrate so as to cover the chip.
(4)
The imaging device according to (3) above, wherein the intermediate member has a second thermal conductivity higher than a first thermal conductivity of the protective layer.
(5)
The imaging device according to any one of (1) to (4) above, wherein the second substrate and the intermediate member are integrated.
(6)
The imaging device according to any one of (1) to (5) above, wherein the material of the second substrate and the material of the intermediate member are substantially the same.
(7)
The image pickup device according to any one of (1) to (6) above, wherein both the constituent material of the second substrate and the constituent material of the intermediate member are silicon (Si).
(8)
The chip is
a third substrate;
a circuit forming layer provided on the third substrate;
The imaging device according to any one of (1) to (7) above, comprising: a terminal portion provided on the circuit forming layer.
(9)
The distance between the chip and the first substrate in the first direction is substantially equal to the distance between the intermediate member and the first substrate according to any one of (1) to (8) above. Imaging device.
(10)
The imaging device according to any one of (1) to (8), wherein the distance between the chip and the first substrate is narrower than the distance between the intermediate member and the first substrate in the first direction. .
(11)
The imaging device according to any one of (1) to (8) above, wherein the distance between the chip and the first substrate is wider than the distance between the intermediate member and the first substrate in the first direction. .
(12)
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate having a recess facing the first substrate in a first direction;
A chip located between the first substrate and the second substrate, partially or entirely accommodated in the recess in the first direction, and having a circuit for performing signal processing of the pixel signal.
(13)
The imaging device according to (12) above, further comprising a protective layer filled in a gap between the first substrate and the second substrate so as to cover the chip.
(14)
The imaging device according to (13) above, wherein the intermediate member has a second thermal conductivity higher than a first thermal conductivity of the protective layer.
(15)
The imaging device according to (12) above, wherein the side wall of the concave portion and the end surface of the chip are separated from each other.
(16)
preparing a first substrate having an imaging element capable of generating a pixel signal, a second substrate, and a chip having a circuit for performing signal processing of the pixel signal;
forming an accommodation portion in the second substrate;
disposing the chip in the housing;
forming a protective layer over the second substrate and the chip;
and bonding the first substrate to the second substrate such that the chip is sandwiched between the substrate and the second substrate.
(17)
The method for manufacturing an imaging device according to (16) above, further comprising planarizing the protective layer.
(18)
The chip has a third substrate, an insulating layer provided on the third substrate, and wiring embedded in the insulating layer,
The method for manufacturing an imaging device according to (16) above, wherein the wiring is exposed from the insulating layer by planarizing the protective layer.
(19)
Equipped with an imaging device,
The imaging device is
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate arranged to face the first substrate in a first direction;
a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
An electronic device, comprising: an intermediate member located in a gap between the first substrate and the second substrate, and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
なお、本開示にかかる技術が奏する効果は、ここに記載された効果に必ずしも限定されるわけではなく、本開示中に記載されたいずれの効果であってもよい。
(1)
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向するように配置される第2基板と、
前記第1基板と前記第2基板との間に設けられると共に前記画素信号の信号処理を行う回路を有するチップと、
前記第1基板と前記第2基板との隙間に位置し、前記第1方向と直交する面内方向において前記チップと隣り合うように設けられた中間部材と
を備える撮像装置。
(2)
前記中間部材は、前記面内方向において絶縁膜を介して前記チップと接している
上記(1)記載の撮像装置。
(3)
前記チップを覆うように前記第1基板と前記第2基板との隙間に充填される保護層をさらに備える
上記(1)または(2)に記載の撮像装置。
(4)
前記中間部材は、前記保護層の第1熱伝導率よりも高い第2熱伝導率を有する
上記(3)記載の撮像装置。
(5)
前記第2基板と前記中間部材とは一体化されている
上記(1)から(4)のいずれか1つに記載の撮像装置。
(6)
前記第2基板の構成材料および前記中間部材の構成材料は、互いに実質的に同じである
上記(1)から(5)のいずれか1つに記載の撮像装置。
(7)
前記第2基板の構成材料および前記中間部材の構成材料は、いずれも珪素(Si)である
上記(1)から(6)のいずれか1つに記載の撮像装置。
(8)
前記チップは、
第3基板と、
前記第3基板上に設けられる回路形成層と、
前記回路形成層に設けられる端子部と
を有する
上記(1)から(7)のいずれか1つに記載の撮像装置。
(9)
前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔と実質的に等しい
上記(1)から(8)のいずれか1つに記載の撮像装置。
(10)
前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔よりも狭い
上記(1)から(8)のいずれか1つに記載の撮像装置。
(11)
前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔よりも広い
上記(1)から(8)のいずれか1つに記載の撮像装置。
(12)
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向する凹部を有する第2基板と、
前記第1基板と前記第2基板との間に位置し、前記第1方向の一部または全部が前記凹部に収容され、前記画素信号の信号処理を行う回路を有するチップと
を備える撮像装置。
(13)
前記チップを覆うように前記第1基板と前記第2基板との隙間に充填される保護層をさらに備える
上記(12)記載の撮像装置。
(14)
前記中間部材は、前記保護層の第1熱伝導率よりも高い第2熱伝導率を有する
上記(13)記載の撮像装置。
(15)
前記凹部の側壁と前記チップの端面とが離間している
上記(12)記載の撮像装置。
(16)
画素信号を生成可能な撮像素子を有する第1基板と、第2基板と、前記画素信号の信号処理を行う回路を有するチップとを用意することと、
前記第2基板に収容部を形成することと、
前記収容部に前記チップを配置することと、
前記第2基板および前記チップを覆うように保護層を形成することと、
前記第2基板との間に前記チップを挟持するように、前記第2基板に前記第1基板を接合することと
を含む
撮像装置の製造方法。
(17)
前記保護層を平坦化することをさらに含む
上記(16)記載の撮像装置の製造方法。
(18)
前記チップは、第3基板と、前記第3基板上に設けられた絶縁層と、前記絶縁層に埋設された配線とを有し、
前記保護層を平坦化することにより、前記配線を前記絶縁層から露出させる
上記(16)記載の撮像装置の製造方法。
(19)
撮像装置を備え、
前記撮像装置は、
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向するように配置される第2基板と、
前記第1基板と前記第2基板との間に設けられると共に前記画素信号の信号処理を行う回路を有するチップと、
前記第1基板と前記第2基板との隙間に位置し、前記第1方向と直交する面内方向において前記チップと隣り合うように設けられた中間部材と
を備える電子機器。 Note that the technology according to the present disclosure can also have the following configuration. In the solid-state imaging device of the present disclosure having the following configuration, the intermediate member is provided in the gap between the first substrate and the second substrate so as to be adjacent to the chip in the in-plane direction orthogonal to the first direction. Therefore, for example, the thickness of the protective layer provided in the gap between the first substrate and the second substrate so as to cover the chip may be thin. As a result, it is possible to realize a structure suitable for thinning while having good imaging performance.
Note that the effects of the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
(1)
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate arranged to face the first substrate in a first direction;
a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
an intermediate member located in a gap between the first substrate and the second substrate and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
(2)
The imaging device according to (1), wherein the intermediate member is in contact with the chip via an insulating film in the in-plane direction.
(3)
The imaging device according to (1) or (2) above, further comprising a protective layer filled in a gap between the first substrate and the second substrate so as to cover the chip.
(4)
The imaging device according to (3) above, wherein the intermediate member has a second thermal conductivity higher than a first thermal conductivity of the protective layer.
(5)
The imaging device according to any one of (1) to (4) above, wherein the second substrate and the intermediate member are integrated.
(6)
The imaging device according to any one of (1) to (5) above, wherein the material of the second substrate and the material of the intermediate member are substantially the same.
(7)
The image pickup device according to any one of (1) to (6) above, wherein both the constituent material of the second substrate and the constituent material of the intermediate member are silicon (Si).
(8)
The chip is
a third substrate;
a circuit forming layer provided on the third substrate;
The imaging device according to any one of (1) to (7) above, comprising: a terminal portion provided on the circuit forming layer.
(9)
The distance between the chip and the first substrate in the first direction is substantially equal to the distance between the intermediate member and the first substrate according to any one of (1) to (8) above. Imaging device.
(10)
The imaging device according to any one of (1) to (8), wherein the distance between the chip and the first substrate is narrower than the distance between the intermediate member and the first substrate in the first direction. .
(11)
The imaging device according to any one of (1) to (8) above, wherein the distance between the chip and the first substrate is wider than the distance between the intermediate member and the first substrate in the first direction. .
(12)
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate having a recess facing the first substrate in a first direction;
A chip located between the first substrate and the second substrate, partially or entirely accommodated in the recess in the first direction, and having a circuit for performing signal processing of the pixel signal.
(13)
The imaging device according to (12) above, further comprising a protective layer filled in a gap between the first substrate and the second substrate so as to cover the chip.
(14)
The imaging device according to (13) above, wherein the intermediate member has a second thermal conductivity higher than a first thermal conductivity of the protective layer.
(15)
The imaging device according to (12) above, wherein the side wall of the concave portion and the end surface of the chip are separated from each other.
(16)
preparing a first substrate having an imaging element capable of generating a pixel signal, a second substrate, and a chip having a circuit for performing signal processing of the pixel signal;
forming an accommodation portion in the second substrate;
disposing the chip in the housing;
forming a protective layer over the second substrate and the chip;
and bonding the first substrate to the second substrate such that the chip is sandwiched between the substrate and the second substrate.
(17)
The method for manufacturing an imaging device according to (16) above, further comprising planarizing the protective layer.
(18)
The chip has a third substrate, an insulating layer provided on the third substrate, and wiring embedded in the insulating layer,
The method for manufacturing an imaging device according to (16) above, wherein the wiring is exposed from the insulating layer by planarizing the protective layer.
(19)
Equipped with an imaging device,
The imaging device is
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate arranged to face the first substrate in a first direction;
a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
An electronic device, comprising: an intermediate member located in a gap between the first substrate and the second substrate, and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
本出願は、日本国特許庁において2021年3月15日に出願された日本特許出願番号2021-041900号を基礎として優先権を主張するものであり、この出願のすべての内容を参照によって本出願に援用する。
This application claims priority based on Japanese Patent Application No. 2021-041900 filed on March 15, 2021 at the Japan Patent Office, and the entire contents of this application are incorporated herein by reference. to refer to.
当業者であれば、設計上の要件や他の要因に応じて、種々の修正、コンビネーション、サブコンビネーション、および変更を想到し得るが、それらは添付の請求の範囲やその均等物の範囲に含まれるものであることが理解される。
Depending on design requirements and other factors, those skilled in the art may conceive various modifications, combinations, subcombinations, and modifications that fall within the scope of the appended claims and their equivalents. It is understood that
Claims (19)
- 複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向するように配置される第2基板と、
前記第1基板と前記第2基板との間に設けられると共に前記画素信号の信号処理を行う回路を有するチップと、
前記第1基板と前記第2基板との隙間に位置し、前記第1方向と直交する面内方向において前記チップと隣り合うように設けられた中間部材と
を備える撮像装置。 a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate arranged to face the first substrate in a first direction;
a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
an intermediate member located in a gap between the first substrate and the second substrate and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction. - 前記中間部材は、前記面内方向において絶縁膜を介して前記チップと接している
請求項1記載の撮像装置。 The imaging device according to claim 1, wherein the intermediate member is in contact with the chip via an insulating film in the in-plane direction. - 前記チップを覆うように前記第1基板と前記第2基板との隙間に充填される保護層をさらに備える
請求項1記載の撮像装置。 2. The imaging device according to claim 1, further comprising a protective layer filled in a gap between said first substrate and said second substrate so as to cover said chip. - 前記中間部材は、前記保護層の第1熱伝導率よりも高い第2熱伝導率を有する
請求項3記載の撮像装置。 The imaging device according to claim 3, wherein the intermediate member has a second thermal conductivity higher than the first thermal conductivity of the protective layer. - 前記第2基板と前記中間部材とは一体化されている
請求項1記載の撮像装置。 The imaging device according to claim 1, wherein the second substrate and the intermediate member are integrated. - 前記第2基板の構成材料および前記中間部材の構成材料は、互いに実質的に同じである
請求項1記載の撮像装置。 The imaging device according to claim 1, wherein the constituent material of the second substrate and the constituent material of the intermediate member are substantially the same. - 前記第2基板の構成材料および前記中間部材の構成材料は、いずれも珪素(Si)である
請求項1記載の撮像装置。 2. The imaging device according to claim 1, wherein the constituent material of the second substrate and the constituent material of the intermediate member are both silicon (Si). - 前記チップは、
第3基板と、
前記第3基板上に設けられる回路形成層と、
前記回路形成層に設けられる端子部と
を有する
請求項1記載の撮像装置。 The chip is
a third substrate;
a circuit forming layer provided on the third substrate;
The imaging device according to claim 1, further comprising a terminal section provided on the circuit forming layer. - 前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔と実質的に等しい
請求項1記載の撮像装置。 2. The imaging device according to claim 1, wherein the distance between said chip and said first substrate in said first direction is substantially equal to the distance between said intermediate member and said first substrate. - 前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔よりも狭い
請求項1記載の撮像装置。 2. The imaging device according to claim 1, wherein the distance between the chip and the first substrate is narrower than the distance between the intermediate member and the first substrate in the first direction. - 前記第1方向において、前記チップと前記第1基板との間隔が、前記中間部材と前記第1基板との間隔よりも広い
請求項1記載の撮像装置。 The imaging device according to claim 1, wherein the distance between the chip and the first substrate is wider than the distance between the intermediate member and the first substrate in the first direction. - 複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向する凹部を有する第2基板と、
前記第1基板と前記第2基板との間に位置し、前記第1方向の一部または全部が前記凹部に収容され、前記画素信号の信号処理を行う回路を有するチップと
を備える撮像装置。 a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate having a recess facing the first substrate in a first direction;
A chip located between the first substrate and the second substrate, partially or entirely accommodated in the recess in the first direction, and having a circuit for performing signal processing of the pixel signal. - 前記チップを覆うように前記第1基板と前記第2基板との隙間に充填される保護層をさらに備える
請求項12記載の撮像装置。 13. The imaging device according to claim 12, further comprising a protective layer filled in a gap between said first substrate and said second substrate so as to cover said chip. - 前記第2基板は、前記保護層の第1熱伝導率よりも高い第2熱伝導率を有する
請求項13記載の撮像装置。 The imaging device according to claim 13, wherein the second substrate has a second thermal conductivity higher than the first thermal conductivity of the protective layer. - 前記凹部の側壁と前記チップの端面とが離間している
請求項12記載の撮像装置。 13. The imaging device according to claim 12, wherein a side wall of said recess and an end face of said chip are separated from each other. - 画素信号を生成可能な撮像素子を有する第1基板と、第2基板と、前記画素信号の信号処理を行う回路を有するチップとを用意することと、
前記第2基板に収容部を形成することと、
前記収容部に前記チップを配置することと、
前記第2基板および前記チップを覆うように保護膜を形成することと、
前記第2基板との間に前記チップを挟持するように、前記第2基板に前記第1基板を接合することと
を含む
撮像装置の製造方法。 preparing a first substrate having an imaging element capable of generating a pixel signal, a second substrate, and a chip having a circuit for performing signal processing of the pixel signal;
forming an accommodation portion in the second substrate;
disposing the chip in the housing;
forming a protective film to cover the second substrate and the chip;
and bonding the first substrate to the second substrate such that the chip is sandwiched between the substrate and the second substrate. - 前記保護膜を平坦化することをさらに含む
請求項16記載の撮像装置の製造方法。 17. The method of manufacturing an imaging device according to claim 16, further comprising planarizing the protective film. - 前記チップは、第3基板と、前記第3基板上に設けられた絶縁層と、前記絶縁層に埋設された配線とを有し、
前記保護膜を平坦化することにより、前記配線を前記絶縁層から露出させる
請求項16記載の撮像装置の製造方法。 The chip has a third substrate, an insulating layer provided on the third substrate, and wiring embedded in the insulating layer,
17. The method of manufacturing an imaging device according to claim 16, wherein the wiring is exposed from the insulating layer by planarizing the protective film. - 撮像装置を備え、
前記撮像装置は、
複数の画素を含んで前記画素ごとに画素信号を生成可能な撮像素子を有する第1基板と、
第1方向において前記第1基板と対向するように配置される第2基板と、
前記第1基板と前記第2基板との間に設けられると共に前記画素信号の信号処理を行う回路を有するチップと、
前記第1基板と前記第2基板との隙間に位置し、前記第1方向と直交する面内方向において前記チップと隣り合うように設けられた中間部材と
を備える電子機器。 Equipped with an imaging device,
The imaging device is
a first substrate having an imaging device that includes a plurality of pixels and is capable of generating a pixel signal for each pixel;
a second substrate arranged to face the first substrate in a first direction;
a chip provided between the first substrate and the second substrate and having a circuit for performing signal processing of the pixel signal;
An electronic device, comprising: an intermediate member located in a gap between the first substrate and the second substrate, and provided so as to be adjacent to the chip in an in-plane direction perpendicular to the first direction.
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