JPS63131546A - Semiconductor device - Google Patents

Abstract

PURPOSE:To flatten an inter-layer insulating film easily and positively by using an insulating film formed through a bias-sputtering method as the inter-layer insulating film as a foundation and shaping an applied baked insulating film onto the insulating film. CONSTITUTION:First wiring layer patterns 2 consisting of aluminum are formed onto a semiconductor substrate 1, and an oxide film 3 is applied through a bias-sputtering method. The film through the bias-sputtering method is applied at that time because the shape of a depositing insulating film is easy to be flattened. S.O.G films 4 through an application baking method are cured after spin coating, and an inter-layer insulating film having the excellent flatness of the surface is acquired. Accordingly, the insulating film is shaped effectively onto the fine and complicate wiring patterns without uselessly narrowing the spaces of the wiring layers, and the films are also applied and baked into recessed sections formed by the wiring patterns of the S.O.G films positively, thus acquiring the inter-layer insulating film having a flat surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interlayer insulating film between multilayer interconnections in an integrated circuit or the like, and particularly to flattening the surface of an interlayer insulating film.

[Conventional technology]

BACKGROUND OF THE INVENTION As semiconductor integrated circuits become more densely packed, wiring patterns between circuit elements become finer and more multilayered. When wiring fine wiring patterns in multiple layers, an interlayer insulating film is interposed to ensure complete insulation between each wiring layer, but the surface of the interlayer insulating film formed on the wiring layer of the underwear is It is necessary to flatten the formed wiring layer in order to ensure reliable adhesion. Conventionally, several methods for forming a planarized interlayer insulating film have been proposed.

Method using coated and fired insulating film (Spin On Glass)
The s method (hereinafter referred to as the SOG method) is one of them, as shown in Figure 2 (a).
As shown in FIG. 2, after depositing an oxide film 23 formed by plasma CVD on the entire surface of the substrate 21 on which the wiring pattern 22 is formed, a glass component dissolved in a solvent is spin-coated and plasma C.
A glass film is deposited on the concave portion of the oxide film 23 by the VD method, and then baked, followed by S, 0. G and M'A24 are formed to eliminate unevenness caused by the wiring pattern and to form a flat insulating film.

In addition, the bias sputtering method performs sputtering by applying a bias between the target and the substrate, and the insulating film ions excited from the target are directly deposited on the substrate, as shown in Figure 3 (al). Insulating film 33 to be deposited
It is not uniformly distributed around the wiring pattern 32 and is deposited on the substrate and the wiring layer, and especially on the wiring layer, it is deposited in the shape of a mountain with a taper angle θ. Therefore, the groove between wiring layers is difficult to narrow,
In addition, the surface can be easily flattened depending on the sputtering conditions (for example, VLSI 5ynp'83.Te
Chnical Digest.

(See pages 100-101).

[Problem that the invention seeks to solve]

However, these conventional methods have the following disadvantages as wiring patterns become finer and their shapes become more complex.

In other words, the method using a coated and fired oxide film can planarize the interlayer insulating film very easily and in a short time. When the groove 2 between the plasma oxide films 23
The interval d' between 3' and 3' is further refined and becomes narrower and steeper, so S, O, G.

A problem arises in that the JI924 does not adhere to the fine grooves and that part cannot be flattened.

In addition, with the method using bias sputtering, even if the wiring pattern becomes finer, the sputtered film is mainly coated on the wiring pattern at an angle, and the surface can be sufficiently flattened over time, but it is not completely flat. It takes too much time to convert into
When the wiring patterns 32 and 32' have different widths, the film thicknesses H1 and H2 to be flattened will differ, and if the power supply part has a wiring part with a wide back width, it will take a longer time to complete the flattening. The film thickness H also becomes thicker. Also, if the film deposition is stopped midway, a surface with an edge 33' will remain as shown in FIG. If the electric field is strengthened to increase the deposition rate, the energy of the excited ions that directly spackle the substrate 31 will be high (this will also affect the characteristics of elements such as transistors that are pre-formed in the substrate 31, causing Problems such as a shift in threshold voltage (vth) and an increase in leakage current arise.

Therefore, an object of the present invention is to provide a semiconductor device having an interlayer insulating film that can reliably flatten the surface of the interlayer insulating film in a multilayer wiring structure having a fine and complicated wiring pattern in a short time in order to solve the above-mentioned problems. It provides:

Means and operation for solving problem C] The present invention is directed to the first
An insulating film is formed by a bias spacing method on a substrate on which a wiring layer has been formed, and then S is deposited by a coating and baking method.
, O, G, and films are spin-coated and then cured to obtain an interlayer insulating film with good surface flatness.

By first depositing an insulating film on the first wiring layer using a bias sputtering method, the insulating film is effectively formed on the fine and complicated wiring layer without unnecessarily narrowing the spacing between the wiring layers. S, O, G formed in
The film is reliably coated and baked even in the recesses formed by the wiring pattern, and an interlayer insulating film with a flat surface can be obtained.

〔Example〕

An embodiment of the invention will be described with reference to FIG.

FIG. 1 is an explanatory diagram showing the process of forming an interlayer insulating film according to the present invention. First, a first wiring layer pattern 2 made of aluminum is formed according to a design on a semiconductor substrate 1 on which circuit elements such as transistors are to be formed. do. An oxide film 3 is deposited on this substrate 1 by bias sputtering. For example, R
F power 2゜5KW, argon gas pressure 10X10=I
When the film is deposited under the conditions of -80 V and -80 V bias, the taper angle θ of the oxide film formed on the wiring pattern is about 55° (FIG. 1(a)). The reason why the film is deposited using the bias sputtering method is that the shape of the deposited insulating film tends to be flattened.If the oxide film is formed using a method such as sputtering that does not apply a bias, the oxide film will be uniformly formed around the wiring layer. is formed, and the width d' at the bottom of the oxide film trench is much smaller than the interconnect spacing d, which is the 3.0. This makes it difficult for S, O, G, and MJ to adhere to the grooves in which the G and film are applied, resulting in poor flatness of the interlayer insulating film. In addition, when the bias is increased, the tilter angle θ of the edge of the deposited oxide film becomes smaller and the flatness after the S, O, G film formation process becomes better.
The sputtering conditions are set so that the taper angle is about 60' because the effect on the circuit elements formed in the sputtering is large.

Next, in order to improve the adhesion of the S, O, G film, it was treated in oxygen plasma for about 10 minutes, and then the S, O,
The S, O, G film is coated with approximately 400 Or, p, m, and heated at approximately 300° C. for 15 minutes after pre-beta to evaporate the solvent, forming the S, O, G film 4 (Figure 1 (b)). ).

Furthermore, a phosphorus glass film 5 (Pho
A sphosi'licate glass film (hereinafter referred to as P film) is deposited over the entire substrate at about 430° C. by about 5,000 coats (FIG. 1(C)). This film is produced by PS (
J! Alternatively, an insulating film formed by a plasma CVD method, a photo CVD method, or a sputtering method may be used.

A wiring layer 6 is formed on the interlayer insulating film planarized in this manner according to the second wiring pattern to complete a multilayer wiring (FIG. 1(d)).

〔Effect of the invention〕

By using an interlayer insulating film having the structure of the present invention, it is possible to easily and reliably flatten the interlayer insulating film even when the wiring layer has a fine pattern, and the insulation between multilayer wiring can be made perfect. Moreover, a highly reliable semiconductor device that does not cause problems such as disconnection of the upper wiring layer can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a detailed explanatory diagram of the present invention, and FIGS. 2 and 3 are explanatory diagrams of a conventional example. 1.21, 31 - Substrate 2 - Wiring layer 3 - Insulating film 4 by bias sputtering method...S, O
, G, film 5--phosphorus glass film 6-- upper wiring layer 22
．． 32--Wiring layer 23--Oxide film 24-5 by plasma CVD method. O
, G, Film 33 - Oxide film by bias sputtering Fig. 1 Fig. 2 Fig. 3

Claims (1)

[Claims] A semiconductor device having multilayer wiring, which has an insulating film including at least a coated and fired insulating film formed on an insulating film formed by a bias sputtering method as a base and an insulating film formed by a bias sputtering method as an interlayer insulating film.