JPS59195845A - Fabrication of multilayer interconnection - Google Patents

Abstract

PURPOSE:To prevent breakage of the wiring layer and to improve the manufacturing yield and the reliability by laying a first wiring layer on the projecting part previously arranged on the substrate as well as by subjecting the inter-layer insulating film to levelling treatment. CONSTITUTION:A projecting part 12 is arranged on the predetermined position of the semiconductor substrate 11. Next, as a wiring of first layer, Al is coated and this film is patterned to form a first wiring layer 13. Next, for levelling of the surface, an organic insulator e.g. polyimide resin is spin-coated to form an insulating film 14. Next, the insulating film 14 is subjected to the overall etching so far as a first wiring layer 13a on the projecting part 12 is exposed. Lastly, a metal layer to become a second wiring, e.g. Al film coated over the whole surface is patterned to form a second wiring layer 15. At this time, a part of the second wiring layer 15 is so arranged that it is in contact with the exposed first wiring layer 13a.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing multilayer wiring.

[Technical background of the invention and its problems]

Conventionally, the following method is used to manufacture multilayer wiring. First, as shown in FIG.
A first wiring layer 2 is formed by /f turning the metal layer using photolithography. Next, if it is an inorganic insulator, C
VD method or SuA? An insulating film 3 is deposited on the entire surface as shown in FIG. 1(b) using the ivy method or the spin coating method if an organic insulator is used. Thereafter, through holes 4 are formed at predetermined locations using photolithography as shown in FIG. 1(e). Next, a metal layer is deposited on the entire surface by a vapor deposition method, a sputtering method, etc., and then the metal layer is patterned using a photolithography method to form the second wiring layer 5 as shown in FIG. 1(d). form. This completes the multilayer wiring.

Incidentally, in recent years, as patterns have become finer, higher processing precision has been required, and the sides of both the p1 wiring layer and through holes are now cut vertically. Along with this, the following problems have arisen in the above-mentioned method. That is, when an inorganic insulator is used as the insulating film 3, breaks occur in the second wiring layer 5 at the edge portions 6 and through-hole portions 7 of the first wiring layer 2, as shown in FIG. 2(a). Furthermore, when an organic insulator is used as the insulating film 3, as shown in FIG.
As shown in b), since the surface of the insulating film 3 becomes relatively flat, there is no step break at the edge portion, but a step break occurs in the through hole portion 7 as well. As a result, there has been a problem in that manufacturing yield and reliability are reduced.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing multilayer wiring that can prevent disconnection of wiring layers and improve manufacturing yield and reliability.

[Summary of the invention]

The gist of the present invention is to provide a convex portion on the substrate in advance, pass the first wiring layer over the convex portion, and flatten the interlayer insulating film to eliminate steps and through holes at the crossover portion of the wiring layer. The aim is to eliminate the department.

That is, in the method of manufacturing multilayer wiring, the present invention forms a convex portion at a predetermined position R on a substrate (a position where contact between wiring layers is to be made), and then forms an IF-first wiring layer on the substrate. A part of the wiring layer is formed on the convex portion, and then an insulating film is deposited on the entire surface and the surface is planarized, and then the entire surface is etched until the first wiring layer on the convex portion is exposed. In this method, the film is etched 1.4 times, and then a second wiring layer is formed on the insulating film, and a part of the wiring layer is brought into contact with the exposed first wiring layer.

〔Effect of the invention〕

According to the present invention, steps and through holes at the edge portion of the first wiring layer are eliminated, and the second wiring layer can be formed on the insulating film with a substantially flat surface.
It is possible to prevent disconnections in the wiring layer. Therefore, multilayer wiring with high manufacturing yield and high reliability can be easily manufactured.

Furthermore, there is no need to form snow holes using photoetching for contact between the first and second wiring layers, and the contact can be realized simply by etching the entire surface of the insulating film.
It has the advantage that the manufacturing process is significantly simplified and productivity can be improved.

[Embodiments of the invention]

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 3(a) to 3(e) are cross-sectional views showing a multilayer wiring manufacturing process according to an embodiment of the present invention.

In this embodiment, a case will be explained in which a semiconductor substrate is used as the substrate. In addition, the semiconductor substrate includes transistors,
Diodes, resistors, etc. are integrated, but are omitted from the diagram. First, as shown in FIG. 3(a), a convex portion 12 is provided at a predetermined position on a semiconductor substrate 1. As shown in FIG. There are various ways to create the convex portion 12, but in this embodiment, the method was as follows. That is, after selectively forming polysilicon islands 31 at predetermined positions on the substrate 1 as shown in FIG. 4(a), an oxide film 32 containing phosphorus is formed over the entire surface as shown in FIG. 4(b).
For example, a PSG film is deposited by CVD or the like. after that,
This is melted by heat treatment, as shown in Figure 4 (C
), a relatively gentle protrusion 33 is formed on the substrate 11.

Then, this convex portion 33 was used as the convex portion 12. Although polysilicon is used here for the island 3, it is not limited to this, and may be an oxide film, a nitride film, a metal, or the like. Further, the insulating film 32 deposited on the island 31 is not limited to an oxide film containing phosphorus, but may be an organic insulating material such as polyimide.

Next, as the first layer of wiring, for example, aluminum is deposited to a thickness of approximately 1 μm over the entire surface by vapor deposition or sputtering, and this aluminum film is patterned by photolithography as shown in Figure 3(b). A first wiring layer 13 is formed as shown. At this time, by arranging the wiring layer 13 so that at least a part thereof immediately covers the top of the convex part 12, there is a height difference between the wiring layer 13a at the top of the convex part 120 and the wiring layer 13b in other parts. You can make a difference. Next, in order to flatten the surface, an insulating film 14 is formed using an organic insulator such as polyimide resin by spin coating, as shown in FIG. 3(c).

Here, the method of spin-coding polyimide resin has the characteristic that it adheres thickly to low places and thinly to high places, so it is more suitable for flattening than other methods such as CVD method of depositing 8i02 film. There is. Furthermore, in order to make the surface more flat, it is better to apply a thin film multiple times rather than applying a thick film once. This method reduces surface irregularities by 20
00(X) or less.

Next, as shown in FIG. 3(d), the first
The entire surface of the insulating film 14 is etched until the wiring layer 13a is exposed. This etching includes wet etching,
Although it is different from dry etching using a gas, dry etching is superior in terms of uniformity and reproducibility. Among them, dry etching using a parallel plate type plasma etching apparatus is extremely superior. Further, as the etching gas, oxygen or a mixed gas mainly containing oxygen may be used. Typical etching conditions include oxygen gas pressure of 0.02 (Torr) and high frequency power density of 0.15.
(Approximately 1200CX / when W/cffl “l”
An etching rate of min ) is obtained. Finally, a metal layer that will become the second layer of wiring, such as aluminum, is deposited to a thickness of approximately 1 μm over the entire surface by vapor deposition or sputtering, and a pattern of this aluminum film is engraved using photolithography. A second wiring layer 15 is formed as shown in FIG. 3(e). At this time, a part of the second wiring layer 15 is brought into contact with the exposed first wiring JGQ 13a.

Thus, according to the method of this embodiment, the second wiring layer 15 is formed on the insulating film 14 whose surface is substantially flat. Therefore, inconveniences such as breakage in the second wiring layer 15 at the edge portion of the first wiring layer 13 can be prevented.

In addition, since there is no need to use through holes as in the prior art when making contact between the wiring layers 13 and 15, there is no problem such as breakage of the second wiring layer 15 at the contact portion. Therefore, manufacturing yield and reliability can be significantly improved.

Note that the present invention is not limited to the embodiments described above. For example, various conductive films other than (r:i) and aluminum can be used as the wiring layer. Also, it goes without saying that the method for forming the wiring layer is not limited to vapor deposition, sputtering, or the like. Furthermore, it is most preferable that the insulating film between the wiring layers is made of an organic material from the viewpoint of surface flattening.
It may also be an inorganic material such as Sio, 8i3N, or the like. In this case, after depositing the above-mentioned inorganic insulating film for surface flattening, an organic material such as lenost is applied relatively thickly on the insulating film to flatten the resist surface, and then each etching rate of the resist and the insulating film is adjusted. Etching may be performed on the entire surface under substantially equal conditions.

Furthermore, the method for forming the convex portions on the substrate is not limited to the embodiments, and can be changed as appropriate. Furthermore, if a semiconductor substrate or the like has a convex portion that is inevitably formed during the process of forming an element, it is also possible to utilize this convex portion.

Furthermore, it is also possible to use an insulating substrate instead of a semiconductor substrate as the substrate. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are cross-sectional views showing the conventional multilayer wiring manufacturing process, FIGS. 2(a) and (b) are cross-sectional views for explaining the problems of the conventional method, and FIG. a) to (e) are cross-sectional views showing the multilayer wiring manufacturing process according to an embodiment of the present invention, and FIGS. 4(a) to (C) are cross-sectional views showing the process of forming the convex portions used in the above embodiment. It is a diagram. DESCRIPTION OF SYMBOLS 11... Substrate, 12.33... Convex part, 13... First wiring layer, 14... Insulating film, 15... Second wiring layer, 3
1... Polysilicon island, 32... Oxide film. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 C Figure 3 Figure 3 Figure 4

Claims (4)

[Claims] (1)゛ In a method for manufacturing multilayer wiring formed by laminating a plurality of wiring layers on a substrate, a step of forming a convex portion at a predetermined position on the substrate, and then forming a first wiring layer on the substrate. and forming a part of the wiring layer on the convex portion, then a step of depositing an insulating film over the entire surface and flattening the surface, and then etching the entire surface to form a part of the wiring layer on the convex portion. etching the insulating film until the first wiring layer is exposed; and then forming a second wiring layer on the insulating film and bringing a portion of the wiring layer into contact with the exposed first wiring layer. A method for manufacturing multilayer wiring, characterized by comprising: (2) The method for manufacturing a multilayer wiring according to claim 1, wherein an organic material is used as the insulating film. (3) The insulating film is made of an inorganic material, and after the insulating film is deposited on the entire surface, a resist is applied on the insulating film and the entire surface is etched to flatten the surface. A method for manufacturing a multilayer wiring according to claim 1. (4) A method of manufacturing a multilayer wiring according to claim 1, characterized in that a parallel plate type plasma etching apparatus is used in the step of etching the entire surface of the insulating film.