JPH05175195A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid an increase of parasitic capacitance due to a dummy pattern for flattening in relation to a flattening technique relating to multilayer wiring for inner connection of a semiconductor integrated circuit. CONSTITUTION:After forming a dummy pattern consisting of the same conductive layer with a wiring 2 or an electrode 3 followed by covering this dummy pattern 8 with a thin insulating layer, the conductive layer composing the dummy pattern 8 through an opening provided on this insulating layer is selectively removed. Later, the interlayer insulating layers are piled up on the wiring 2 or the electrode 3 and the insulating layer by using a normal pressure CVD method. A cavity generated after removal of the dummy pattern 8 is filled with the interlayer insulating layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a planarization technique related to a multi-layer wiring for its internal connection.

The miniaturization of elements, wirings, or electrodes accompanying the higher density of semiconductor integrated circuits is progressing more rapidly in the horizontal direction than in the vertical direction. For this reason, there is an urgent need to reduce the step due to the wiring pattern having a high aspect ratio. That is, in order to efficiently expose a fine pattern, it is necessary to use a lens having a large numerical aperture, but when the numerical aperture becomes large, the depth of focus of the lens becomes shallow. Therefore, if there is unevenness in the thickness of the resist layer due to the step, a lens with a large numerical aperture cannot be used, and as a result,
This is because the area of the mask pattern that can be collectively exposed is small, and it becomes impossible to expose an integrated circuit chip having a large area.

[0003]

Therefore, when an interlayer insulating layer or an upper wiring is formed on a stepped surface, a base layer is flattened by coating a resin layer or sputtering the surface with argon gas in advance. The method of converting to the conventional method has been adopted. For example, as shown in FIG. 2, a wiring 2 and an electrode 3 are formed on the surface of a semiconductor substrate 1 covered with an insulating layer. In order to eliminate a step due to the wiring 2 and the electrode 3, a so-called spin-on-glass (SO
A flattening layer 4 is formed by applying a silicic acid solution such as G). In this way, the step due to the wiring 2 or the electrode 3 is flattened, a contact hole is provided in the flattening layer 4, and then the upper wiring 5 is formed.

According to the above method, the wiring 2 or the electrode 3
The level difference between the individual patterns and the region in the vicinity thereof is reduced. However, when the area on one side of the level difference is large as in the case of the electrode 3, the flattening layer 4 near the center of this region is formed. Becomes relatively thick. In flattening by sputtering, the etching rate in the direction inclined at 45 ° is generally higher than the etching rate in the direction perpendicular to the surface, so the same phenomenon occurs. As described above, the above method is effective for the local flattening, but cannot sufficiently obtain the flattening over a large area.

[0005]

On the other hand, as shown in FIG. 3, at least in a region requiring a flat base, a space between predetermined patterns having steps such as the wiring 2 or the electrode 3 is formed. There is also used a method of laying the dummy pattern 7 on. According to this method, since the influence of the area of the wiring 2 or the electrode 3 as shown in FIG. 2 does not appear, the flattening layer 4 having a uniform thickness is formed.
Can be formed over the entire chip area, for example. As a result, it is possible to pattern fine contact holes and upper layer wiring by using an exposure system equipped with a large aperture lens.

However, since the dummy pattern 7 as described above is usually formed by etching the same conductive layer as the wiring 2 and the electrode 3 which cause a step, the wiring through the dummy pattern 7 is not possible. Between 2 or wiring 2 and electrode 3
Or the parasitic capacitance between the upper wiring 5 and the semiconductor substrate 1
There was a problem that (C) increased. The dummy pattern 7
Although it is possible to form the insulating layer separately from the conductive layer for the wiring 2 and the electrode 3, there is a problem in that the yield is reduced due to an increase in the number of processes and pattern alignment.

An object of the present invention is to solve the problems in the above-described conventional flattening technique using a dummy pattern.

[0008]

The above object is to form a conductive layer on one surface of a semiconductor substrate covered with an insulating layer, etch the conductive layer to form a plurality of wirings, and to form a plurality of wirings between adjacent wirings. A dummy pattern composed of the conductive layer electrically separated from the wiring is formed, a second insulating layer covering at least the dummy pattern is formed, and the dummy is formed on the second insulating layer on the dummy pattern. An opening that exposes at least a part of the pattern is formed, and the dummy pattern covered with the second insulating layer in which the opening is formed is selectively removed by using an isotropic etching agent. A cavity surrounded by a second insulating layer is formed, and a third insulating layer is formed on the surface of the semiconductor substrate having the second insulating layer in which the cavity is formed, and the third insulating layer is formed on the third insulating layer. A second wire connected to the wire or electrode This is achieved by a method for manufacturing a semiconductor device according to the present invention, which includes various forming steps.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. A dummy pattern 8 spread between wirings 2 or electrodes 3 having steps is a hollow thin insulating layer 9 and the inside of this insulating layer 9. And a planarization layer 4 filling the same. Such a dummy pattern 8 is formed by patterning the same conductive layer as the wiring 2 and the like to form a dummy pattern prototype.
After covering with, the conductive layer in the dummy pattern is selectively removed. As a result, the insulating layer 9, which is a replica of the removed conductive layer, remains. After that, the planarization layer 4 is deposited by, for example, the atmospheric pressure CVD method. As a result, the cavity in the insulating layer 9 is filled with the flattening layer 4. According to the dummy pattern 8 of the present invention, the flattening effect is maintained and, at the same time, the increase of the parasitic capacitance as in the conventional dummy pattern made of the conductive layer is avoided.

[0010]

EXAMPLE FIG. 4 is a cross-sectional view for explaining a process of an example of the present invention. As shown in FIG. 4A, the surface of a semiconductor substrate 10 covered with an insulating layer is, A conductive layer having a thickness of about 1 μm is deposited, and the conductive layer is etched to form wirings or electrodes 11 and a dummy pattern master 12. The width of the wiring or electrode 11 and the dummy pattern master 12 in the lateral direction is about 1.5 μm, and the distance between them is about 0.8 μm. Depending on the distance between the wirings or electrodes 11, a plurality of dummy patterns 12 may be provided in the lateral direction. In addition, in the cross section perpendicular to the paper surface, normally,
It has a structure in which a plurality of dummy pattern prototypes 12 are arranged with the same width and mutual spacing as above.

Next, as shown in FIG. 1B, at least the dummy pattern prototype 12 is covered with, for example, silicate glass (P
An insulating layer 14 made of SG) and having a thickness of about 1000 Å is formed. Usually, the insulating layer 14 may be formed on the entire semiconductor substrate 10,
Therefore, the wiring or electrode 11 is also covered with the insulating layer 14.

Next, as shown in FIG. 1C, a resist layer 15 is applied to the entire surface of the semiconductor substrate 10, and an opening 16 exposing a part of the dummy pattern master 12 is formed in the resist layer 15. Form. The size of this opening 16 may be the same as that of a contact hole for connection between multilayer wirings, and is, for example, a rectangle with one side of about 0.6 μm. After that, opening 16
Through, the conductive layer forming the dummy pattern prototype 12 is selectively etched and removed. As a result, the cavity 12A remains after the dummy pattern prototype 12.

Next, after removing the resist layer 15, as shown in FIG.
An approximately 1.0 μm thick insulating layer 18 of SiO ₂ is deposited. The insulating layer 18 is made of, for example, well-known atmospheric pressure CVD (chemical vapor deposition) using a mixed gas of tetraethoxysilane (TEOS) and ozone as a raw material.
, The insulating layer 18 inside the cavity 12A.
Is easily grown, and most of the cavity 12A is filled with a part of the insulating layer 18. The insulating layer 18 serves as the flattening layer to flatten the step due to the wiring or the electrode 11 and constitutes an interlayer insulating layer with an upper wiring to be formed later.

After that, a contact hole that exposes the wiring or the electrode 11 is formed in the insulating layer 18 and an upper wiring (not shown) made of aluminum or the like is further formed on the insulating layer 18 according to a normal process. To do.

The dummy pattern prototype 12 as described above is used.
The removal of the conductive layer and the burying of the insulating layer 18 in the cavity after removing it form the well-known fin structure and the dielectric film that form the capacitor electrode in a kind of dynamic random access memory (DRAM). It can be more easily implemented compared to. That is, the fins in the DRAM are based on the technology of etching and depositing the insulating layer in the gap of about several hundred Å. Further, the process of removing the dummy pattern prototype 12 and forming the cavity 12A as described above may be performed only on an integrated circuit and a specific circuit block of which high speed is required, and high speed is required. It goes without saying that the conductive layer of the dummy pattern prototype 12 may be left as it is for the products that do not.

[0016]

According to the present invention, it is possible to avoid an increase in parasitic capacitance in the flattening method in which dummy patterns are spread between wirings or electrodes, and it is possible to improve the performance and performance of a high density integrated circuit that requires fine multilayer wiring. It greatly contributes to the improvement of manufacturing yield.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is an explanatory view of a conventional problem (No. 1)

FIG. 3 is an explanatory diagram of conventional problems (No. 2)

FIG. 4 is a process explanatory view of the embodiment of the present invention.

[Explanation of symbols]

 1, 10 Semiconductor substrate 2 Wiring 3 Electrode 4 Flattening layer 5 Upper layer wiring 7, 8 Dummy pattern 9, 14, 18 Insulating layer 11 Wiring or electrode 12 Dummy pattern prototype 12A Cavity 15 Resist layer 16 Opening

Claims (3)

[Claims] 1. A step of forming a conductive layer on one surface of a semiconductor substrate covered with an insulating layer, and etching the conductive layer to form a plurality of wirings or electrodes, and the wirings between adjacent wirings or electrodes. Alternatively, a step of forming a dummy pattern composed of the conductive layer electrically separated from the electrode, a step of forming a second insulating layer covering at least the dummy pattern, and a step of forming the second insulating layer on the dummy pattern. Forming an opening exposing at least a part of the dummy pattern in the layer, and selecting the dummy pattern covered with the second insulating layer in which the opening is formed using an isotropic etching agent. Of removing the second insulating layer to form a cavity surrounded by the second insulating layer, and forming a third insulating layer on the surface of the semiconductor substrate having the second insulating layer in which the cavity is formed. When, A step of forming a second wiring connected to the wiring or the electrode on the third insulating layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the cavity is filled with a part of the third insulating layer. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the third insulating layer is formed by a vapor phase growth method under normal pressure.