JPH05175342A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a parasitic capacitance according to a dummy pattern for flattening related to a multilayer wiring for internal connection of a semiconductor integrated circuit. CONSTITUTION:An intermediate resist layer 9 where a granular filling material 9A of specified dimensions made of an etching-resistance material is dispersed is coated on the same conductive layer as a wiring 2 and an electrode 3, an upper-layer resist layer 11 with a pattern corresponding to the wiring and the electrodes is formed on it, and then an exposed intermediate resist layer is subjected to anisotropic etching. In this case, since a resist layer directly below the filling material cannot be etched, a column-shaped intermediate resist layer 9 remains in a region between the wirings or the electrodes. A conductive layer is subjected to anisotropic etching using, as a mask, the column-shaped intermediate resist layer patterned using a lower-layer resist layer 10 as a mask. Also, a column-shaped dummy pattern 8 consisting of a conductive layer is formed in the same region in self-alignment manner reflecting the shape and the distribution density of the filling material within the intermediate resist layer and the column-shaped dummy pattern suppresses the increase in parasitic capacitance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a planarization technique related to a multi-layer wiring for its internal connection.

The miniaturization of elements, wirings, or electrodes accompanying the higher density of semiconductor integrated circuits is progressing more rapidly in the horizontal direction than in the vertical direction. For this reason, there is an urgent need to reduce the step due to the wiring pattern having a high aspect ratio. That is, in order to efficiently expose a fine pattern, it is necessary to use a lens having a large numerical aperture, but when the numerical aperture becomes large, the depth of focus of the lens becomes shallow. Therefore, if there is unevenness in the thickness of the resist layer due to the step, a lens with a large numerical aperture cannot be used, and as a result,
Inevitably, it becomes difficult to expose a large-area integrated circuit chip.

[0003]

Therefore, when an interlayer insulating layer or an upper wiring is formed on a stepped surface, a resin layer is applied in advance or the surface is sputtered with an argon gas to form a base. The method of flattening has been conventionally used. For example, as shown in FIG. 3, wirings 2 and electrodes 3 are formed on the surface of a semiconductor substrate 1 covered with an insulating layer, and so-called spin-on-glass (S
A flattening layer 4 is formed by applying a silicic acid solution such as OG). In this way, the step due to the wiring 2 or the electrode 3 is flattened, a contact hole is provided in the flattening layer 4, and then the upper wiring 5 is formed.

By the above method, the wiring 2 or the electrode 3
The level difference between the individual patterns and the region in the vicinity thereof is reduced. However, when the area on one side of the level difference is large as in the case of the electrode 3, the planarization layer 4 near the center of this region is formed. Becomes relatively thick. A similar phenomenon occurs in flattening by sputtering because the etching rate in the direction inclined at 45 ° is generally higher than the etching rate in the direction perpendicular to the surface. Thus, although the above method is effective for microscopic planarization, it is not effective enough for macroscopic planarization over a wide area.

[0005]

On the other hand, as shown in FIG. 4, at least in a region requiring a flat base, a space between predetermined patterns having steps such as the wiring 2 or the electrode 3 is formed. There is also used a method of laying the dummy pattern 7 on. According to this method, since the influence of the area of the wiring 2 or the electrode 3 as shown in FIG. 3 does not appear, the flattening layer 4 having a uniform thickness can be formed, for example, over the entire chip region.
As a result, using an exposure device equipped with a large aperture lens,
It is possible to pattern fine contact holes and upper wiring.

However, since the dummy pattern 7 as described above is usually formed by etching the same conductive layer as the wiring 2 and the electrode 3 which cause a step, the wiring through the dummy pattern 7 is not possible. Between 2 or wiring 2 and electrode 3
Or the parasitic capacitance between the upper wiring 5 and the semiconductor substrate 1
There was a problem that (C) increased. The dummy pattern 7
Although it is possible to form the insulating layer separately from the conductive layer for the wiring 2 and the electrode 3, there is a problem in that the yield is reduced due to an increase in the number of processes and pattern alignment.

An object of the present invention is to solve the problems in the above-described conventional flattening technique using a dummy pattern.

[0008]

The object of the invention is to form a conductive layer on one surface of a semiconductor substrate covered by an insulating layer, and then apply a lower resist layer on the conductive layer to form a material having etching resistance. An intermediate resist layer having a granular filler dispersed therein is applied on the lower resist layer, and an upper resist layer having a pattern corresponding to a desired wiring or electrode is formed on the intermediate resist layer. After the first anisotropic etching is performed on the intermediate resist layer using the mask as a mask to leave the filler and the intermediate resist layer in the shaded portion of the filler in the region exposed from the upper resist. Removing the upper resist layer, and using the intermediate layer and the filler present on the surface of the substrate from which the upper resist layer has been removed as a mask, and second with respect to the lower resist layer
Anisotropic etching is performed, and the conductive layer is subjected to third anisotropic etching using the lower resist layer subjected to the second anisotropic etching as a mask to form the wiring or electrode. And a method for manufacturing a semiconductor device according to the present invention, which includes various steps of forming an insulating layer covering the surface of the substrate on which the wiring or the electrode is formed.

[0009]

1 is a plan view of the present invention, (a) is a plan view, and (b) is a sectional view taken along line XX in (a). A dummy pattern made of the same conductive layer as these is spread between the wirings 2 or electrodes 3 having steps, but a finer dummy pattern 8 is formed in a self-aligned manner as compared with the conventional one. For this purpose, so-called multilayer resist technology is used. That is, as shown in the figure, for example, the lower resist layer
A filler 9A of a predetermined size made of an etching resistant material is dispersed in an intermediate resist layer 9 of a multilayer resist consisting of 10 and an upper resist layer 11. In the anisotropic etching for patterning the intermediate resist layer 9, in the region exposed from the upper resist layer 11 that covers the region where the wiring 2 and the electrode 3 are formed, the filler 9A serves as a mask to form a fine pattern. A pattern is formed. When the lower resist layer 10 is anisotropically etched using the intermediate resist layer 9 as a mask, and the conductive layer is etched using the patterned lower resist layer 10 as a mask,
A predetermined wiring 2 or electrode 3 pattern is formed, and a fine columnar dummy pattern 8 made of the same conductive layer is formed. In FIG. 1, for convenience of explanation, the wiring 2 or the electrode 3 and the dummy pattern 8 are
Although the intermediate resist layer 9 and the upper resist layer 11 are depicted as remaining, at least the upper resist layer 11 does not exist at a stage immediately after the wiring 2 and the like are patterned in the actual process.

According to the above method, the wiring 2 or the electrode 3
Since the dense dummy patterns 8 are formed in a region between them in a self-aligned manner in accordance with the pattern, the amount of data accompanying the design of the dummy pattern 8 does not increase. Similar to the conventional dummy pattern 7 spread between the wiring 2 and the electrode 3 (see FIG. 4), the flattening effect is maintained by the dummy pattern 8 according to the method of the present invention, but the conventional dummy pattern 7 is spread. Since the porosity is higher than in the case, the parasitic capacitance is reduced.

[0011]

EXAMPLE FIG. 2 is a cross-sectional view for explaining a process of an example of the present invention. As shown in FIG. 2A, a semiconductor substrate 1 is covered with an insulating layer (not shown). Conductive layer 6 made of, for example, aluminum and having a thickness of about 1 μm, lower resist layer 10 made of photoresist, for example, an aqueous solution of silicic acid called spin-on-glass (SOG), having a thickness of about 0.1 μm. After the resist layer 9 and the upper resist layer 11 made of photoresist are sequentially applied, the upper resist layer 11 is patterned into a shape corresponding to an electrode or a wiring. For the intermediate resist layer 9, for example,
Spherical filler 9A made of SiO ₂ with a diameter of about 1000Å
Are dispersed. The mixing ratio of the filler 9A in the intermediate resist layer 9 is about 70% by weight.

Then, as shown in FIG. 1B, the intermediate resist layer 9 is anisotropically etched using the upper resist layer 11 as a mask. This etching is, for example, reactive ion etching (R) using a mixed gas of CF ₄ and CHF ₃ as an etchant.
IE) method, pressure 0.2 Torr, high frequency power 450W. As a result, in the region exposed from the upper resist layer 11, the SOG layer forming the intermediate resist layer 9 is etched, but the filling material 9A is not etched, and the SOG layer in the shaded portion of the filling material 9A is also etched. Layers remain.

Next, after removing the upper resist layer 11, the lower resist layer 10 is anisotropically etched using the intermediate resist layer 9 as a mask, as shown in FIG. This etching is performed at a high frequency power of 300 W by the RIE method in an oxygen atmosphere with a pressure of 0.04 Torr.

Next, the conductive layer 6 is anisotropically etched using the patterned lower resist layer 10 as a mask. This etching of the conductive layer 6 is performed by using the intermediate resist layer 9
May be left as it is, or may be performed after the intermediate resist layer 9 is removed. As a result, the figure
As shown in (d), the wiring 2 or the electrode 3 made of the conductive layer 6 and the dummy pattern 8 are formed.

After the above, the wiring 2 is formed by the well-known CVD method.
Alternatively, a planarizing layer 4 made of, for example, phosphosilicate glass (PSG), which covers the electrodes 3 and the dummy patterns 8, is deposited. Then, a contact hole that exposes a part of the predetermined wiring 2 or electrode 3 is formed in the flattening layer 4, and then the flattening layer 4 is formed.
A conductive film made of, for example, aluminum is deposited thereon, and the conductive film is patterned to form the upper wiring 5.

The filler 9A is preferably prepared by hydrolyzing a metal or semiconductor alkoxide represented by the general formula M (0R) _n with an organic alkali as a catalyst. Where M is a metal or semiconductor atom with a valence of n,
R represents an alkyl group. Taking tetraethoxysilane Si (OC ₂ H ₅ ) ₄ which is an alkoxide of silicon as an example, hydrolysis is carried out under pressure using, for example, hydrazine (NH ₂ ) ₂ as an organic alkali of a catalyst. As a result, Si (OC ₂ H ₅ ) ₄
Spherical SiO ₂ particles are generated by the reaction of + 2H ₂ O → SiO ₂ + 4C ₂ H ₅ OH. By such preparation method, contamination of the filler with sodium can be avoided.

Needless to say, the application of the present invention is not limited to the materials of the filler and other layers or films described in the above embodiments.

[0018]

According to the present invention, the flattening effect of the dummy pattern can be sufficiently exhibited without increasing the parasitic capacitance, and the performance of the high-density integrated circuit requiring fine multilayer wiring can be improved. Has the effect of Further, conventionally, the position where the dummy pattern as described above is provided cannot be determined until the pattern design for the electrode or wiring is completed, so standardization is difficult. Therefore, since it is necessary to set the position of the dummy pattern every time the pattern of the electrode or wiring changes, the amount of data regarding the placement of the dummy pattern cannot be ignored. On the other hand, according to the present invention, since the dummy patterns are formed in a self-aligned manner corresponding to the wirings and electrodes, the pattern data is not increased and the pattern design cost is reduced and the throughput is improved. Further, conventionally, in order to avoid an increase in parasitic capacitance, misalignment of the pattern as in the case of forming such a dummy pattern with an insulating layer does not occur, and therefore, it is also effective in improving the manufacturing yield.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a process explanatory view of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of conventional problems (No. 1)

FIG. 4 is an explanatory diagram of a conventional problem (No. 2)

[Explanation of symbols]

 1 Semiconductor Substrate 7, 8 Dummy Pattern 2 Wiring 9 Intermediate Resist Layer 3 Electrode 9A Filler 4 Flattening Layer 10 Lower Layer Resist Layer 5 Upper Layer Wiring 11 Upper Layer Resist Layer 6 Conductive Layer

Claims (3)

[Claims] 1. A step of forming a conductive layer on one surface of a semiconductor substrate covered by an insulating layer and then applying a lower resist layer on the conductive layer, and a granular filler made of a material having etching resistance. Applying the dispersed intermediate resist layer onto the lower resist layer; forming an upper resist layer having a pattern corresponding to a desired wiring or electrode on the intermediate resist layer; and masking the upper resist layer As a result, a first anisotropic etching is performed on the intermediate resist layer to leave the filler and the intermediate resist layer in a shaded portion of the filler in a region exposed from the upper resist, and then the upper resist. A step of removing the layer, and using the intermediate layer and the filler existing on the surface of the substrate from which the upper resist layer has been removed as a mask, a second anisotropic layer with respect to the lower resist layer. And a step of forming the wiring or electrode by subjecting the conductive layer to third anisotropic etching using the lower resist layer subjected to the second anisotropic etching as a mask. And a step of forming an insulating layer covering the surface of the substrate on which the wiring or the electrode is formed, the method of manufacturing a semiconductor device. 2. The intermediate resist layer has a diameter of 20 nm to 20 nm.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the filler having a spherical shape of 0 nm is contained in a weight ratio of 50% to 90%. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the filler is prepared by hydrolyzing a metal or semiconductor alkoxide with an organic alkali as a catalyst.