JPH04142065A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a layer insulating film whose film thickness is proper and to flatten its surface by a method wherein a first SOG film is etched by making use of a resist film pattern as a mask, the SOG film on an interconnection layer is removed and the interconnection layer is revealed. CONSTITUTION:A semiconductor substrate 11 where interconnection layers 13, 14 are formed so as to be protrusion-shaped is coated with a first spin-on- glass(SOG) film 15; the film is solidified. Then, a resist filmpattern 17 whose pattern is reverse to an interconnection pattern is formed. The first SOG film 15 which is revealed is etched and removed by making use of the pattern as a mask; the interconnection layers 13, 14 are revealed. In this manner, after the first SOG film 15 is applied, the first SOG film which has become a protrusion shape is removed, and uneven parts on the surface are once reduced. Thereby, a second SOG film 18 is applied and a insulating film whose surface is flattened can be formed.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for forming a glabellar insulating film among semiconductor device manufacturing methods, the purpose is to form a glabellar insulating film with an appropriate thickness and to flatten its surface. and a step of applying and solidifying a first SOG film on a semiconductor substrate including a wiring layer formed in a convex shape, and then forming a resist film pattern having a pattern shape opposite to that of the wiring layer pattern. step, then, using the resist film pattern as a mask, the first
a step of etching the first SOG film on the wiring layer to expose the wiring layer; and a step of applying and solidifying a second SOG film on the entire surface. It is characterized by being

[Industrial application field]

The present invention relates to a method of forming an interlayer insulating film among methods of manufacturing a semiconductor device.

Semiconductor devices such as LSIs have become highly dense and highly integrated, and a large number of semiconductor elements are provided on a semiconductor substrate, and wiring to connect them is formed in multiple layers, such as two or three layers. The formation method for flattening the glabellar insulating film provided between the wiring lines is particularly important.

[Prior art and problems to be solved by the invention] Now, the reliability of semiconductor devices is greatly related to the reliability of wiring that can cause disconnections and short circuits. It's important. Conventionally, the general method for forming an interlayer insulating film is to form the surface as flat as possible and then provide wiring on that flat surface. This is because the thickness of the wiring becomes uniform, and disconnections and short circuits can be reduced.

Therefore, tSOG (
A method of applying a spin-on-glass (Spin On Glass) film, a method of applying a resist or the like and performing an etch hack under conditions where the etching rate is equal to that of the insulating film (equal etch rate condition), and a combination of these methods are known.

Here, the SOG film is spin-on glass
This is an insulating film in which silanol is dissolved in an organic solvent containing alcohol as a main component, and when this is applied and heat treated, the solvent scatters and only the SiO□ film is fixed.

However, as layer integration and miniaturization have recently progressed, the rough density and area (width) of the underlying wiring patterns have affected the surface of the applied SOG and resist, leaving unevenness and flatness. Problems such as insufficient properties occur due to the high viscosity of SOG and resist.

FIG. 3 is a diagram illustrating the problem, and FIG. 3(a) shows a state where the flatness is insufficient due to the influence of the coarse density and pattern width of the wiring pattern.

In the figure, symbol 1 is a semiconductor substrate, 2 is an insulating film, 3.4 is an aluminum wiring, and 5 is a solidified SOG film, but a thick SOG film is formed on the wide aluminum wiring 3, and the width is narrow. A thin SOG film is formed on the aluminum wiring 4.

In order to improve this flatness, it is possible to thicken these coating films, but if the interlayer insulating film is formed too thick, it will be difficult to form through holes (upper and lower connection holes). It also becomes difficult to fill the wiring material, which reduces reliability. In addition, a thick glabellar insulating film increases the difference in film thickness, making the manufacturing method difficult, which also causes a problem of reduced reliability.

Therefore, one possible method for flattening the glabella insulating film formed of the SOG film is to provide a dummy wiring pattern.
A sectional view thereof is shown in FIG. 3(b). Symbol 6 in the diagram
is a dummy wiring pattern, and when this dummy wiring pattern 6 is made of aluminum (^l) and PSG
There are two methods: one is made of an insulating film deposited by CVD (chemical vapor deposition), such as a phosphorus silicate glass film, and the other is a phosphorus silicate glass film. If the former is made of aluminum, the wiring becomes complicated and short circuits between the wirings increase, and the wiring capacitance increases, deteriorating high-speed operation characteristics, and furthermore, automated wiring becomes difficult. happens.

On the other hand, when creating with a CVD insulating film such as PSG film, C
The deposition process using the VD method and the patterning process of the dummy pattern are increased, and there is also a risk of positional deviation, which may even lead to a decrease in reliability.

Furthermore, the CVD insulating film is likely to be made of the same material as the underlying insulating film 2 on which the wiring layer is provided, and over-etching is likely to occur in the patterning process of a dummy pattern made of this material.

The present invention proposes a manufacturing method aimed at forming a glabellar insulating film with an appropriate thickness that does not cause such problems, and flattening the surface thereof.

[Means to solve the problem]

The problem is that wiring layers 13 and 14 formed in a convex shape on the insulating film 12 are
a step of applying and solidifying a first SOG film 15 on the semiconductor substrate 11 containing the wiring layer pattern; a step of forming a resist film pattern 17 having a pattern shape opposite to that of the wiring layer pattern; Using the resist film pattern as a mask, the first
5OGII 115 is etched to form the wiring layer 13.
．． The problem is solved by a manufacturing method that includes a step of removing the first 5OGWi on 14 to expose the wiring layer, and then a step of applying and solidifying the second 5OGWi on the entire surface.

[Operation] That is, in the present invention, the first SOG film 15 is coated and solidified on the semiconductor substrate 11 on which the wiring layers 13 and 14 are formed in a convex shape, and then a pattern opposite to the wiring layer pattern is formed. A resist film pattern 17 is formed, and using this as a mask, the exposed first SOG film 15 is etched and removed to expose the wiring layers 13 and 14.
This is to reduce the unevenness of the surface by removing the convex first SOG film 18 after depositing the SOG film 18, and then depositing the second SOG film 18 to make the surface extremely flat. Forms an insulating film between the eyebrows.

[Example] Hereinafter, a detailed explanation will be given by way of example with reference to the drawings. FIGS.

Refer to FIG. 2(a); A wide aluminum wiring 13 and a narrow aluminum wiring 14 are provided on a semiconductor substrate 11 with an insulating film 12 interposed therebetween, and a film thickness of 1 μm is formed on the upper surface thereof.
The PSG film 19 is grown to a certain extent. The PSG film is grown by CVD at normal pressure or reduced pressure using a reaction gas containing monosilane, disilane, and phosphine.

Refer to FIG. 2(b); Next, the first SOG film 15 is applied and heat-treated at a temperature of 350 to 450''C for 30 minutes (
annealing) and solidify. The solidified first SO
The thickness of the G film 15 is approximately 0.5 μm.

Refer to FIG. 2(C) - Then, on the first SOC film 15, a resist film pattern 17 having a pattern opposite to that of the aluminum wiring is formed.

That is, the first SOG film 15 deposited on the aluminum wiring 13, 14 is exposed, and other parts of the first SOG film 15 are exposed.
This is a resist film pattern covering the film 15.

See FIG. 2(d); then, the resist film pattern 1
7 as a mask, the first SOG film 15 is etched and removed by RIE (reactive ion etching) method.
The PSG film 19 on the aluminum interconnections 13 and 14 is exposed. This RIE method is CFa:02=400sccm
: 40 sccm of mixed gas is introduced, and the degree of decompression is 0.
The temperature is set to about 3 Torr and the power is 200W.

Since the SOG film and the PSG film have slightly different etching rates, only the SOG film can be removed. After this etching, the resist film pattern 17 is removed.

See FIG. 2(e); next, a second SOG film 18 is applied and solidified by heat treatment under the same conditions as above.

The second SOG film 18 is also formed to have a thickness of about 0.5 μm.

(See Figure 2); Next, the entire surface is etched by RIE to remove a thickness of about 1 μm. To do this, both the SOG film and the PSG film must be etched at the same time, so conditions (conditions such as mixed gas ratio, degree of depressurization, power, etc.) are provided so that the etching rates of the SOG film and the PSG film are approximately equal. do. Then, approximately half of the thickness of the PSG film 19 is etched and exposed on the aluminum wiring 1314, and SO is formed in the gaps between the wiring patterns.
An insulating film is formed with the G film exposed, and its surface becomes extremely flat.

Next, a PSG film 20 with a thickness of 0.5 μm is grown thereon by the CVD method.

As a result, the interlayer insulating film consisting of the PSG film and the SOG film becomes extremely planarized, and the thickness of the film on the wiring is 1 μm.
Only PSG films 19.20 m thick are stacked, and the wiring gap (
In the gap between wiring patterns), PSG with SOG film sandwiched between
IIi19.20 is formed. Currently, the film quality of the PSG film is slightly better than that of the SoG film, so it can be said that forming the film by the above-described method using the principles of the present invention is an excellent method.

In addition, in the formation method according to the present invention, when a PSG film is used instead of the SOG film, the PSG film has good covering properties and covers with the uneven shape remaining, and it is also possible to use a PSG film that is made of the same material as the underlying insulating film. Therefore, when patterning is performed with the resist film pattern 17 shifted in position, there is a drawback that over-etching is likely to occur. Therefore, it is optimal to use an insulating film (SOG film) that is coated with a liquid and then solidified.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the surface of the glabella insulating film is extremely flattened, thereby maintaining the reliability of semiconductor devices such as LSIVLSI, which are increasingly integrated and miniaturized to form multilayer wiring.・It has a great effect on improvement.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are principle diagrams, FIGS. 2(a) to (g) are cross-sectional views of the forming method according to the present invention, and FIGS. 3(a) and (b) are conventional It is a figure explaining a problem. In the figure, 1.11 is a semiconductor substrate, 2.12 is an insulating film, 3, 4.13.14 is aluminum wiring, and 5 is SOG
6 is a dummy wiring pattern, 15 is a first SOG film, 17 is a resist film pattern, 18 is a second SOG film, and 19 and 20 are PSG films. 17 Len ZFIli-＼苧〉 Thick r￥ ■ No. Ill No. 2 (Second 2) 6 Dummy worry soft orgasm and rush to play ttifl throat Tj No. 3

Claims (1)

[Claims] A step of applying and solidifying a first SOG film on a semiconductor substrate including a wiring layer formed in a convex shape, and then a resist film having a pattern shape opposite to that of the wiring layer pattern. a step of forming a pattern, and then using the resist film pattern as a mask to form the first pattern.
a step of etching the first SOG film on the wiring layer to expose the wiring layer; and a step of applying and solidifying a second SOG film on the entire surface. A method of manufacturing a semiconductor device, comprising: