JP3841345B2 - Method for forming fine pattern of semiconductor element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a fine pattern of a semiconductor device, and more particularly to a method for forming a fine pattern of a semiconductor device capable of forming a fine pattern corresponding to high integration.
[0002]
[Prior art]
FIG. 1 is a cross-sectional view for explaining a conventional method for forming a fine pattern of a semiconductor device.
[0003]
First, the conductive film 20 and the photosensitive film 30 are sequentially formed on the first insulating film 10. Next, after patterning the photosensitive film 30 so that the pitch becomes (α + β), the conductive film 20 is locally dry etched using the photosensitive film 30 as a mask, and then the photosensitive film 30 is removed to form a pattern. To do.
[0004]
In general, much investment and efforts are made to form ultrafine patterns for realizing miniaturization of semiconductor devices, but it is difficult to obtain an accurate pattern size.
[0005]
For example, if the pattern pitch is 0.20 μm, a fine pattern composed of a wiring having a width of 0.10 μm and a spacing having a width of 0.10 μm must be formed. Currently, such a pattern pitch of 0.20 μm is realized using an ArF device and a photoresistor (PR).
[0006]
In addition, in order to realize a pattern pitch of 0.40 μm, a KrF device and a KrF photoresistor (PR) are used.
[0007]
[Problems to be solved by the invention]
However, in the conventional method for forming a fine pattern of a semiconductor device, a pattern having a pitch of 0.20 μm is created by using equipment (KrF) that realizes a pattern pitch of 0.40 μm and a photoresistor (PR) for KrF. I couldn't.
[0008]
Accordingly, the present invention has been made to solve the above-described problems, and enables the formation of a fine pattern corresponding to high integration by using two substances having a large dry etching selectivity, thereby reducing the production cost. It is an object to provide a method for forming a fine pattern of a semiconductor device that can be reduced.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, in a method for forming a fine pattern of a semiconductor element having a pitch size of (α + β), a step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate; Forming a photosensitive film having a predetermined shape having a pitch size twice the pitch size of (α + β) on the second insulating film; and dry etching the second insulating film using the photosensitive film as a mask; Removing the photosensitive film; forming a third insulating film on the entire surface of the semiconductor substrate including the remaining second insulating film; and the remaining second on the resultant structure. The fourth insulating film is formed in a portion corresponding to between each of the insulating films so that the position of the bottom of the fourth insulating film partially overlaps the position of the top of the second insulating film. A third insulating film and a fourth insulating layer; A step of performing a first planarization process by a method in which a dry etching selectivity to the film is 1: 1 and interrupting the etching when the second insulating film is exposed; and the remaining fourth Etching the third insulating film using the insulating film and the second insulating film as a mask to form a third insulating film pattern, and forming the second insulating film and the third insulating film After the space is filled with the conductive film, a second planarization process is performed on the conductive film to form conductive film wiring having a pitch size of (α + β).
[0010]
The first planarization process is preferably performed by an etch back process.
[0011]
The second planarization process is preferably performed by a chemical mechanical polishing (CMP) process or an etch back process.
[0012]
The above objects and other features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the present invention.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
2 to 6 are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
[0014]
FIG. 2 is a view in the middle of a process for finally obtaining the same pattern pitch as the pattern shown in FIG. 1, and a first insulating film 1 and a second insulating film are formed on a semiconductor substrate (not shown). It is a figure which shows the state in which the film pattern 2 and the photosensitive film pattern 3 were formed. As shown in FIG. 2, first, a first insulating film 1 and a second insulating film are sequentially formed on a semiconductor substrate (not shown), and then a photosensitive film pattern having a predetermined shape is formed on the second insulating film. 3 is formed. At this time, the pattern pitch of the photosensitive film pattern 3 is twice the pattern pitch (α + β) shown in FIG. 1 (α is a wiring width and β is a spacing width between adjacent wirings). It is patterned to become. Thereafter, the second insulating film is dry etched to form a second insulating film pattern 2. At this time, in order to adjust the critical dimension (CD) based on the thickness of the third insulating film, the thickness of the second insulating film is much thicker than the thickness of the third insulating film to be formed later. Is done.
[0015]
Thereafter, as shown in FIG. 3, after removing the photosensitive film pattern 3, a third insulating film 4 is deposited thereon, and a fourth portion is formed in a predetermined portion between the second insulating film patterns 2. The insulating film 5 is formed. Specifically, the fourth insulating film 5 is formed on the surface of the third insulating film 4 which is the surface of the resultant structure, at a position corresponding to the upper part of each intermediate position of the adjacent second insulating pattern 2. Is formed. At this time, the position of the bottom of the fourth insulating pattern 5 is set so as to partially overlap the position of the top of the second insulating pattern 2.
[0016]
Subsequently, a planarization process by chemical mechanical polishing (CMP) is performed on the surfaces of the third and fourth insulating films 4 and 5.
[0017]
Thereafter, as shown in FIG. 4, the second insulating film is formed by a method in which the dry etching selectivity between the third insulating film 4 and the fourth insulating film 5 is 1: 1. Etch back only a predetermined thickness until 2 is exposed. At this time, the fourth insulating film 5 remains in the third insulating film 4.
[0018]
After that, the technique is changed to use a technique in which the fourth insulating film 5 and the second insulating film 2 realize etching (10: 1 or more) with a high selectivity with respect to the third insulating film 4. Then, the third insulating film 4 is etched. As a result, since the third insulating film 4 is etched faster than the fourth insulating film 5 and the second insulating film pattern 2, the third insulating film under the fourth insulating film 5 is etched. Remains to form the third insulating film pattern 4a. Thereafter, the fourth insulating film 5 acting as a mask is removed by the above-described 1: 1 method.
[0019]
As shown in FIG. 6, after a conductive film (not shown) is filled between the second insulating film pattern 2 and the third insulating film pattern 4a finally left in FIG. Then, a planarization process is performed by a chemical mechanical polishing (CMP) process or an etch back process. Thereafter, if the remaining second insulating film 2 and third insulating film 4 are removed, conductive film wiring 6 having a pattern pitch substantially as shown in FIG. 1 is formed.
[0020]
【The invention's effect】
As described above, in the method for forming a fine pattern of a semiconductor device according to the present invention, it is possible to form a fine pattern corresponding to high integration by using two substances having a large dry etching selectivity. As a result, the production cost of the semiconductor device can be reduced.
[0021]
The above-described embodiments have been disclosed for the purpose of illustrating the present invention, and those skilled in the art can make various modifications, changes, additions and the like within the scope of the spirit of the present invention. Modifications, etc. should be viewed as belonging to the claims.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a method for forming a fine pattern of a semiconductor device according to a conventional technique. FIG. 2 is a cross-sectional view for explaining a process of a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view for explaining a process of a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view for explaining the steps of the method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention. It is sectional drawing for demonstrating the process of the formation method of the fine pattern of a semiconductor element.
DESCRIPTION OF SYMBOLS 1 1st insulating film 2 2nd insulating film 3 Photosensitive film 4 3rd insulating film 5 4th insulating film 6 Conductive film wiring

Claims (4)

In a method for forming a fine pattern of a semiconductor element having a pitch size of (α + β),
Sequentially forming a first insulating film and a second insulating film on a semiconductor substrate;
Forming a photosensitive film having a predetermined shape on the second insulating film having a pitch size that is twice the pitch size of (α + β);
Dry etching the second insulating film using the photosensitive film as a mask;
Removing the photosensitive film;
Forming a third insulating film on the entire surface of the semiconductor substrate including the remaining second insulating film;
On the resultant structure, the position of the bottom of the fourth insulating film partially corresponds to the position of the top of the second insulating film at portions corresponding to each of the remaining second insulating films. Forming the fourth insulating film so as to overlap ;
The first planarization process is performed by a technique in which the dry etching selectivity between the third insulating film and the fourth insulating film is 1: 1, and the etching is performed when the second insulating film is exposed. The stage of interrupting,
Etching the third insulating film using the remaining fourth insulating film and the second insulating film as a mask to form a third insulating film pattern;
After filling the space between the second insulating film and the third insulating film with a conductive film, the conductive film is subjected to a second planarization step and has a pitch size of (α + β). A method for forming a fine pattern of a semiconductor device, comprising the step of forming a wiring.   The method for forming a fine pattern of a semiconductor device according to claim 1, wherein the first planarization step is performed by an etch-back step.   The method for forming a fine pattern of a semiconductor device according to claim 1, wherein the second planarization process is performed by a chemical mechanical polishing (CMP) process.   2. The method of forming a fine pattern of a semiconductor device according to claim 1, wherein the second planarization step is performed by an etch back step.

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