JP3191769B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a manufacturing method thereof a semiconductor device, and more particularly to a method of manufacturing a semiconductor equipment having a fine wiring pattern formed by the photolithography technique.

[0002]

2. Description of the Related Art A conventional pattern forming method for a semiconductor device will be described with reference to FIGS. FIG. 7 is a plan view of a wiring pattern of a conventional semiconductor device, and FIGS. 8A and 8B are cross-sectional views taken along lines AA 'and BB' in FIG. 7, respectively. First, a first insulating film 200 such as silicon oxide is formed over a semiconductor substrate (not shown), and then a metal layer such as aluminum is formed over the first insulating film 200 by a sputtering method or the like. Then, a first wiring pattern 201 is formed. Next, after a second insulating film 202 of silicon oxide or the like is formed on the entire surface of the semiconductor substrate, a contact hole 2 reaching the surface of the first wiring pattern is formed at the contact hole forming portion of the second insulating film 202.
After forming a metal layer such as aluminum on the second insulating film 202 including the contact hole 204 by sputtering, a second layer is formed by photolithography etching.
By forming the wiring pattern 203, a wiring structure including the first wiring pattern 201, the second wiring pattern 203, and the contact hole 204 is formed.

[0003]

The miniaturization of the wiring pitch has become more and more important with the progress of higher density and higher functionality of the semiconductor device. Has become difficult. That is, in the above prior art, if the wiring pattern formation limit of the photolithography is d1, as shown in FIG.
The total of the wiring pattern 201 and one interval therebetween is 3
d1 and cannot be smaller than this value.

Various techniques have been proposed to solve the above-mentioned problems of the conventional wiring pattern forming technique for semiconductor devices. For example, Japanese Patent Laid-Open No. 1-181546 discloses the following wiring pattern forming technique. Have been. That is, in this technique, first, an aluminum layer is deposited on an insulating film such as silicon nitride formed on a semiconductor substrate, and the aluminum layer is dry-etched using the first photoresist pattern as a mask to form a predetermined wiring pattern. Also forms a wide wiring pattern. A second photoresist pattern is formed between the wide wiring patterns so as to cover a part of the wiring pattern, and is then dry-etched to make the wide wiring pattern finer.

However, in this technique, the second
In order to form the photoresist pattern, the number of times the lithography technique is used increases. In general, the lithography process has a higher manufacturing cost than other processes such as film formation and etching. Therefore, the technique disclosed in Japanese Patent Application Laid-Open No. 1-181546 has a problem that the manufacturing cost is high.

Another example of a technique for miniaturizing a wiring pattern of a semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 2-89319. In this technique, an overetching pattern of tungsten metal is formed on an insulating film of silicon oxide or the like of a silicon substrate using silicon nitride as a mask, and aluminum wiring is grown on side surfaces of the overetching pattern. A method for forming a fine aluminum wiring pattern by removing the aluminum wiring pattern is disclosed. In this technique, there is a problem that it is difficult to control the over-etching amount of tungsten with high accuracy, and the variation in the width of the aluminum wiring becomes large.

[0007] The present invention aims at resolving the above-mentioned problems of the prior art, to provide a method of manufacturing a semiconductor equipment having a wiring pattern below the limit of the width of the photolithographic technique.

[0008]

Means for Solving the Problems] This onset Ming, a first wiring pattern formed on the first insulating film on a semiconductor substrate,
A second insulating film formed on the first insulating film including the first wiring pattern, a second wiring pattern formed on the second insulating film, and the first wiring pattern Semiconductor device having a wiring structure composed of and a contact hole for electrically interconnecting the second wiring pattern
, Comprising the following configuration .

That is, the method of manufacturing a semiconductor device according to the present invention comprises:
Forming a first wiring pattern by coating and patterning a first wiring layer on a first insulating film formed on the semiconductor substrate; and forming a first wiring pattern on the semiconductor substrate including the first wiring pattern. Forming the second insulating film; and forming the first insulating film on a predetermined portion of the second insulating film on the first wiring pattern.
Forming a first opening penetrating through the first wiring pattern, and simultaneously dividing the predetermined wiring pattern of the first wiring pattern into a portion of the second insulating film other than the first opening forming portion to form a fine pattern. Forming a second opening to be converted, forming a third insulating film so as to completely fill the second opening and form a recess in the first opening, Removing the third insulating film so as to leave the third insulating film only in the opening, and exposing the first wiring pattern only in the first opening; and Forming a second wiring pattern by coating a second wiring layer on the second insulating film and patterning the second wiring layer.

In the method of manufacturing a semiconductor device according to the present invention, the second opening is formed simultaneously with the formation of the first opening penetrating the first wiring pattern for contact between the first wiring pattern and the second wiring pattern. By forming the first wiring pattern so as to be divided, a fine wiring pattern can be formed without increasing the number of times of photolithography. In particular, in the present invention, the width d2 of the first wiring pattern before being divided by the second opening and the width d1 of the second opening are designed to have a relationship of d1 <d2 <3d1, and d1
Is the limit width of photolithography, there is an effect that the first wiring pattern can be divided into widths smaller than d1.

[0011]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a state after forming a wiring pattern of a main part of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 2 to 6 are cross-sectional views of a main part of the semiconductor device for explaining a wiring pattern forming process sequence in the method of manufacturing a semiconductor device according to the embodiment of the present invention. ) Are cross-sectional views along the line AA ′ and the line BB ′ in FIG. 1, respectively.

In FIG. 1, reference numeral 101 denotes a first wiring pattern, reference numeral 107 denotes a second wiring pattern, and reference numeral 105 denotes a first wiring pattern.
Is a first opening for forming a contact hole for electrically connecting the first and second wiring patterns. Also, reference numeral 1
03 is a second opening formed in the first wiring pattern at the same time when the first opening 105 is formed. This second opening 103 is not used to electrically connect the first wiring pattern 101 and the second wiring pattern 107, but is used to locally pattern the first wiring pattern to a width smaller than the limit of the photolithography technique. It is for. The second
1 is finally buried with an insulating film.
In the figure, all the insulating films are omitted so that the positional relationship between each wiring pattern and each opening can be understood.

In FIG. 1, when minimizing the wiring pitch in the AA ′ portion, assuming that the limit dimension of the photolithography technique is d 1, the second opening formed at the same time as the first opening 105 is formed. The width of the opening 103 is d1, and
Before the second opening 103 is formed, the width d2 of the first wiring pattern 101 can be set to d1 <d2 <3d1. Therefore, in the present invention, it is possible to form a wiring having a width equal to or less than the limit of the photolithography technology and to reduce the wiring pitch.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2, a first insulating film 100 is formed on a main surface of a semiconductor substrate (not shown here), and a metal layer mainly composed of, for example, 500 nm thick is formed thereon. The first wiring pattern 101 is formed by coating and patterning into a desired pattern by a photolithography technique and an anisotropic dry etching technique.

Here, the wiring width d2 of the first wiring pattern in FIG. 2A is set to d1 <d2 <3d1, where the limit dimension of the photolithography technique is d1. Here, for convenience, in the present embodiment, d2 =
It is assumed to be 2.4d1. In FIG. 2, two wires having a wire width d2 are arranged at an interval of d1.

Next, as shown in FIG. 3, after a second insulating film 102 is formed on the first insulating film including the first wiring pattern 101, the second insulating film 102 and the first wiring pattern are formed. 101 is formed by anisotropic dry etching technique and photolithography technique with the second opening 103 of FIG.
The portion corresponding to the opening 105 is patterned. Here, in FIG. 3A, the first wiring pattern 101 is patterned by the second opening 103 having the limit dimension d1 of the photolithography technique, and the width d2 = 2.4d.
The two first wiring patterns 101 become four fine wiring patterns 104 having a width of 0.7d1 which are electrically separated at intervals of d1.

On the other hand, as shown in FIG. 3B, a first opening 1 for forming a contact hole for electrically connecting a second wiring pattern formed later and the first wiring pattern is formed.
Reference numeral 05 denotes a width d3 (d3> d1), and in this portion, the central portion of the first wiring pattern 101 (the first opening 1).
05) has a hollowed out shape.

Next, as shown in FIG. 4, for example, when the thickness is d1 /
A third insulating film 106 having a thickness of 2 or more and less than d3 / 2 is formed.
Here, the second opening 103 is completely buried in the third insulating film 106, and the first opening 105 is not completely buried in the third insulating film 106.

Thereafter, as shown in FIG. 5, the third insulating film 106 is subjected to isotropic wet etching back to form the second insulating film 1.
02 is exposed. Here, the third insulating film 106 is buried only in the concave portion of the second opening 103 and remains. In the first opening 105, the side wall of the first wiring pattern 101 is exposed. Note that the third insulating film 106 and the second insulating film 102 are formed of a similar film containing, for example, a silicon oxide film as a main component, and the above wet etch back may be performed by time control. Further, a different kind of film such as a silicon oxide film is formed on the second insulating film 102 and a silicon nitride film is formed on the third insulating film 106, and the third insulating film 1 is selectively formed.
06 may be etched only.

Next, as shown in FIG.
By covering a semiconductor substrate with a metal layer mainly composed of aluminum of 0 nm and patterning it into a desired pattern, a second wiring pattern 107 is formed, and interconnected two-layer wiring having a desired configuration is formed. A structure is formed.
In the wiring section of FIG.
A first wiring pattern 101 is divided on the insulating film 100, and a fine wiring pattern 104 having a width smaller than a critical dimension of the photolithography technique is provided. The surface thereof is covered with a second insulating film 102, and the fine wiring pattern is further formed. Pattern 104
Are partially electrically separated from each other by a third insulating film 106 burying the second opening 103 formed simultaneously with the first opening 105. FIG.
In the contact hole 108 shown in FIG. 2B, the first wiring pattern 101 and the second wiring pattern 107 are formed by the first opening 105 having a dimension d3 (d3> d1) slightly larger than d1. The side walls of the opening 105 are electrically connected.

[0023]

The effect of the present invention is that part of the patterning of the first wiring pattern is performed at the time of forming the first opening in the subsequent process, so that the first wiring pattern can be formed without an additional photolithography step. Can be divided into widths equal to or less than the limit of the photolithography technology, and a high-density semiconductor device with a narrow wiring pitch can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state after forming a wiring pattern of a main part of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views of main parts of the semiconductor device for explaining a wiring pattern forming step in the method of manufacturing a semiconductor device according to the embodiment of the present invention; FIGS. It is sectional drawing along the A 'line and the BB' line.

3A and 3B are cross-sectional views of a main part of the semiconductor device for explaining a line pattern forming step subsequent to the wiring pattern forming step of FIG. 2; FIGS. 3A and 3B are AA ′ line and FIG. It is sectional drawing which followed the BB 'line.

FIGS. 4A and 4B are cross-sectional views of main parts of the semiconductor device for explaining a line pattern forming step subsequent to the wiring pattern forming step of FIG. 3; FIGS. It is sectional drawing which followed the BB 'line.

5A and 5B are cross-sectional views of main parts of the semiconductor device for explaining a line pattern forming step following the wiring pattern forming step of FIG. 4; FIGS. 5A and 5B are AA ′ line and FIG. It is sectional drawing which followed the BB 'line.

FIGS. 6A and 6B are cross-sectional views of a main part of the semiconductor device for explaining a line pattern forming step subsequent to the wiring pattern forming step of FIG. 5; FIGS. It is sectional drawing which followed the BB 'line.

FIG. 7 is a plan view of a wiring pattern of a conventional semiconductor device.

8 is a cross-sectional view of the semiconductor device of FIG.
Lines -A 'and (B) are cross-sectional views along line BB'.

[Explanation of symbols]

 100, 200 First insulating film 101, 201 First wiring pattern 102, 202 Second insulating film 103 Second opening 104 Fine wiring pattern 105 First opening 106 Third insulating film 107, 203 Second Wiring pattern 108, 204 Contact hole

Claims (7)

(57) [Claims] A step of forming a first wiring pattern by covering and patterning a first wiring layer on a first insulating film formed on a semiconductor substrate; and forming the first wiring pattern. Forming a second insulating film on the semiconductor substrate and forming a first opening penetrating the first wiring pattern at a predetermined position of the second insulating film on the first wiring pattern; Forming a second opening for dividing the predetermined wiring pattern of the first wiring pattern and miniaturizing the second wiring pattern at a location different from the location where the first opening is formed in the second insulating film; 2 is completely filled, and the first
Forming a third insulating film so as to form a concave portion in the opening, and removing the third insulating film so as to leave the third insulating film only in the second opening. A step of exposing the first wiring pattern only in the first opening, a step of coating the second wiring layer on the second insulating film including the first opening and then patterning the second wiring pattern, Forming a semiconductor device. And wherein the width d2 of the first wiring pattern before being divided by the second opening, the width d1 of the second opening is d1 <d2 <according to claim 1, wherein a relationship 3d1 A method for manufacturing a semiconductor device. Wherein the method of manufacturing a semiconductor device according to claim 1 or 2, wherein the first and second wiring layers is characterized in that it consists of the same material. Wherein said second and third method of any one of a semiconductor device according to claim 1 to claim 3, wherein the insulating film is characterized in that it consists of the same material. 5. A method according to claim 1 to claim wherein the second insulating film a third insulating film is characterized in that it consists of different materials
4. The method for manufacturing a semiconductor device according to claim 3 . Wherein said second producing method of opening any one of the semiconductor device of claims 1 to 5, wherein is formed by anisotropic dry etching. 7. The method of the third insulating film any one of a semiconductor device according to claim 1 to claim 6, wherein is removed by wet etching isotropic.