KR100578222B1 - Improved dual damascene process in semiconductor device - Google Patents

Improved dual damascene process in semiconductor device Download PDF

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KR100578222B1
KR100578222B1 KR1019990024802A KR19990024802A KR100578222B1 KR 100578222 B1 KR100578222 B1 KR 100578222B1 KR 1019990024802 A KR1019990024802 A KR 1019990024802A KR 19990024802 A KR19990024802 A KR 19990024802A KR 100578222 B1 KR100578222 B1 KR 100578222B1
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interlayer insulating
insulating film
dual damascene
etching
etch stop
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KR1019990024802A
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Korean (ko)
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KR20010004182A (en
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권세한
임태정
김상익
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers

Abstract

본 발명은 식각정지층을 이용한 듀얼 대머신 공정을 수행함에 있어, 식각정지층에 대한 층간절연막의 높은 식각선택비를 얻을 수 있어 새로운 장비의 개발 및 구입 없이 고집적소자의 개발을 앞당길 수 있는, 개선된 듀얼 대머신 공정의 반도체소자 제조방법을 제공하는데 그 목적이 있는 것으로, 이를 위한 본 발명의 듀얼 대머신 공정은 소정의 단차 구조물이 형성되어 있는 기판 상에 제1층간절연막을 형성하는 제1단계; 상기 제1층간절연막 상에 식각정지층으로서 금속층을 형성하는 제2단계; 상기 금속막을 선택적으로 식각하여 콘택부위의 상기 제1층간절연막을 노출시키는 제3단계; 상기 제3단계가 완료된 결과물 상부에 제2층간절연막을 형성하는 제4단계; 및 선택적 식각으로 상기 제2층간절연막과 상기 제3단계에서 노출된 부위의 제1층간절연막을 식각하는 제5단계를 포함하여 이루어진다.In the present invention, in performing the dual damascene process using the etch stop layer, it is possible to obtain a high etch selectivity of the interlayer insulating film to the etch stop layer, which can accelerate the development of highly integrated devices without the development and purchase of new equipment. It is an object of the present invention to provide a method for manufacturing a semiconductor device of a dual damascene process. The dual damascene process of the present invention provides a first step of forming a first interlayer dielectric layer on a substrate on which a predetermined stepped structure is formed. ; Forming a metal layer as an etch stop layer on the first interlayer insulating film; Selectively etching the metal layer to expose the first interlayer dielectric layer at a contact portion; A fourth step of forming a second interlayer insulating film on the resultant of the third step; And a fifth step of etching the second interlayer insulating film and the first interlayer insulating film of the portion exposed in the third step by selective etching.

듀얼 대머신 공정, 식각선택비, 식각정지층, 금속Dual machine process, etch selectivity, etch stop layer, metal

Description

반도체소자에서의 개선된 듀얼 대머신 공정{Improved dual damascene process in semiconductor device} Improved dual damascene process in semiconductor device             

도1a 내지 도1c는 종래기술에 따른 듀얼 대머신 공정을 나타내는 공정 단면도,1A to 1C are cross-sectional views illustrating a dual damascene process according to the prior art;

도2a 내지 도2c는 본 발명에 따른 개선된 듀얼 대머신 공정을 나타내는 공정 단면도.2A-2C are process cross-sectional views illustrating an improved dual damascene process in accordance with the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

201, 204 : 층간산화막201, 204: interlayer oxide film

202 : 질화막202: nitride film

203, 205 : 포토레지스트패턴203 and 205: photoresist pattern

206 : 홀206: hall

본 발명은 반도체소자 제조방법에 관한 것으로, 특히 개선된 이중 대머신 공정(Dual Damascene Process)에 관한 것이다.TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improved dual damascene process.

잘 알려진 바와 같이, 메모리소자는 집적도가 매 3년을 주기로 4배씩 증가하다 근래에 dl르러 그 집적도의 증가 주기가 더욱 짧아지고 있으며, 이에 대응하여 0.2㎛ 이하의 디자인 룰(Design Rule)을 요구하는 1Gbit 디램(Dynamic Random Access Memory, 이하 DRAM이라 칭함)을 위한 포토리소그래피 기술이 소개되었다. 그러나 포토리소그래피 기술은 근본적으로 해상력이 한계를 갖게되는바, 이는 해상력이 노광장비인 스텝퍼(stepper)의 광원 파장과 개수구(Numerical Aperture)에 의해 제약받기 때문이다. 한편 화학적기계적폴리싱(Chemical Mechanical Polishing, 이하 CMP라 한다)를 이용한 평탄화의 진보와, PSM(Phase Shift Mask) 및 변형조명 기법 등 초해상기술이 계속 소개되어, 리소그래피 측면에서의 제약요인이 상당히 완화되었다. 그러나, 이러한 성과에도 불구하고 콘택 패턴은 고집적화가 진행될 수록 더작고 더깊은 형태를 요구하게되어 어스펙트 비(Aspect Ratio), 콘택 넓이에 대한 콘택 깊이에 대한 비가 크게 증가하게 되었다. 일예로 1Gbit DRAM의 경우 3층 배선 기술을 적용하더라도 금속콘택에 요구되는 어스펙트 비가 5 이상이 된다. 때문에, 보다 더 어스펙트 비를 줄이기 위해서는 3층 또는 그 이상의 배선 공정이 필요한 바, 이는 공정수의 증가에 따른 많은 문제점이 나타나게 된다.As is well known, memory devices have increased density four times every three years. Recently, the period of increase in density has become shorter, and correspondingly, a design rule of 0.2 μm or less is required. Photolithography technology for 1Gbit DRAM (Dynamic Random Access Memory) is introduced. However, photolithography technology is fundamentally limited in resolution because the resolution is limited by the light source wavelength and the numerical aperture of a stepper, which is an exposure apparatus. On the other hand, advances in planarization using Chemical Mechanical Polishing (CMP) and super-resolution techniques such as phase shift mask (PSM) and deformation lighting techniques have been introduced, which has greatly eased the constraints in lithography. . However, despite these achievements, contact patterns require smaller and deeper shapes as high integration increases, resulting in a significant increase in aspect ratio and contact depth to contact width. For example, in the case of 1Gbit DRAM, the aspect ratio required for the metal contact becomes 5 or more even if the three-layer wiring technology is applied. Therefore, in order to further reduce the aspect ratio, three or more wiring processes are required, which causes many problems due to an increase in the number of processes.

이러한 문제점에 대응하고자 질화막을 식각정지층으로 이용하는 듀얼 대머신 공정이 등장하기에 이르렀는데, 이 역시 소자가 더욱 고집적화되어 가면서 층간산화막의 두께가 증가함에 따라 20:1 이상의 식각선택비를 요구하는 문제가 발생되며 이러한 높은 식각선택비를 얻기에 공정 조건을 확립하는데 많은 어려움이 있다.In order to cope with this problem, a dual damascene process using a nitride film as an etch stop layer has emerged, which also requires an etching selectivity of 20: 1 or more as the thickness of the interlayer oxide film increases as the device becomes more integrated. There are many difficulties in establishing the process conditions in order to obtain such high etching selectivity.

이러한 종래기술의 듀얼 대머신 공정과 그의 문제점을 도1a 내지 도1c를 참조하여 상세히 살펴보도록 한다.The dual damascene process and its problems in the prior art will be described in detail with reference to FIGS. 1A to 1C.

도1a 내지 도1c에는 질화막을 식각정지층으로 이용하는 듀얼 대머신 공정이 도시되어 있다.1A to 1C illustrate a dual damascene process using a nitride film as an etch stop layer.

종래의 듀얼 대머신 공정에 있어서는, 먼저 도1a에 도시된 바와 같이 제1층간산화막(101) 상에 식각정지층으로서 질화막(102)을 형성하고, 이 질화막(102)상에 포토리소그래피 공정에 통해 포토레지스트패턴(103)을 형성한다. In the conventional dual damascene process, first, as shown in FIG. 1A, a nitride film 102 is formed on the first interlayer oxide film 101 as an etch stop layer, and a photolithography process is performed on the nitride film 102. The photoresist pattern 103 is formed.

이어서 도1b에 도시된 바와 같이 상기 포토레지스트패턴(103)을 식각마스크로하여 상기 질화막(102)을 식가하고 상기 포토레지스트패턴(103)을 제거한 다음 그 결과물의 전면에 제2층간산화막(103)을 형성하고, 상기 제2층간산화막(104)에 콘택홀 형성을 위한 포토레지스트패턴(105)을 형성한다.Subsequently, as shown in FIG. 1B, the nitride film 102 is etched using the photoresist pattern 103 as an etch mask, the photoresist pattern 103 is removed, and the second interlayer oxide film 103 is formed on the entire surface of the resultant. And a photoresist pattern 105 for forming a contact hole in the second interlayer oxide film 104.

이어서, 도1c에 도시된 바와 같이 상기 포토레지스트패턴(105)을 식각마스크로하여 상기 제1 및 제2 층간산화막(104, 101)을 식각하여 금속선이 매립될 홀(106)을 형성한다.Subsequently, as shown in FIG. 1C, the first and second interlayer oxide films 104 and 101 are etched using the photoresist pattern 105 as an etching mask to form holes 106 in which metal lines are to be filled.

도면에는 도시되지 않았지만 이후, 결과물 전면에 금속 또는 기타 재질의 전도막을 증착하고 CMP를 실시하므로써 상기 홀(106)에 금속 또는 기타 재질의 전도막이 매립되도록 한다.Although not shown in the drawings, a conductive film of metal or other material is deposited on the entire surface of the resultant, and CMP is performed so that the conductive film of metal or other material is embedded in the hole 106.

그런데, 소자가 더욱 고집적화되어 가면서 층간산화막(104, 101)의 두께가 점차 증가함에 따라 상기 질화막(102)에 대한 상기 산화막(104, 101)의 식각선택비 로서 20:1 이상을 요구하게 되며, 기존의 장비를 사용하여 이러한 높은 식각선택비를 얻기 위한 공정 조건을 확립하는데 많은 어려움이 있다. 또한, 이러한 높은 선택비를 얻기 위해서는 새로운 장비의 구입 또는 개발이 필요한 바, 이러한 점들이 고집적소자의 개발에 많은 제약을 주게 된다. However, as the device becomes more integrated, the thickness of the interlayer oxide films 104 and 101 gradually increases, requiring 20: 1 or more as an etching selectivity ratio of the oxide films 104 and 101 to the nitride film 102. There are many difficulties in establishing process conditions to achieve such high etch selectivity using existing equipment. In addition, in order to obtain such a high selection ratio, it is necessary to purchase or develop new equipment, which places many limitations on the development of the high integration device.

즉, 홀(106) 형성을 위한 산화막(104, 101)의 식각은 산화막 식각장비에서 CxF계 에천트(Etchant)를 사용하게 되는데, 이러한 CxF계 에천트는 질화막도 동시에 식각하므로, 질화막에 대한 산화막의 높은 식각선택비를 얻기가 어렵다. 그러므로, 폴리머(Polymer) 형성 등으로 식각률의 저하를 감수하면서 선택비를 높이는 식각 방법을 개발중이나, 층간산화막 특히 질화막(102) 하부의 층간산화막(101)의 두께가 증가함에 따라 식각 공정시간의 증가로 공정단가의 상승이 불가피하다. 때문에, 간단한 공정으로 질화막에 대한 산화막의 식각선택비를 높이기 위해서는 새로운 장비의 개발 및 구입이 필요시 된다.That is, the etching of the oxide film (104, 101) for a hole 106 forming there is used an etchant (Etchant) to the C x F based on the oxide etching equipment, because these C x F based etchant nitride film is also etched at the same time, the nitride film It is difficult to obtain a high etching selectivity of the oxide film with respect to. Therefore, while developing an etching method for increasing the selectivity while reducing the etching rate due to the formation of a polymer, the etching process time increases as the thickness of the interlayer oxide film 101, especially the interlayer oxide film 101 under the nitride film 102, increases. As such, an increase in process costs is inevitable. Therefore, in order to increase the etching selectivity of the oxide film to the nitride film by a simple process, it is necessary to develop and purchase new equipment.

본 발명은 상기 종래가술의 문제점을 해결하기 위하여 안출된 것으로서, 식각정지층을 이용한 듀얼 대머신 공정을 수행함에 있어, 식각정지층에 대한 층간절연막의 높은 식각선택비를 얻을 수 있어 새로운 장비의 개발 및 구입 없이 고집적소자의 개발을 앞당길 수 있는, 개선된 듀얼 대머신 공정의 반도체소자 제조방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the problems of the conventional technique, in performing the dual damascene process using the etch stop layer, it is possible to obtain a high etch selectivity of the interlayer insulating film to the etch stop layer of the new equipment It is an object of the present invention to provide a method for manufacturing a semiconductor device of an improved dual damascene process that can accelerate the development of a high integration device without development and purchase.

상기 목적을 달성하기 위하여 본 발명은 식각정지층을 사용하는 듀얼 대머신 공정을 적용한 반도체소자 제조방법에 있어서, 소정의 단차 구조물이 형성되어 있는 기판 상에 제1층간절연막을 형성하는 제1단계; 상기 제1층간절연막 상에 식각정지층으로서 금속층을 형성하는 제2단계; 상기 금속막을 선택적으로 식각하여 콘택부위의 상기 제1층간절연막을 노출시키는 제3단계; 상기 제3단계가 완료된 결과물 상부에 제2층간절연막을 형성하는 제4단계; 및 선택적 식각으로 상기 제2층간절연막과 상기 제3단계에서 노출된 부위의 제1층간절연막을 식각하는 제5단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a semiconductor device manufacturing method using a dual damascene process using an etch stop layer, the method comprising: forming a first interlayer insulating film on a substrate on which a predetermined stepped structure is formed; Forming a metal layer as an etch stop layer on the first interlayer insulating film; Selectively etching the metal layer to expose the first interlayer dielectric layer at a contact portion; A fourth step of forming a second interlayer insulating film on the resultant of the third step; And a fifth step of etching the second interlayer insulating film and the first interlayer insulating film of the portion exposed in the third step by selective etching.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도2a 내지 도2c에는 본 발명에 따른 개선된 듀얼 대머신 공정이 도시되어 있다.2A-2C show an improved dual damascene process according to the present invention.

먼저 도2a를 참조하면, 소정의 단차 구조물이 형성되어 있는 기판 상에 제1층간산화막(201)을 형성하고, 그 상부에 식각정지층으로서 TiN막(202)을 형성한 다음, 상기 TiN막(202) 상에 포토리소그래피 공정을 통해 콘택마스크로서 제1포토레지스트패턴(203)을 형성한다. 바람직하게 층간산화막(201)은 평탄화되어야 한다.First, referring to FIG. 2A, a first interlayer oxide film 201 is formed on a substrate on which a predetermined stepped structure is formed, and a TiN film 202 is formed thereon as an etch stop layer, and then the TiN film ( A first photoresist pattern 203 is formed on the 202 as a contact mask through a photolithography process. Preferably, the interlayer oxide film 201 should be planarized.

이어서 도2b를 참조하면, 상기 포토레지스트패턴(203)을 식각마스크로하여 상기 TiN막(202)을 선택적으로 식각하므로써, 콘택 부위의 상기 제1층간산화막(201)을 노출시킨 다음, 상기 포토레지스트패턴(103)을 제거한 후 결과물 전면에 제2층간산화막(204)을 증착하고, 그 상부에 배선 마스크인 제2포토레지스트패턴(205)을 형성한다. 이때 제2층간산화막(204) 역시 평탄화되는 것이 바람직하다. TiN막(202)의 식각은 SxF, Cl2, HBr 등의 에천트를 이용한다.2B, the TiN film 202 is selectively etched using the photoresist pattern 203 as an etch mask, thereby exposing the first interlayer oxide film 201 at a contact portion, and then the photoresist. After the pattern 103 is removed, a second interlayer oxide film 204 is deposited on the entire surface of the resultant, and a second photoresist pattern 205 that is a wiring mask is formed thereon. In this case, the second interlayer oxide film 204 may also be planarized. The etching of the TiN film 202 uses an etchant such as S x F, Cl 2 and HBr.

이어서, 도2c를 참조하면, 상기 포토레지스트패턴(205)을 식각마스크로하여 상기 제2층간산화막(204)과 제1층간산화막(201)를 식각하여 홀(206)을 형성한다. 제1층간산화막(201)은 패턴된 TiN막(202)에 의해 오픈된 부위만이 식각된다. 이때 식각 공정은 산화막 식각장비에서 CxF계 에천트를 사용하게 되는데, TiN막(202)은 CxF계 에천트에 의해 실질적인 식각이 이루어지지 않는다. 따라서 식각정지층으로서의 작용이 매우 뛰어나다.2C, the second interlayer oxide layer 204 and the first interlayer oxide layer 201 are etched using the photoresist pattern 205 as an etch mask to form holes 206. Only a portion of the first interlayer oxide film 201 opened by the patterned TiN film 202 is etched. At this time, the etching process uses a C x F-based etchant in the oxide etching equipment, the TiN film 202 is not substantially etched by the C x F-based etchant. Therefore, it acts very well as an etch stop layer.

도면에는 도시되지 않았지만 이후, 결과물 전면에 금속 또는 기타 재질의 전도막을 증착하고 CMP를 실시하므로써 상기 홀(207)에 금속 또는 기타 재질의 전도막이 매립되도록 하면, 듀얼 대머신 공정에 의한 배선 형성이 완료된다. 금속을 매립할때에는 통상의 배선 공정과 같이 글루층과 베리어메탈을 먼저 형성하고 금속을 매립할 수 있다.Although not shown in the drawings, after the conductive film of metal or other material is deposited on the entire surface of the resultant and CMP is carried out to fill the conductive film of metal or other material in the hole 207, the wiring formation by the dual damascene process is completed. do. When the metal is buried, the glue layer and the barrier metal may be formed first, and the metal may be buried as in the usual wiring process.

이상에서 설명한 바와 같이 본 실시예는 TiN을 식각정지층으로 이용하고 있으나, TiN 이외의 금속을 사용하는 것이 가능하다. 예를 들면, W 등이 가능하다.
한편, 복수의 듀얼 대머신 패턴에 의해 복수의 금속 콘택 및 배선이 형성되는 반도체소자가 있을 수 있는 바, 이때 TiN, W 등의 금속층은 도전층이므로 듀얼 대머신 패턴에 의한 금속배선뿐 아니라, 그 주위에 형성될 수 있는 다른 도전층 배선과 전기적으로 연결될 수 있다. 때문에 이럴 경우에는 듀얼 대머신 패턴 주위에 존재하는 식각정지층으로서의 금속층을 별도로 식각 제거할 필요가 있다. 그때의 식각정지용 금속층의 패턴 형성 공정은 앞서 설명한 도 2a의 과정에서 마스크의 형상을 변형하는 것에 가능하다.As described above, the present embodiment uses TiN as an etch stop layer, but it is possible to use a metal other than TiN. For example, W and the like are possible.
Meanwhile, there may be a semiconductor device in which a plurality of metal contacts and wirings are formed by a plurality of dual damascene patterns. In this case, since the metal layers such as TiN and W are conductive layers, not only the metal wirings due to the dual damascene pattern, It can be electrically connected with other conductive layer wiring that can be formed around it. Therefore, in this case, it is necessary to separately etch away the metal layer as an etch stop layer existing around the dual damascene pattern. The pattern formation process of the etch stop metal layer at this time is possible to deform | transform the shape of a mask in the process of FIG. 2A mentioned above.

이렇듯 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As described above, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 식각장벽을 이용한 듀얼 대머신 공정을 수행함에 있어, 식각장벽에 대한 산화물(층간절연물)의 높은 식각선택비를 얻을 수 있어 새로운 장비의 개발 및 구입 없이 고집적소자의 개발을 앞당길 수 있다.In the present invention, in performing a dual damascene process using an etch barrier, a high etching selectivity of an oxide (interlayer insulator) with respect to the etch barrier can be obtained, thereby speeding up the development of highly integrated devices without developing and purchasing new equipment.

또한, 유전상수 값이 큰 질화막을 사용하지 않기 때문에 소자의 동작 속도를 향상시킬 수 있다.In addition, since the nitride film having a large dielectric constant value is not used, the operation speed of the device can be improved.

또한 금속을 식각정지층으로 사용하므로써 베리어메탈의 두께를 감소시킬 수 있다.In addition, the thickness of the barrier metal can be reduced by using a metal as an etch stop layer.

Claims (3)

식각정지층을 사용하는 듀얼 대머신 공정을 적용한 반도체소자 제조방법에 있어서,In the semiconductor device manufacturing method applying a dual damascene process using an etch stop layer, 소정의 단차 구조물이 형성되어 있는 기판 상에 제1층간절연막을 형성하는 제1단계;A first step of forming a first interlayer insulating film on a substrate on which a predetermined stepped structure is formed; 상기 제1층간절연막 상에 식각정지층으로서 금속층을 형성하는 제2단계;Forming a metal layer as an etch stop layer on the first interlayer insulating film; 상기 금속막을 선택적으로 식각하여 콘택부위의 상기 제1층간절연막을 노출시키는 제3단계;Selectively etching the metal layer to expose the first interlayer dielectric layer at a contact portion; 상기 제3단계가 완료된 결과물 상부에 제2층간절연막을 형성하는 제4단계; 및A fourth step of forming a second interlayer insulating film on the resultant of the third step; And 선택적 식각으로 상기 제2층간절연막과 상기 제3단계에서 노출된 부위의 제1층간절연막을 식각하는 제5단계A fifth step of etching the second interlayer insulating film and the first interlayer insulating film of a portion exposed in the third step by selective etching; 를 포함하여 이루어진 반도체소자 제조방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 및 제2 층간절연막은 산화막이며 상기 금속막은 TiN막임을 특징으로 하는 반도체소자 제조방법.Wherein the first and second interlayer insulating films are oxide films and the metal films are TiN films. 제1항에 있어서,The method of claim 1, 상기 제5단계에서의 식각은 CxF계 가스에서 이루어짐을 특징으로 하는 반도체소자 제조방법.The etching in the fifth step is a semiconductor device manufacturing method, characterized in that made in the C x F-based gas.
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