WO2011135641A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2011135641A1
WO2011135641A1 PCT/JP2010/006672 JP2010006672W WO2011135641A1 WO 2011135641 A1 WO2011135641 A1 WO 2011135641A1 JP 2010006672 W JP2010006672 W JP 2010006672W WO 2011135641 A1 WO2011135641 A1 WO 2011135641A1
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WO
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Prior art keywords
insulating film
interlayer insulating
dummy pattern
inductor
wiring
Prior art date
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PCT/JP2010/006672
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French (fr)
Japanese (ja)
Inventor
柴田義行
飛田郭雅
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パナソニック株式会社
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Publication of WO2011135641A1 publication Critical patent/WO2011135641A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the technology described in the present specification relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which an inductor and a dummy pattern for wiring formation are provided under the inductor and a manufacturing method thereof when an inductor is mounted.
  • a wiring structure in which wiring is embedded in a groove and copper is used as a wiring material has been adopted.
  • a groove is formed in the interlayer insulating film using lithography and dry etching processes.
  • copper is deposited on the interlayer insulating film by, for example, plating, and a part of the copper film is polished and removed by chemical-mechanical polishing (CMP) so that the copper is embedded in the previously provided groove. Can be formed.
  • CMP chemical-mechanical polishing
  • grooves 1902 and 1903 are formed in the interlayer insulating film 1901 deposited on the semiconductor substrate by using lithography and dry etching processes.
  • the groove 1902 is a wiring groove
  • the groove 1903 is a CMP dummy pattern.
  • copper 1904 is deposited on the entire upper surface of the semiconductor substrate including the previously formed grooves by, for example, plating.
  • the copper on the interlayer insulating film 1901 is removed by CMP, and the copper embedded in the trench is left, thereby forming the wiring 1905.
  • the copper 1904 embedded in the groove is excessively polished, resulting in a step 1906 on the upper surface of the substrate.
  • FIG. 8D shows a step of removing copper on the interlayer insulating film 1901 by CMP for a semiconductor device in which no dummy pattern is formed.
  • the amount of polishing of the interlayer insulating film 1901 is larger than that in the region where the wiring and the dummy pattern are provided. Will occur.
  • the upper surface 1908 of the interlayer insulating film 1901 shows good flatness even after CMP by providing a dummy pattern also in a region where no wiring is provided on the wafer.
  • good flatness can be secured for the layer on which the wiring is formed, and the same process is repeated to repeat the wiring layer. Can be laminated.
  • CMOS complementary MOS
  • an inductor is mounted together with a variable capacitance and a capacitance in a wiring portion.
  • the inductor is formed on an upper layer portion of the wiring layer or on the wiring layer.
  • a dummy pattern is required as in the case of a normal wiring. Therefore, in the previous case where the inductor is formed in the same layer as the wiring layer, a dummy pattern is arranged around the inductor.
  • FIG. 9 is a cross-sectional view showing a conventional semiconductor device provided with embedded wiring and an inductor.
  • the transistor 1803 is formed over the semiconductor substrate 1801 in which the element isolation region 1802 is formed, and the first interlayer insulating film 1804 is formed over the transistor and the semiconductor substrate 1801.
  • a buried wiring 1806 is formed on the first interlayer insulating film 1804, and the wiring 1806 is connected to the impurity diffusion region of the semiconductor substrate 1801 by a contact plug 1805.
  • a dummy pattern 1808 is appropriately formed in the vicinity of the wiring 1806 and a dummy pattern 1807 is appropriately formed in a region where the wiring 1806 is not formed.
  • the inductor 1811 is formed in the upper wiring layer.
  • the inductor 1811 is arranged in the upper wiring layer, and there is no wiring layer below the inductor 1811, but the dummy pattern 1807 is arranged.
  • the dummy pattern is formed at the same time as the wiring, a dummy pattern made of copper is arranged under the inductor but not the wiring. At this time, since parasitic capacitance is generated between the inductor and the dummy pattern, there is a possibility that the Q value characteristic of the inductor deteriorates.
  • parasitic capacitance is generated for the dummy pattern of each layer, which may degrade the Q value of the inductor.
  • the inductor can be arranged at a certain distance from the wiring in the same wiring layer, but even in this case, the parasitic capacitance generated between the dummy pattern in the lower layer cannot be reduced.
  • An object of the present invention is to provide a semiconductor device in which the parasitic capacitance generated between the wiring and the inductor is reduced while maintaining the flatness of the wiring layer.
  • a semiconductor device is a semiconductor device including a wiring formation region and an inductor region.
  • the semiconductor device includes a semiconductor substrate, a first interlayer insulating film formed on or above the semiconductor substrate, and a wiring embedded in a portion of the first interlayer insulating film located in the wiring formation region A second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region, and a second interlayer insulating film formed on or above the first interlayer insulating film A film, and an inductor embedded in a portion of the second interlayer insulating film located in the inductor region above the second dummy pattern.
  • a conductor is not formed as the second dummy pattern.
  • the second dummy pattern provided below the inductor is not made of metal, parasitic capacitance generated between the inductor and the second dummy pattern is reduced by the second dummy pattern. Compared with the case where it comprises, it can reduce remarkably. For this reason, the Q value of the inductor can be improved.
  • the step formed on the upper surface of the first interlayer insulating film can be reduced.
  • the second dummy pattern may be constituted by a cavity or an insulating film.
  • a semiconductor device is a semiconductor device including a wiring formation region and an inductor region.
  • the semiconductor device includes a semiconductor substrate, a first interlayer insulating film formed on or above the semiconductor substrate, and a wiring embedded in a portion of the first interlayer insulating film located in the wiring formation region And a first dummy pattern, a second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region, and the upper side of the first interlayer insulating film.
  • the parasitic capacitance generated between the inductor and the second dummy pattern because the inductor and the second dummy pattern provided below the inductor do not overlap at least partially when seen in a plan view. Therefore, the Q value of the inductor can be improved.
  • the flatness of the upper surface of the first interlayer insulating film is improved by providing the second dummy pattern.
  • a semiconductor device is a semiconductor device including a wiring formation region and an inductor region, and includes a semiconductor substrate and a first interlayer insulating film formed on or above the semiconductor substrate.
  • an inductor embedded in a portion of the insulating film located in the inductor region, and the area ratio of the second dummy pattern in the inductor region is the first damascene in the wiring formation region. Smaller than the area ratio of over pattern.
  • the area ratio of the second dummy pattern in the inductor region is smaller than the area ratio of the first dummy pattern in the wiring formation region, the overlap between the inductor and the second dummy pattern is performed.
  • the parasitic capacitance between the inductor and the second dummy pattern can be reduced.
  • a method of manufacturing a semiconductor device includes a step of forming a transistor formed on a semiconductor substrate, a first interlayer insulating film on the semiconductor substrate, and the first interlayer insulating film. Forming a groove, and forming a wiring and a first dummy pattern in a portion of the first interlayer insulating film located in a wiring formation region by embedding a conductor in the groove, and then forming the first interlayer A step of selectively removing the conductive film in the groove formed in a portion located in the inductor region of the insulating film; and the step formed in a portion located in the inductor region of the first interlayer insulating film.
  • Process to form 3 interlayer insulation film When, and a step of forming an inductor in a portion positioned in the inductor region of the third interlayer insulating film.
  • the cavity serving as the second dummy pattern is formed in the groove formed in the portion located in the inductor region of the first interlayer insulating film, the gap between the inductor and the second pattern is formed.
  • the generated parasitic capacitance can be reduced.
  • the upper surface of the first interlayer insulating film can be kept flat when the conductive film is removed.
  • a method of manufacturing a semiconductor device includes a step of forming a transistor formed on a semiconductor substrate, a first interlayer insulating film on the semiconductor substrate, and the first interlayer insulating film. Forming a groove, and forming a wiring and a first dummy pattern in a portion of the first interlayer insulating film located in a wiring formation region by embedding a conductor in the groove, and then forming the first interlayer A step of selectively removing the conductive film in the groove formed in a portion of the insulating film located in the inductor region; and a step of forming the portion of the first interlayer insulating film located in the inductor region.
  • the insulating film is embedded in the second interlayer insulating film as the second dummy pattern, the parasitic capacitance generated between the inductor and the second dummy pattern can be reduced. Therefore, the Q value of the inductor can be increased.
  • the first dummy pattern and the second dummy pattern are formed to realize the planarization of the wiring layer, and the inductor and the second dummy pattern. Parasitic capacitance generated between them can be reduced, and the Q value of the inductor can be improved.
  • FIG. 1A is a sectional view showing a semiconductor device according to the first embodiment of the present invention
  • FIG. 1B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. It is a figure and (c) is a figure which expands and shows a wiring groove
  • 2A to 2E are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • 3A to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 4A is a sectional view showing a semiconductor device according to the second embodiment of the present invention, and FIG.
  • FIG. 4B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device.
  • FIG. 5A to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 6A is a sectional view showing a semiconductor device according to the third embodiment of the present invention, and FIG. 6B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device.
  • FIG. FIG. 7A is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention, and FIG. 7B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device.
  • FIG. 8A to 8E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
  • FIG. 9 is a cross-sectional view showing a conventional semiconductor device provided with embedded wiring and an inductor.
  • FIG. 1A is a sectional view showing a semiconductor device according to the first embodiment of the present invention
  • FIG. 1B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. It is a figure and (c) is a figure which expands and shows a wiring groove
  • elements such as the MOS transistor 103 are provided on the semiconductor substrate 101 made of silicon or the like provided with the element isolation region 102.
  • a first interlayer insulating film 104 is provided on the MOS transistor 103 and the semiconductor substrate 101, and a second interlayer insulating film 506 is provided on the first interlayer insulating film 104.
  • a wiring 106 made of a metal such as copper is embedded in the second interlayer insulating film 506. The wiring 106 is connected to the impurity diffusion region of the semiconductor substrate 101 by a contact plug 105.
  • a laminated wiring structure 110 composed of a plurality of wiring layers is formed, and each wiring is connected by a via 109.
  • the wiring 106, the dummy pattern 107, and the cavity 108 are formed in each wiring layer.
  • a dummy pattern 107 is formed in the vicinity of the wiring 106 (in the wiring formation region).
  • the dummy pattern 107 is formed by burying the same material as the constituent material of the wiring 106 in the groove formed in the second interlayer insulating film 506.
  • a cavity 108 is provided as a dummy pattern in the inductor region of the same wiring layer as the wiring 106 and in the inductor region of the upper wiring layer.
  • the cavity 108 is formed in a trench formed in the second interlayer insulating film 506 and each interlayer insulating film.
  • the width and depth of the groove in which the cavity 108 is formed may be the same as the groove in which the dummy pattern 107 is provided, and the distance between the grooves can be arbitrarily set.
  • an inductor 111 made of the same material as the wiring 106 is provided in the upper wiring layer of the cavity 108.
  • the inductor 111 has, for example, a spiral planar shape.
  • the groove width (groove diameter) for the dummy pattern is 1 ⁇ m
  • an interlayer insulating film 113 having a thickness of about 500 nm is formed on the groove by a chemical vapor deposition (CVD) method or the like.
  • CVD chemical vapor deposition
  • the corner 114 at the bottom of the groove is not filled with the insulating film, and the cavity 114 is formed (the left diagram in FIG. 1C).
  • the insulating film is not uniformly deposited over the entire groove, and the cavity 115 is formed in the center of the groove.
  • the cavity 108 is formed as a dummy pattern below the inductor 111, no parasitic capacitance is generated between the inductor 111 and the dummy pattern. For this reason, the Q value of the inductor 111 can be improved as compared with the case where parasitic capacitance is generated between the inductor and the dummy pattern.
  • each wiring layer can be planarized.
  • a cavity is provided in each groove in the inductor region.
  • generation of parasitic capacitance is suppressed. Can do.
  • the cavities 108 may be formed in all the wiring layers, the generation of parasitic capacitance can be suppressed if the cavities 108 are formed in at least some of the wiring layers.
  • the cavity 108 is provided as a dummy pattern.
  • a conductor such as a metal is not provided as a dummy pattern, the formation in the groove is not limited to the cavity 108.
  • FIGS. 3A to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • a MOS transistor 103 having a gate electrode is formed by a known method.
  • the contact plug 105 penetrating the first interlayer insulating film 104 is formed.
  • a second interlayer insulating film 506 is formed on the first interlayer insulating film 104 by a CVD method or the like.
  • lithography and dry etching of the second interlayer insulating film 506 are performed to form a wiring formation groove 507 in the second interlayer insulating film 506 and a dummy pattern in the wiring forming region.
  • a trench 508 for forming a dummy pattern in the inductor region is formed.
  • the width of the groove 507 is about 200 nm, for example, and the width of the grooves 508 and 509 is about 200 nm, for example.
  • the interval between the grooves 509 is about 2 ⁇ m, for example.
  • a copper film (conductor) 510 is formed on the upper surface of the substrate including the grooves 507, 508, and 509 in the step shown in FIG.
  • the copper film 510 is formed by, for example, a plating method.
  • the copper film 510 is polished by CMP to remove a portion of the copper film 510 provided outside the groove, and the wiring 106 and the position near the wiring 106 are removed. Then, a copper film (dummy pattern 107) embedded in the groove 508 and a copper film 513 embedded in the groove 509 are formed.
  • a resist mask 514 that covers the wiring formation region of the substrate (semiconductor device being fabricated) and has an opening in the inductor region is formed.
  • the resist mask 514 is formed using lithography, for example.
  • the copper film 513 disposed in the inductor region is removed by wet etching using a chemical solution such as sulfuric acid. Thereby, the inside of the groove 509 becomes a cavity.
  • an interlayer insulating film made of an insulating film is formed on the second interlayer insulating film 506 and the wiring 106.
  • the cavity 108 is formed in the groove 509.
  • the multilayer wiring structure 110 is formed by repeating the above-described wiring and dummy pattern forming steps.
  • the inductor 111 made of the same copper as the wiring 106 is formed in the upper wiring layer.
  • the cavity 108 is formed as a dummy pattern provided in the lower layer of the inductor 111, no parasitic capacitance is generated between the inductor 111 and the dummy pattern. For this reason, the parasitic capacitance can be greatly reduced as compared with the case where a dummy pattern made of metal is provided below the inductor, and the Q value of the inductor 111 can be sufficiently increased.
  • the inductor region since the dummy pattern is formed in each interlayer insulating film as in the wiring formation region, the step generated in the wiring layer is reduced. For this reason, it is possible to form an inductor having an excellent Q value while suppressing problems such as poor connection due to the formation of a step.
  • FIG. 4A is a sectional view showing a semiconductor device according to the second embodiment of the present invention
  • FIG. 4B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device.
  • the semiconductor device of the present embodiment is formed on the semiconductor substrate 101 on which the element isolation region 102 is formed, like the semiconductor device according to the first embodiment.
  • a wiring 106 formed on the wiring 506, a contact plug 105 connected to the wiring 106, a dummy pattern 107, and a dummy pattern 208 formed on the second interlayer insulating film 506 in the inductor region are provided.
  • An inductor 111 is formed in the upper wiring layer.
  • a laminated wiring structure 210 composed of a plurality of wiring layers is formed above the wiring 106 provided in the second interlayer insulating film 506, and each wiring is connected by a via 109.
  • the dummy pattern 107 provided in the vicinity of the wiring 106 is embedded in the groove and is made of the same copper as the constituent material of the wiring 106.
  • the semiconductor device of this embodiment is different from the first semiconductor device in that grooves are formed in the interlayer insulating film in the inductor region at a predetermined interval, and an insulating film is provided as a dummy pattern 208 in the groove. It is a point.
  • the dummy pattern 208 is made of an insulator such as a silicon nitride film.
  • each wiring layer can be planarized.
  • an insulating film is provided in each groove in the inductor region. However, if an insulating film is provided in a part of the groove, parasitic capacitance is generated. Can be suppressed. Insulating films may be formed in all the wiring layers, but if an insulating film is formed in at least some of the wiring layers, the generation of parasitic capacitance can be suppressed.
  • the dielectric constant of the insulating film which is the dummy pattern 208 is lower than the dielectric constant of the interlayer insulating film provided with the dummy pattern, the parasitic capacitance between the inductor and the dummy pattern can be further reduced, and the higher Q The value can be realized.
  • the dummy pattern 208 may be composed of a single insulating film, but the same effect can be obtained even if it is a laminated body of a silicon nitride film or an oxide film.
  • -Semiconductor device manufacturing method- 5A to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 5A shows the semiconductor device in the same state as FIG.
  • an insulating film 709 made of, for example, a silicon nitride film is formed on the entire upper surface of the substrate including the groove 509.
  • the insulating film 709 is embedded in the trench 509.
  • the insulating film 709 is polished by CMP until the wiring 106 and the second interlayer insulating film 506 are exposed, and a dummy pattern made of the insulating film 709 embedded in the trench 509 is formed. 208 is formed.
  • the laminated wiring structure 210 is formed by repeating the process of forming the wiring 106 and the dummy patterns 107 and 208.
  • the inductor 111 made of the same copper as the wiring 106 is formed in the upper wiring layer.
  • the parasitic capacitance can be greatly reduced as compared with the case where a dummy pattern made of metal is provided below the inductor, and the Q value of the inductor 111 can be sufficiently increased.
  • the inductor region since the dummy pattern is formed in each interlayer insulating film as in the wiring formation region, the step generated in the wiring layer is reduced. For this reason, it is possible to form an inductor having an excellent Q value while suppressing problems such as poor connection due to the formation of a step.
  • FIG. 6A is a sectional view showing a semiconductor device according to the third embodiment of the present invention
  • FIG. 6B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device.
  • the semiconductor device of this embodiment is formed on the semiconductor substrate 101 in which the element isolation region 102 is formed, as in the semiconductor device according to the first embodiment.
  • a wiring 106 formed on the wiring 506, a contact plug 105 connected to the wiring 106, a dummy pattern 307, and a dummy pattern 308 formed on the second interlayer insulating film 506 in the inductor region are provided.
  • An inductor 111 is formed in the upper wiring layer.
  • a laminated wiring structure 310 composed of a plurality of wiring layers is formed above the wiring 106 provided in the second interlayer insulating film 506, and each wiring is connected by a via 109.
  • the dummy pattern 307 provided in the vicinity of the wiring 106 is embedded in the groove and is made of the same copper as the constituent material of the wiring 106.
  • the semiconductor device of this embodiment is different from the first semiconductor device in that the dummy pattern 308 is composed of a conductor embedded in the groove, and the dummy pattern 308 and the inductor 111 in the inductor region are planar. Is at least partially non-overlapping. In particular, it is more preferable if the dummy pattern 308 and the inductor 111 do not overlap in plan view.
  • the dummy pattern 308 may be made of the same material as the wiring 106.
  • the inductor 111, the wiring 106, and the dummy pattern 308 may be made of, for example, copper, Al, or a laminated film of metal.
  • the inductor 111 is formed in a coil shape in one wiring layer, and the width of the metal film forming the inductor 111 is, for example, about several ⁇ m to 10 ⁇ m, and the distance between the metal films is about several ⁇ m to 20 ⁇ m. .
  • the width of the dummy pattern 307 in the wiring formation region is about 1 ⁇ m, and the arrangement interval is about 2 ⁇ m, for example.
  • a dummy pattern 308 may be formed between the metal films constituting the inductor 111.
  • the dummy pattern 308 is not disposed immediately below the inductor 111, the distance between the dummy pattern 308 and the inductor 111 is increased as compared with the case where the dummy pattern and the inductor overlap in plan view. be able to. For this reason, the parasitic capacitance generated between the dummy pattern 308 and the inductor 111 can be reduced, and the Q value of the inductor 111 can be improved.
  • FIG. 7A is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention
  • FIG. 7B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device.
  • the semiconductor device according to the present embodiment is formed on the semiconductor substrate 101 on which the element isolation region 102 is formed, similarly to the semiconductor device according to the first embodiment.
  • a wiring 106 formed on the wiring 506, a contact plug 105 connected to the wiring 106, a dummy pattern 407, and a dummy pattern 408 formed on the second interlayer insulating film 506 in the inductor region are provided.
  • An inductor 111 is formed in the upper wiring layer.
  • a laminated wiring structure 410 composed of a plurality of wiring layers is formed above the wiring 106 provided in the second interlayer insulating film 506, and each wiring is connected by a via 109.
  • the wiring 106, the dummy pattern 407, and the dummy pattern 408 are formed in each wiring layer.
  • the dummy pattern 407 provided in the vicinity of the wiring 106 is embedded in the groove and is made of the same copper as the constituent material of the wiring 106.
  • the semiconductor device of this embodiment is different from the first semiconductor device in that the area ratio of the dummy pattern 408 formed below the inductor 111 in the inductor region (the dummy pattern in the entire main surface of the substrate occupies the predetermined region). (Area ratio) is smaller than the area ratio of the dummy pattern 407 in the wiring formation region.
  • the dummy pattern 408 may be made of the same material as that of the wiring 106, and may be made of, for example, copper, Al, or a laminated film of metal.
  • the size of the dummy pattern 408 is equal to that of the dummy pattern 407, and the number of the dummy patterns 408 formed is smaller than that of the dummy pattern 407. That is, the dummy pattern density of the dummy pattern 408 is set lower than the density of the dummy pattern 407 and the wiring density of the wiring 106.
  • “dummy pattern density” refers to a dummy pattern area per unit area. Note that the size of the dummy patterns 408 may be smaller than that of the dummy patterns 407 and may be provided in the same number as the dummy patterns 407.
  • the area where the inductor 111 and the dummy pattern 408 overlap can be reduced as compared with the case where the area ratio of the dummy pattern 408 is arranged at the same area ratio as the dummy pattern 407. Therefore, the parasitic capacitance generated between the inductor 111 and the dummy pattern 408 can be reduced, and the Q value of the inductor 111 can be increased.
  • the area ratio of the defined dummy pattern is a value having a width of several tens of percent.
  • a difference of, for example, 10% or more is provided in the area ratio of the dummy pattern in each of the wiring formation region and the inductor region.
  • the semiconductor device and the manufacturing method thereof according to an example of the present invention, it is useful for a method of forming a semiconductor device in which embedded metal wiring formed in a plurality of wiring layers and an inductor are mounted. It is.

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Disclosed is a semiconductor device which is provided with: a first interlayer insulating film (506), which is formed on a semiconductor substrate (101); wiring (106) which is embedded in a first interlayer insulating film (506) part that is positioned in a wiring forming region; a first dummy pattern (107), which is embedded in a first interlayer insulating film (506) part that is positioned in the wiring forming region; a second dummy pattern (108), which is embedded in a first interlayer insulating film (506) part that is positioned in an inductor region; a second interlayer insulating film, which is formed above the first interlayer insulating film (506); and an inductor (111), which is disposed above the second dummy pattern (108), and which is embedded in a second interlayer insulating film part that is positioned in the inductor region. A metal is not formed as the second dummy pattern (108).

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本明細書に記載の技術は、半導体装置及びその製造方法に関し、特にインダクタを搭載する場合に、インダクタと、インダクタの下層に配線形成用ダミーパターンを設けた半導体装置及びその製造方法に関する。 The technology described in the present specification relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which an inductor and a dummy pattern for wiring formation are provided under the inductor and a manufacturing method thereof when an inductor is mounted.
　近年、半導体装置の高集積化、高機能化、微細化に伴って、配線を溝の中に埋め込み、且つ配線材料に銅を用いた配線構造が採用されてきている。この構造を作製するには、基板上に層間絶縁膜を堆積した後、リソグラフィ及びドライエッチング工程などを用いて層間絶縁膜に溝を形成する。次いで、層間絶縁膜上に例えば、めっき法などにより銅を堆積し、Chemical Mechanical Polishing（ＣＭＰ）により銅膜の一部を研磨除去することにより、先に設けた溝の中に銅が埋め込めこまれてなる配線を形成できる。このとき、配線を埋め込む溝の周囲に、ダミーパターンと呼ばれるパターンを設けることにより、配線層及び層間絶縁膜の平坦化を図ることができる。 In recent years, with the high integration, high functionality, and miniaturization of semiconductor devices, a wiring structure in which wiring is embedded in a groove and copper is used as a wiring material has been adopted. In order to fabricate this structure, after depositing an interlayer insulating film on the substrate, a groove is formed in the interlayer insulating film using lithography and dry etching processes. Next, copper is deposited on the interlayer insulating film by, for example, plating, and a part of the copper film is polished and removed by chemical-mechanical polishing (CMP) so that the copper is embedded in the previously provided groove. Can be formed. At this time, the wiring layer and the interlayer insulating film can be planarized by providing a pattern called a dummy pattern around the trench for embedding the wiring.
　図８（ａ）～（ｅ）を用いて、埋め込み型の配線の一般的な形成方法を説明する。 A general method for forming embedded wiring will be described with reference to FIGS.
　まず、図８（ａ）に示す工程で、半導体基板上に堆積された層間絶縁膜１９０１にリソグラフィ及びドライエッチング工程を用いて溝１９０２、１９０３を形成する。ここで、溝１９０２は配線用の溝であり、溝１９０３はＣＭＰ用のダミーパターンである。 First, in the process shown in FIG. 8A, grooves 1902 and 1903 are formed in the interlayer insulating film 1901 deposited on the semiconductor substrate by using lithography and dry etching processes. Here, the groove 1902 is a wiring groove, and the groove 1903 is a CMP dummy pattern.
　次に、図８（ｂ）に示す工程で、先に形成した溝を含む半導体基板の上面全体に、例えばめっき法などにより銅１９０４を堆積する。 Next, in the step shown in FIG. 8B, copper 1904 is deposited on the entire upper surface of the semiconductor substrate including the previously formed grooves by, for example, plating.
　次に、図８（ｃ）に示す工程で、ＣＭＰにより層間絶縁膜１９０１上の銅を除去し、溝の中に埋め込まれた銅を残すことにより、配線１９０５を形成する。この時、配線形成用の溝１９０２の周辺にダミーパターン（ダミーの溝）を設けていなければ溝中に埋め込まれた銅１９０４が過剰に研磨され、基板上面に段差１９０６が生じてしまう。 Next, in the step shown in FIG. 8C, the copper on the interlayer insulating film 1901 is removed by CMP, and the copper embedded in the trench is left, thereby forming the wiring 1905. At this time, if a dummy pattern (dummy groove) is not provided around the wiring forming groove 1902, the copper 1904 embedded in the groove is excessively polished, resulting in a step 1906 on the upper surface of the substrate.
　ここで、図８（ｄ）では、ダミーパターンが形成されていない半導体装置について、ＣＭＰにより層間絶縁膜１９０１上の銅を除去する工程を示している。ダミーパターンも配線も形成されていない領域では、配線及びダミーパターンが設けられている領域に比べて層間絶縁膜１９０１の研磨量が大きくなるので層間絶縁膜厚が互いに異なり、両領域の境界に段差が生じてしまう。 Here, FIG. 8D shows a step of removing copper on the interlayer insulating film 1901 by CMP for a semiconductor device in which no dummy pattern is formed. In the region where neither the dummy pattern nor the wiring is formed, the amount of polishing of the interlayer insulating film 1901 is larger than that in the region where the wiring and the dummy pattern are provided. Will occur.
　そこで、図８（ｅ）に示すように、ウエハに配線を設けない領域についてもダミーパターンを設けることにより、層間絶縁膜１９０１の上面１９０８はＣＭＰ後も良好な平坦性を示す。このように、層間絶縁膜中に埋め込み型の銅配線を形成する場合には、ダミーパターンを設けることにより、配線を形成した層について良好な平坦性を確保でき、同様の工程を繰り返して配線層を積層することができる。 Therefore, as shown in FIG. 8E, the upper surface 1908 of the interlayer insulating film 1901 shows good flatness even after CMP by providing a dummy pattern also in a region where no wiring is provided on the wafer. Thus, in the case of forming a buried copper wiring in an interlayer insulating film, by providing a dummy pattern, good flatness can be secured for the layer on which the wiring is formed, and the same process is repeated to repeat the wiring layer. Can be laminated.
　一方、素子の微細化に伴い、シリコン等からなる半導体基板上に形成したComplementary MOS（ＣＭＯＳ）トランジスタについても高周波用に使用する要望が高まっている。 On the other hand, with the miniaturization of elements, there is an increasing demand for using a complementary MOS (CMOS) transistor formed on a semiconductor substrate made of silicon or the like for high frequency use.
　ＣＭＯＳ構造をベースとした高周波デバイスでは、可変容量や配線部での容量などと合せてインダクタが搭載される。インダクタは、配線層の上層部あるいは、配線層上に形成されるが、銅配線のような埋め込み型配線を利用して形成する場合には、通常の配線と同様にダミーパターンが必要となる。そのため、インダクタを配線層と同層に形成する先行事例では、インダクタ周辺にダミーパターンが配置されている。 In a high-frequency device based on a CMOS structure, an inductor is mounted together with a variable capacitance and a capacitance in a wiring portion. The inductor is formed on an upper layer portion of the wiring layer or on the wiring layer. However, when the inductor is formed using a buried wiring such as a copper wiring, a dummy pattern is required as in the case of a normal wiring. Therefore, in the previous case where the inductor is formed in the same layer as the wiring layer, a dummy pattern is arranged around the inductor.
　図９は、埋め込み型配線とインダクタとを備えた従来の半導体装置を示す断面図である。この例では、素子分離領域１８０２が形成された半導体基板１８０１上にトランジスタ１８０３が形成され、トランジスタ及び半導体基板１８０１上に第１の層間絶縁膜１８０４が形成される。第１の層間絶縁膜１８０４の上部には埋め込み型の配線１８０６が形成されており、この配線１８０６は、コンタクトプラグ１８０５によって半導体基板１８０１の不純物拡散領域に接続されている。配線１８０６の上層には、複数の配線層で構成された積層配線構造１８１０が形成されており、各配線はビア１８０９によって接続されている。 FIG. 9 is a cross-sectional view showing a conventional semiconductor device provided with embedded wiring and an inductor. In this example, the transistor 1803 is formed over the semiconductor substrate 1801 in which the element isolation region 1802 is formed, and the first interlayer insulating film 1804 is formed over the transistor and the semiconductor substrate 1801. A buried wiring 1806 is formed on the first interlayer insulating film 1804, and the wiring 1806 is connected to the impurity diffusion region of the semiconductor substrate 1801 by a contact plug 1805. On the upper layer of the wiring 1806, a laminated wiring structure 1810 composed of a plurality of wiring layers is formed, and each wiring is connected by a via 1809.
　配線１８０６の近傍にはダミーパターン１８０８が、配線１８０６が形成されない領域にはダミーパターン１８０７が適宜形成される。インダクタ１８１１は上層の配線層内に形成される。 A dummy pattern 1808 is appropriately formed in the vicinity of the wiring 1806 and a dummy pattern 1807 is appropriately formed in a region where the wiring 1806 is not formed. The inductor 1811 is formed in the upper wiring layer.
特開２００１－１４４６０５号公報JP 2001-144605 A
　従来の半導体装置では、インダクタ１８１１が上層の配線層内に配置され、インダクタ１８１１の下方に配線層は存在しないが、ダミーパターン１８０７が配置されている。一般にダミーパターンは配線と同時に形成されるため、インダクタ下層に配線ではないが、銅からなるダミーパターンが配置されることになる。この時、インダクタとダミーパターンの間に寄生容量が発生してしまうため、インダクタのＱ値特性が劣化するという不具合が生じる可能性がある。 In the conventional semiconductor device, the inductor 1811 is arranged in the upper wiring layer, and there is no wiring layer below the inductor 1811, but the dummy pattern 1807 is arranged. In general, since the dummy pattern is formed at the same time as the wiring, a dummy pattern made of copper is arranged under the inductor but not the wiring. At this time, since parasitic capacitance is generated between the inductor and the dummy pattern, there is a possibility that the Q value characteristic of the inductor deteriorates.
　さらに、積層配線構造を有する場合には、各層のダミーパターンについて寄生容量が発生してしまい、インダクタのＱ値を劣化させる可能性がある。従来技術において、同じ配線層内の配線から一定の距離を空けてインダクタを配置することはできるが、その場合でも下層のダミーパターンとの間で発生する寄生容量を低減することはできない。 Furthermore, in the case of a laminated wiring structure, parasitic capacitance is generated for the dummy pattern of each layer, which may degrade the Q value of the inductor. In the prior art, the inductor can be arranged at a certain distance from the wiring in the same wiring layer, but even in this case, the parasitic capacitance generated between the dummy pattern in the lower layer cannot be reduced.
　本発明の目的は、配線層の平坦性を維持しつつ、配線とインダクタとの間に生じる寄生容量を低減させた半導体装置を提供することにある。 An object of the present invention is to provide a semiconductor device in which the parasitic capacitance generated between the wiring and the inductor is reduced while maintaining the flatness of the wiring layer.
　本発明の一例に係る半導体装置は、配線形成領域と、インダクタ領域とを備えた半導体装置である。この半導体装置は、半導体基板と、前記半導体基板上または上方に形成された第１の層間絶縁膜と、前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた配線と、前記第１の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれた第２のダミーパターンと、前記第１の層間絶縁膜の上または上方に形成された第２の層間絶縁膜と、前記第２のダミーパターンの上方であって、前記第２の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれたインダクタとを備えている。そして、前記第２のダミーパターンとして導電体が形成されていない。 A semiconductor device according to an example of the present invention is a semiconductor device including a wiring formation region and an inductor region. The semiconductor device includes a semiconductor substrate, a first interlayer insulating film formed on or above the semiconductor substrate, and a wiring embedded in a portion of the first interlayer insulating film located in the wiring formation region A second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region, and a second interlayer insulating film formed on or above the first interlayer insulating film A film, and an inductor embedded in a portion of the second interlayer insulating film located in the inductor region above the second dummy pattern. A conductor is not formed as the second dummy pattern.
　この構成によれば、インダクタの下方に設けられた第２のダミーパターンが金属で構成されていないので、インダクタと第２のダミーパターンとの間に生じる寄生容量を、第２のダミーパターンが金属で構成される場合に比べて著しく低減することができる。このため、インダクタのＱ値を向上させることができる。 According to this configuration, since the second dummy pattern provided below the inductor is not made of metal, parasitic capacitance generated between the inductor and the second dummy pattern is reduced by the second dummy pattern. Compared with the case where it comprises, it can reduce remarkably. For this reason, the Q value of the inductor can be improved.
　また、第２のダミーパターンが形成されていることで、第１の層間絶縁膜の上面に形成される段差を小さくすることができる。 Further, since the second dummy pattern is formed, the step formed on the upper surface of the first interlayer insulating film can be reduced.
　前記第２のダミーパターンは、空洞で構成されていてもよいし、絶縁膜で構成されていてもよい。 The second dummy pattern may be constituted by a cavity or an insulating film.
　本発明の別の一例に係る半導体装置は、配線形成領域と、インダクタ領域とを備えた半導体装置である。この半導体装置は、半導体基板と、前記半導体基板上または上方に形成された第１の層間絶縁膜と、前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた配線及び第１のダミーパターンと、前記第１の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれた第２のダミーパターンと、前記第１の層間絶縁膜の上または上方に形成された第２の層間絶縁膜と、前記第２のダミーパターンの上方であって、前記第２の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれたインダクタとを備え、前記第２のダミーパターンと前記インダクタとは、平面的に見て少なくとも一部が重ならない。 A semiconductor device according to another example of the present invention is a semiconductor device including a wiring formation region and an inductor region. The semiconductor device includes a semiconductor substrate, a first interlayer insulating film formed on or above the semiconductor substrate, and a wiring embedded in a portion of the first interlayer insulating film located in the wiring formation region And a first dummy pattern, a second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region, and the upper side of the first interlayer insulating film. A second interlayer insulating film; and an inductor embedded in a portion of the second interlayer insulating film located in the inductor region above the second dummy pattern, The dummy pattern and the inductor do not overlap at least partially in plan view.
　この構成によれば、インダクタと、インダクタの下方に設けられた第２のダミーパターンとが平面的に見て少なくとも一部が重ならないことでインダクタと第２のダミーパターンとの間に生じる寄生容量を低減することができるので、インダクタのＱ値を向上させることができる。また、第２のダミーパターンが設けられていることで、第１の層間絶縁膜の上面の平坦性は向上している。 According to this configuration, the parasitic capacitance generated between the inductor and the second dummy pattern because the inductor and the second dummy pattern provided below the inductor do not overlap at least partially when seen in a plan view. Therefore, the Q value of the inductor can be improved. In addition, the flatness of the upper surface of the first interlayer insulating film is improved by providing the second dummy pattern.
　本発明の別の一例に係る半導体装置は、配線形成領域と、インダクタ領域とを備えた半導体装置であって、半導体基板と、前記半導体基板上または上方に形成された第１の層間絶縁膜と、前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた配線及び第１のダミーパターンと、前記第１の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれた第２のダミーパターンと、前記第１の層間絶縁膜の上または上方に形成された第２の層間絶縁膜と、前記第２のダミーパターンの上方であって、前記第２の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれたインダクタとを備え、前記インダクタ領域内での前記第２のダミーパターンの面積率は、前記配線形成領域内での前記第１のダミーパターンの面積率よりも小さい。 A semiconductor device according to another example of the present invention is a semiconductor device including a wiring formation region and an inductor region, and includes a semiconductor substrate and a first interlayer insulating film formed on or above the semiconductor substrate. A wiring and a first dummy pattern embedded in a portion of the first interlayer insulating film located in the wiring formation region, and a portion of the first interlayer insulating film located in the inductor region. A buried second dummy pattern; a second interlayer insulating film formed on or above the first interlayer insulating film; and the second interlayer pattern above the second dummy pattern. And an inductor embedded in a portion of the insulating film located in the inductor region, and the area ratio of the second dummy pattern in the inductor region is the first damascene in the wiring formation region. Smaller than the area ratio of over pattern.
　この構成によれば、インダクタ領域内での第２のダミーパターンの面積率は、配線形成領域内での第１のダミーパターンの面積率よりも小さいので、インダクタと第２のダミーパターンとの重なりが小さくなっており、インダクタと第２のダミーパターンとの間の寄生容量を低減することができる。 According to this configuration, since the area ratio of the second dummy pattern in the inductor region is smaller than the area ratio of the first dummy pattern in the wiring formation region, the overlap between the inductor and the second dummy pattern is performed. The parasitic capacitance between the inductor and the second dummy pattern can be reduced.
　本発明の別の一例に係る半導体装置の製造方法は、半導体基板上に形成されたトランジスタ及び前記半導体基板の上に第１の層間絶縁膜を形成する工程と、前記第１の層間絶縁膜に溝を形成する工程と、前記溝に導電体を埋め込むことで前記第１の層間絶縁膜のうち配線形成領域に位置する部分に配線及び第１のダミーパターンを形成した後、前記第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された前記溝内の前記導電膜を選択的に除去する工程と、前記第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された前記溝内に第２のダミーパターンとなる空洞ができるように、前記第１の層間絶縁膜上に第２の層間絶縁膜を形成する工程と、前記第２の層間絶縁膜の上または上方に第３の層間絶縁膜を形成する工程と、前記第３の層間絶縁膜のうち前記インダクタ領域に位置する部分にインダクタを形成する工程とを備えている。 A method of manufacturing a semiconductor device according to another example of the present invention includes a step of forming a transistor formed on a semiconductor substrate, a first interlayer insulating film on the semiconductor substrate, and the first interlayer insulating film. Forming a groove, and forming a wiring and a first dummy pattern in a portion of the first interlayer insulating film located in a wiring formation region by embedding a conductor in the groove, and then forming the first interlayer A step of selectively removing the conductive film in the groove formed in a portion located in the inductor region of the insulating film; and the step formed in a portion located in the inductor region of the first interlayer insulating film. A step of forming a second interlayer insulating film on the first interlayer insulating film so that a cavity serving as a second dummy pattern is formed in the trench; and a step above or above the second interlayer insulating film. Process to form 3 interlayer insulation film When, and a step of forming an inductor in a portion positioned in the inductor region of the third interlayer insulating film.
　この方法によれば、第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された溝内に第２のダミーパターンとなる空洞を形成するので、インダクタと第２のパターンとの間に生じる寄生容量を小さくすることができる。また、第２のダミーパターンを形成することで、導電膜を除去する際などに第１の層間絶縁膜の上面を平坦に保つことができる。 According to this method, since the cavity serving as the second dummy pattern is formed in the groove formed in the portion located in the inductor region of the first interlayer insulating film, the gap between the inductor and the second pattern is formed. The generated parasitic capacitance can be reduced. Further, by forming the second dummy pattern, the upper surface of the first interlayer insulating film can be kept flat when the conductive film is removed.
　本発明の別の一例に係る半導体装置の製造方法は、半導体基板上に形成されたトランジスタ及び前記半導体基板の上に第１の層間絶縁膜を形成する工程と、前記第１の層間絶縁膜に溝を形成する工程と、前記溝に導電体を埋め込むことで前記第１の層間絶縁膜のうち配線形成領域に位置する部分に配線及び第１のダミーパターンを形成した後、前記第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された前記溝内の前記導電膜を選択的に除去する工程と、前記第１の層間絶縁膜のうち前記インダクタ領域に位置する部分に形成された前記溝内に第２のダミーパターンとなる絶縁膜を埋め込む工程と、前記第１の層間絶縁膜の上方に第２の層間絶縁膜を形成する工程と、前記第２の層間絶縁膜のうち前記インダクタ領域に位置する部分にインダクタを形成する工程とを備えている。 A method of manufacturing a semiconductor device according to another example of the present invention includes a step of forming a transistor formed on a semiconductor substrate, a first interlayer insulating film on the semiconductor substrate, and the first interlayer insulating film. Forming a groove, and forming a wiring and a first dummy pattern in a portion of the first interlayer insulating film located in a wiring formation region by embedding a conductor in the groove, and then forming the first interlayer A step of selectively removing the conductive film in the groove formed in a portion of the insulating film located in the inductor region; and a step of forming the portion of the first interlayer insulating film located in the inductor region. A step of burying an insulating film to be a second dummy pattern in the trench, a step of forming a second interlayer insulating film above the first interlayer insulating film, and the second interlayer insulating film, Located in the inductor area And a step of forming an inductor portion.
　この方法によれば、第２のダミーパターンとして第２の層間絶縁膜に絶縁膜を埋め込むので、インダクタと第２のダミーパターンとの間に生じる寄生容量を低減することができる。そのため、インダクタのＱ値を大きくすることができる。 According to this method, since the insulating film is embedded in the second interlayer insulating film as the second dummy pattern, the parasitic capacitance generated between the inductor and the second dummy pattern can be reduced. Therefore, the Q value of the inductor can be increased.
　本発明の一例に係る半導体装置及びその製造方法によると、第１のダミーパターン及び第２のダミーパターンを形成することで配線層の平坦化を実現しつつ、インダクタと第２のダミーパターンとの間に生じる寄生容量を低減し、インダクタのＱ値を向上させることができる。 According to the semiconductor device and the manufacturing method thereof according to an example of the present invention, the first dummy pattern and the second dummy pattern are formed to realize the planarization of the wiring layer, and the inductor and the second dummy pattern. Parasitic capacitance generated between them can be reduced, and the Q value of the inductor can be improved.
図１（ａ）は、本発明の第１の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図であり、（ｃ）は、配線溝を拡大して示す図である。FIG. 1A is a sectional view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. It is a figure and (c) is a figure which expands and shows a wiring groove | channel. 図２（ａ）～（ｅ）は、本発明の第１の実施形態に係る半導体装置の製造方法を示す断面図である。2A to 2E are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図３（ａ）～（ｄ）は、第１の実施形態に係る半導体装置の製造方法を示す断面図である。3A to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. 図４（ａ）は、本発明の第２の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図である。FIG. 4A is a sectional view showing a semiconductor device according to the second embodiment of the present invention, and FIG. 4B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. FIG. 図５（ａ）～（ｄ）は、本発明の第２の実施形態に係る半導体装置の製造方法を示す断面図である。5A to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 図６（ａ）は、本発明の第３の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図である。FIG. 6A is a sectional view showing a semiconductor device according to the third embodiment of the present invention, and FIG. 6B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. FIG. 図７（ａ）は、本発明の第４の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図である。FIG. 7A is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention, and FIG. 7B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. FIG. 図８（ａ）～（ｅ）は、従来の半導体装置の製造方法を示す断面図である。8A to 8E are cross-sectional views showing a conventional method for manufacturing a semiconductor device. 図９は、埋め込み型配線とインダクタとを備えた従来の半導体装置を示す断面図である。FIG. 9 is a cross-sectional view showing a conventional semiconductor device provided with embedded wiring and an inductor.
　（第１の実施形態）
　以下、本発明の第１の実施形態に係る半導体装置について、図面を参照しながら説明する。 (First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
　図１（ａ）は、本発明の第１の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図であり、（ｃ）は、配線溝を拡大して示す図である。 FIG. 1A is a sectional view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. It is a figure and (c) is a figure which expands and shows a wiring groove | channel.
　本実施形態の半導体装置では、素子分離領域１０２が設けられたシリコン等からなる半導体基板１０１上にＭＯＳトランジスタ１０３等の素子が設けられている。ＭＯＳトランジスタ１０３及び半導体基板１０１上に第１の層間絶縁膜１０４が設けられており、第１の層間絶縁膜１０４上には第２の層間絶縁膜５０６が設けられている。第２の層間絶縁膜５０６には銅などの金属からなる配線１０６が埋め込まれている。この配線１０６はコンタクトプラグ１０５によって半導体基板１０１の不純物拡散領域に接続されている。第２の層間絶縁膜５０６に設けられた配線１０６の上層には、複数の配線層で構成された積層配線構造１１０が形成されており、各配線はビア１０９によって接続されている。配線１０６、ダミーパターン１０７、空洞１０８は各配線層内に形成されている。 In the semiconductor device of this embodiment, elements such as the MOS transistor 103 are provided on the semiconductor substrate 101 made of silicon or the like provided with the element isolation region 102. A first interlayer insulating film 104 is provided on the MOS transistor 103 and the semiconductor substrate 101, and a second interlayer insulating film 506 is provided on the first interlayer insulating film 104. A wiring 106 made of a metal such as copper is embedded in the second interlayer insulating film 506. The wiring 106 is connected to the impurity diffusion region of the semiconductor substrate 101 by a contact plug 105. On the upper layer of the wiring 106 provided in the second interlayer insulating film 506, a laminated wiring structure 110 composed of a plurality of wiring layers is formed, and each wiring is connected by a via 109. The wiring 106, the dummy pattern 107, and the cavity 108 are formed in each wiring layer.
　配線１０６の近傍（配線形成領域内）にはダミーパターン１０７が形成されている。ダミーパターン１０７は第２の層間絶縁膜５０６に形成された溝内に配線１０６の構成材料と同じ材料が埋め込まれることで形成されている。 A dummy pattern 107 is formed in the vicinity of the wiring 106 (in the wiring formation region). The dummy pattern 107 is formed by burying the same material as the constituent material of the wiring 106 in the groove formed in the second interlayer insulating film 506.
　また、配線１０６と同じ配線層のインダクタ領域と、その上層の配線層のインダクタ領域にはダミーパターンとして空洞１０８が設けられている。空洞１０８は第２の層間絶縁膜５０６および各層間絶縁膜に形成された溝内に形成されている。空洞１０８が形成された溝の幅や深さはダミーパターン１０７が設けられた溝と同様であってもよく、溝間の距離は任意に設定可能である。 Also, a cavity 108 is provided as a dummy pattern in the inductor region of the same wiring layer as the wiring 106 and in the inductor region of the upper wiring layer. The cavity 108 is formed in a trench formed in the second interlayer insulating film 506 and each interlayer insulating film. The width and depth of the groove in which the cavity 108 is formed may be the same as the groove in which the dummy pattern 107 is provided, and the distance between the grooves can be arbitrarily set.
　空洞１０８の上層配線層内には配線１０６と同じ材料で構成されたインダクタ１１１が設けられている。インダクタ１１１は例えば渦巻き状の平面形状を有している。 In the upper wiring layer of the cavity 108, an inductor 111 made of the same material as the wiring 106 is provided. The inductor 111 has, for example, a spiral planar shape.
　図１（ｃ）に示すように、ダミーパターン用の溝幅（溝の径）を例えば１μｍとすると、溝上に厚さ５００ｎｍ程度の層間絶縁膜１１３をChemical Vapor Deposition(ＣＶＤ)法などにより形成した場合、溝の底のコーナー部は絶縁膜で埋められずに空洞１１４が形成される（図１（ｃ）左図）。あるいは、層間絶縁膜１１３の形成条件によっては、絶縁膜が溝全体に均一に堆積されず、溝中央部に空洞１１５が形成される。 As shown in FIG. 1C, when the groove width (groove diameter) for the dummy pattern is 1 μm, for example, an interlayer insulating film 113 having a thickness of about 500 nm is formed on the groove by a chemical vapor deposition (CVD) method or the like. In this case, the corner 114 at the bottom of the groove is not filled with the insulating film, and the cavity 114 is formed (the left diagram in FIG. 1C). Alternatively, depending on the formation conditions of the interlayer insulating film 113, the insulating film is not uniformly deposited over the entire groove, and the cavity 115 is formed in the center of the groove.
　本実施形態の半導体装置によれば、インダクタ１１１の下層にダミーパターンとして空洞１０８が形成されているので、インダクタ１１１とダミーパターンとの間に寄生容量は発生しない。このため、インダクタとダミーパターン間に寄生容量が発生した場合に比べて、インダクタ１１１のＱ値を向上させることが可能となる。 According to the semiconductor device of the present embodiment, since the cavity 108 is formed as a dummy pattern below the inductor 111, no parasitic capacitance is generated between the inductor 111 and the dummy pattern. For this reason, the Q value of the inductor 111 can be improved as compared with the case where parasitic capacitance is generated between the inductor and the dummy pattern.
　また、後述のように、インダクタ領域には配線形成領域と同様の溝が形成されているので、配線材料の研磨工程において段差が形成されにくくなっている。このため、各配線層の上面を平坦化することができる。 Further, as described later, since the same groove as the wiring formation region is formed in the inductor region, it is difficult to form a step in the polishing process of the wiring material. For this reason, the upper surface of each wiring layer can be planarized.
　なお、図１（ａ）、（ｂ）に示す例ではインダクタ領域内の各溝に空洞が設けられているが、溝内の一部に空洞が設けられていれば寄生容量の発生を抑えることができる。また、全ての配線層内に空洞１０８が形成されていてもよいが、少なくとも一部の配線層に空洞１０８が形成されていれば寄生容量の発生を抑えることができる。 In the example shown in FIGS. 1A and 1B, a cavity is provided in each groove in the inductor region. However, if a cavity is provided in a part of the groove, generation of parasitic capacitance is suppressed. Can do. Although the cavities 108 may be formed in all the wiring layers, the generation of parasitic capacitance can be suppressed if the cavities 108 are formed in at least some of the wiring layers.
　また、以上ではダミーパターンとして空洞１０８を設ける例を説明したが、ダミーパターンとして金属などの導電体が設けられていなければ、溝内に形成されるのは空洞１０８に限られない。 In the above, an example in which the cavity 108 is provided as a dummy pattern has been described. However, if a conductor such as a metal is not provided as a dummy pattern, the formation in the groove is not limited to the cavity 108.
　　－半導体装置の製造方法－
　次に、本実施形態に係る半導体装置の製造方法について、図面を参照しながら説明する。図２（ａ）～（ｅ）、図３（ａ）～（ｄ）は、本発明の第１の実施形態に係る半導体装置の製造方法を示す断面図である。 -Semiconductor device manufacturing method-
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. 2A to 2E and FIGS. 3A to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
　まず、図２（ａ）に示す工程で、ＳＴＩ等により半導体基板１０１の上部に素子分離領域１０２を形成した後、ゲート電極を有するＭＯＳトランジスタ１０３を公知の方法によって形成する。次に、ＣＶＤ法などによりＭＯＳトランジスタ１０３及び半導体基板１０１上に第１の層間絶縁膜１０４を形成した後、第１の層間絶縁膜１０４を貫通するコンタクトプラグ１０５を形成する。 First, in the step shown in FIG. 2A, after forming an element isolation region 102 on the semiconductor substrate 101 by STI or the like, a MOS transistor 103 having a gate electrode is formed by a known method. Next, after the first interlayer insulating film 104 is formed on the MOS transistor 103 and the semiconductor substrate 101 by the CVD method or the like, the contact plug 105 penetrating the first interlayer insulating film 104 is formed.
　次に、図２（ｂ）に示す工程で、ＣＶＤ法などにより、第１の層間絶縁膜１０４上に第２の層間絶縁膜５０６を形成する。 Next, in the step shown in FIG. 2B, a second interlayer insulating film 506 is formed on the first interlayer insulating film 104 by a CVD method or the like.
　次いで、図２（ｃ）に示す工程で、リソグラフィ及び第２の層間絶縁膜５０６のドライエッチングを行って第２の層間絶縁膜５０６内に配線形成用の溝５０７、配線形成領域におけるダミーパターン形成用の溝５０８、インダクタ領域におけるダミーパターン形成用の溝５０９を形成する。溝５０７の幅は例えば２００ｎｍ程度であり、溝５０８、５０９の幅は例えば２００ｎｍ程度である。溝５０９同士の間隔は例えば２μｍ程度である。 Next, in the step shown in FIG. 2C, lithography and dry etching of the second interlayer insulating film 506 are performed to form a wiring formation groove 507 in the second interlayer insulating film 506 and a dummy pattern in the wiring forming region. A trench 508 for forming a dummy pattern in the inductor region is formed. The width of the groove 507 is about 200 nm, for example, and the width of the grooves 508 and 509 is about 200 nm, for example. The interval between the grooves 509 is about 2 μm, for example.
　次に、図２（ｄ）に示す工程で、銅膜（導電体）５１０を溝５０７、５０８、５０９を含む基板の上面上に形成する。銅膜５１０は例えばめっき法により形成される。 2D, a copper film (conductor) 510 is formed on the upper surface of the substrate including the grooves 507, 508, and 509 in the step shown in FIG. The copper film 510 is formed by, for example, a plating method.
　次に、図２（ｅ）に示す工程で、銅膜５１０をＣＭＰにより研磨することで銅膜５１０のうち溝の外部に設けられた部分を除去し、配線１０６と、配線１０６の近傍に位置し、溝５０８内に埋め込まれた銅膜（ダミーパターン１０７）と、溝５０９内に埋め込まれた銅膜５１３とを形成する。 Next, in the step shown in FIG. 2E, the copper film 510 is polished by CMP to remove a portion of the copper film 510 provided outside the groove, and the wiring 106 and the position near the wiring 106 are removed. Then, a copper film (dummy pattern 107) embedded in the groove 508 and a copper film 513 embedded in the groove 509 are formed.
　次に、図３（ａ）に示す工程で、基板（作製中の半導体装置）のうち配線形成領域を覆い、インダクタ領域に開口が形成されたレジストマスク５１４を形成する。レジストマスク５１４は例えばリソグラフィを用いて形成される。 Next, in the step shown in FIG. 3A, a resist mask 514 that covers the wiring formation region of the substrate (semiconductor device being fabricated) and has an opening in the inductor region is formed. The resist mask 514 is formed using lithography, for example.
　次に、図３（ｂ）に示す工程で、例えば硫酸などの薬液を用いたウェットエッチングによりインダクタ領域内に配置された銅膜５１３を除去する。これにより、溝５０９内は空洞となる。 Next, in the step shown in FIG. 3B, the copper film 513 disposed in the inductor region is removed by wet etching using a chemical solution such as sulfuric acid. Thereby, the inside of the groove 509 becomes a cavity.
　次いで、図３（ｃ）に示す工程で、レジストマスク５１４を除去する。 Next, the resist mask 514 is removed in the step shown in FIG.
　続いて、図３（ｄ）に示す工程で、第２の層間絶縁膜５０６及び配線１０６上に絶縁膜からなる層間絶縁膜を形成する。この際に、溝５０９内は絶縁膜で完全に埋め込まれないので、溝５０９内に空洞１０８が形成される。その後、以上の配線及びダミーパターンの形成工程を繰り返すことにより、積層配線構造１１０を形成する。ここで、上層の配線層内には配線１０６と同じ銅などからなるインダクタ１１１を形成する。 Subsequently, in the step shown in FIG. 3D, an interlayer insulating film made of an insulating film is formed on the second interlayer insulating film 506 and the wiring 106. At this time, since the groove 509 is not completely filled with an insulating film, the cavity 108 is formed in the groove 509. Thereafter, the multilayer wiring structure 110 is formed by repeating the above-described wiring and dummy pattern forming steps. Here, the inductor 111 made of the same copper as the wiring 106 is formed in the upper wiring layer.
　本実施形態の製造方法で作製された半導体装置では、インダクタ１１１の下層に設けられたダミーパターンとして空洞１０８が形成されているので、インダクタ１１１とダミーパターンとの間に寄生容量が発生しない。このため、インダクタの下方に金属からなるダミーパターンを設ける場合に比べて寄生容量を大きく低減することができ、インダクタ１１１のＱ値を十分に高くすることが可能となる。 In the semiconductor device manufactured by the manufacturing method of the present embodiment, since the cavity 108 is formed as a dummy pattern provided in the lower layer of the inductor 111, no parasitic capacitance is generated between the inductor 111 and the dummy pattern. For this reason, the parasitic capacitance can be greatly reduced as compared with the case where a dummy pattern made of metal is provided below the inductor, and the Q value of the inductor 111 can be sufficiently increased.
　また、インダクタ領域においても配線形成領域と同様に各層間絶縁膜にダミーパターンが形成されているので、配線層内に生じる段差が緩和されている。そのため、段差の形成に起因する接続不良などの不具合を抑えつつ、Ｑ値の優れたインダクタを形成することが可能となる。 Also, in the inductor region, since the dummy pattern is formed in each interlayer insulating film as in the wiring formation region, the step generated in the wiring layer is reduced. For this reason, it is possible to form an inductor having an excellent Q value while suppressing problems such as poor connection due to the formation of a step.
　　(第２の実施形態)
　図４（ａ）は、本発明の第２の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図である。 (Second Embodiment)
FIG. 4A is a sectional view showing a semiconductor device according to the second embodiment of the present invention, and FIG. 4B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. FIG.
　図４（ａ）、（ｂ）に示すように、本実施形態の半導体装置は、第１の実施形態に係る半導体装置と同様に、素子分離領域１０２が形成された半導体基板１０１上に形成されたＭＯＳトランジスタ１０３と、半導体基板１０１上に形成された第１の層間絶縁膜１０４と、第１の層間絶縁膜１０４上に形成された第２の層間絶縁膜５０６と、第２の層間絶縁膜５０６に形成された配線１０６と、配線１０６に接続されたコンタクトプラグ１０５と、ダミーパターン１０７と、インダクタ領域内の第２の層間絶縁膜５０６に形成されたダミーパターン２０８とを備えている。上層の配線層にはインダクタ１１１が形成されている。 As shown in FIGS. 4A and 4B, the semiconductor device of the present embodiment is formed on the semiconductor substrate 101 on which the element isolation region 102 is formed, like the semiconductor device according to the first embodiment. MOS transistor 103, first interlayer insulating film 104 formed on semiconductor substrate 101, second interlayer insulating film 506 formed on first interlayer insulating film 104, and second interlayer insulating film A wiring 106 formed on the wiring 506, a contact plug 105 connected to the wiring 106, a dummy pattern 107, and a dummy pattern 208 formed on the second interlayer insulating film 506 in the inductor region are provided. An inductor 111 is formed in the upper wiring layer.
　また、第２の層間絶縁膜５０６に設けられた配線１０６の上層には複数の配線層で構成された積層配線構造２１０が形成されており、各配線はビア１０９により接続されている。 Further, a laminated wiring structure 210 composed of a plurality of wiring layers is formed above the wiring 106 provided in the second interlayer insulating film 506, and each wiring is connected by a via 109.
　配線１０６の近傍に設けられたダミーパターン１０７は溝内に埋め込まれ、配線１０６の構成材料と同じ銅などからなっている。 The dummy pattern 107 provided in the vicinity of the wiring 106 is embedded in the groove and is made of the same copper as the constituent material of the wiring 106.
　本実施形態の半導体装置が第１の半導体装置と異なるのは、インダクタ領域内の層間絶縁膜内に溝が所定の間隔で形成されており、当該溝内にダミーパターン２０８として絶縁膜が設けられている点である。このダミーパターン２０８は、例えばシリコン窒化膜等の絶縁体で構成されている。 The semiconductor device of this embodiment is different from the first semiconductor device in that grooves are formed in the interlayer insulating film in the inductor region at a predetermined interval, and an insulating film is provided as a dummy pattern 208 in the groove. It is a point. The dummy pattern 208 is made of an insulator such as a silicon nitride film.
　本実施形態の半導体装置では、インダクタ領域内のダミーパターン２０８として絶縁膜が設けられているので、インダクタ１１１とダミーパターン２０８との間に寄生容量が発生しない。このため、インダクタ１１１のＱ値を高くすることができる。 In the semiconductor device of this embodiment, since an insulating film is provided as the dummy pattern 208 in the inductor region, no parasitic capacitance is generated between the inductor 111 and the dummy pattern 208. For this reason, the Q value of the inductor 111 can be increased.
　また、後述のように、インダクタ領域には配線形成領域と同様の溝が形成されているので、配線材料の研磨工程において段差が形成されにくくなっている。このため、各配線層の上面を平坦化することができる。 Further, as described later, since the same groove as the wiring formation region is formed in the inductor region, it is difficult to form a step in the polishing process of the wiring material. For this reason, the upper surface of each wiring layer can be planarized.
　なお、図４（ａ）、（ｂ）に示す例ではインダクタ領域内の各溝に絶縁膜が設けられているが、溝内の一部に絶縁膜が設けられていれば寄生容量の発生を抑えることができる。また、全ての配線層内に絶縁膜が形成されていてもよいが、少なくとも一部の配線層に絶縁膜が形成されていれば寄生容量の発生を抑えることができる。 In the example shown in FIGS. 4A and 4B, an insulating film is provided in each groove in the inductor region. However, if an insulating film is provided in a part of the groove, parasitic capacitance is generated. Can be suppressed. Insulating films may be formed in all the wiring layers, but if an insulating film is formed in at least some of the wiring layers, the generation of parasitic capacitance can be suppressed.
　なお、ダミーパターン２０８である絶縁膜の誘電率が、当該ダミーパターンを設けた層間絶縁膜の誘電率に比べて低ければ、インダクタとダミーパターンとの間の寄生容量を更に低減でき、より高いＱ値を実現することが可能となる。 If the dielectric constant of the insulating film which is the dummy pattern 208 is lower than the dielectric constant of the interlayer insulating film provided with the dummy pattern, the parasitic capacitance between the inductor and the dummy pattern can be further reduced, and the higher Q The value can be realized.
　また、ダミーパターン２０８は単一の絶縁膜で構成されていてもよいが、シリコン窒化膜や酸化膜の積層体であっても同様の効果がある。 In addition, the dummy pattern 208 may be composed of a single insulating film, but the same effect can be obtained even if it is a laminated body of a silicon nitride film or an oxide film.
　　－半導体装置の製造方法－
　図５（ａ）～（ｄ）は、本発明の第２の実施形態に係る半導体装置の製造方法を示す断面図である。 -Semiconductor device manufacturing method-
5A to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
　 まず、第１の実施形態で説明したように、図２（ａ）～（ｅ）、及び図３（ａ）～（ｃ）に示す工程によって、素子分離領域１０２が形成された半導体基板１０１上にＭＯＳトランジスタ１０３、第１の層間絶縁膜１０４、コンタクトプラグ１０５、第２の層間絶縁膜５０６、配線１０６、ダミーパターン１０７、溝５０９などを形成する。図５（ａ）は図３（ｃ）と同じ状態の半導体装置を示している。 First, as described in the first embodiment, on the semiconductor substrate 101 on which the element isolation region 102 is formed by the steps shown in FIGS. 2A to 2E and FIGS. 3A to 3C. Then, the MOS transistor 103, the first interlayer insulating film 104, the contact plug 105, the second interlayer insulating film 506, the wiring 106, the dummy pattern 107, the groove 509, and the like are formed. FIG. 5A shows the semiconductor device in the same state as FIG.
　次に、図５（ｂ）に示す工程で、溝５０９を含む基板の上面全体に例えばシリコン窒化膜からなる絶縁膜７０９を形成する。ここで、絶縁膜７０９は溝５０９内に埋め込まれている。 Next, in the step shown in FIG. 5B, an insulating film 709 made of, for example, a silicon nitride film is formed on the entire upper surface of the substrate including the groove 509. Here, the insulating film 709 is embedded in the trench 509.
　次に、図５（ｃ）に示す工程で、ＣＭＰによって配線１０６や第２の層間絶縁膜５０６が露出するまで絶縁膜７０９を研磨し、溝５０９内に埋め込まれた絶縁膜７０９からなるダミーパターン２０８を形成する。 Next, in the step shown in FIG. 5C, the insulating film 709 is polished by CMP until the wiring 106 and the second interlayer insulating film 506 are exposed, and a dummy pattern made of the insulating film 709 embedded in the trench 509 is formed. 208 is formed.
　その後、図５（ｄ）に示すように、配線１０６、ダミーパターン１０７、２０８の形成工程を繰り返すことにより、積層配線構造２１０を形成する。ここで、上層の配線層内には配線１０６と同じ銅などからなるインダクタ１１１を形成する。 Thereafter, as shown in FIG. 5D, the laminated wiring structure 210 is formed by repeating the process of forming the wiring 106 and the dummy patterns 107 and 208. Here, the inductor 111 made of the same copper as the wiring 106 is formed in the upper wiring layer.
　本実施形態の製造方法で作製された半導体装置では、インダクタ１１１の下層に絶縁膜で構成されたダミーパターン２０８が形成されているので、インダクタ１１１とダミーパターン２０８との間に寄生容量が発生しない。このため、インダクタの下方に金属からなるダミーパターンを設ける場合に比べて寄生容量を大きく低減することができ、インダクタ１１１のＱ値を十分に高くすることが可能となる。 In the semiconductor device manufactured by the manufacturing method of the present embodiment, since the dummy pattern 208 made of an insulating film is formed below the inductor 111, no parasitic capacitance is generated between the inductor 111 and the dummy pattern 208. . For this reason, the parasitic capacitance can be greatly reduced as compared with the case where a dummy pattern made of metal is provided below the inductor, and the Q value of the inductor 111 can be sufficiently increased.
　また、インダクタ領域においても配線形成領域と同様に各層間絶縁膜にダミーパターンが形成されているので、配線層内に生じる段差が緩和されている。そのため、段差の形成に起因する接続不良などの不具合を抑えつつ、Ｑ値の優れたインダクタを形成することが可能となる。 Also, in the inductor region, since the dummy pattern is formed in each interlayer insulating film as in the wiring formation region, the step generated in the wiring layer is reduced. For this reason, it is possible to form an inductor having an excellent Q value while suppressing problems such as poor connection due to the formation of a step.
　　(第３の実施形態)
　図６（ａ）は、本発明の第３の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図である。 (Third embodiment)
FIG. 6A is a sectional view showing a semiconductor device according to the third embodiment of the present invention, and FIG. 6B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. FIG.
　図６（ａ）、（ｂ）に示すように、本実施形態の半導体装置は、第１の実施形態に係る半導体装置と同様に、素子分離領域１０２が形成された半導体基板１０１上に形成されたＭＯＳトランジスタ１０３と、半導体基板１０１上に形成された第１の層間絶縁膜１０４と、第１の層間絶縁膜１０４上に形成された第２の層間絶縁膜５０６と、第２の層間絶縁膜５０６に形成された配線１０６と、配線１０６に接続されたコンタクトプラグ１０５と、ダミーパターン３０７と、インダクタ領域内の第２の層間絶縁膜５０６に形成されたダミーパターン３０８とを備えている。上層の配線層にはインダクタ１１１が形成されている。 As shown in FIGS. 6A and 6B, the semiconductor device of this embodiment is formed on the semiconductor substrate 101 in which the element isolation region 102 is formed, as in the semiconductor device according to the first embodiment. MOS transistor 103, first interlayer insulating film 104 formed on semiconductor substrate 101, second interlayer insulating film 506 formed on first interlayer insulating film 104, and second interlayer insulating film A wiring 106 formed on the wiring 506, a contact plug 105 connected to the wiring 106, a dummy pattern 307, and a dummy pattern 308 formed on the second interlayer insulating film 506 in the inductor region are provided. An inductor 111 is formed in the upper wiring layer.
　また、第２の層間絶縁膜５０６に設けられた配線１０６の上層には複数の配線層で構成された積層配線構造３１０が形成されており、各配線はビア１０９により接続されている。 Further, a laminated wiring structure 310 composed of a plurality of wiring layers is formed above the wiring 106 provided in the second interlayer insulating film 506, and each wiring is connected by a via 109.
　配線１０６の近傍に設けられたダミーパターン３０７は溝内に埋め込まれ、配線１０６の構成材料と同じ銅などからなっている。 The dummy pattern 307 provided in the vicinity of the wiring 106 is embedded in the groove and is made of the same copper as the constituent material of the wiring 106.
　本実施形態の半導体装置が第１の半導体装置と異なるのは、ダミーパターン３０８が溝に埋め込まれた導電体で構成されていること、及びインダクタ領域内のダミーパターン３０８とインダクタ１１１とが平面的に見て少なくとも部分的に重ならないことである。特に、ダミーパターン３０８とインダクタ１１１とが平面的に見て重ならなければより好ましい。ダミーパターン３０８は配線１０６と同じ材料で構成されていてもよい。インダクタ１１１、配線１０６、ダミーパターン３０８は例えば銅やＡｌ、あるいは金属の積層膜などで構成されていてもよい。 The semiconductor device of this embodiment is different from the first semiconductor device in that the dummy pattern 308 is composed of a conductor embedded in the groove, and the dummy pattern 308 and the inductor 111 in the inductor region are planar. Is at least partially non-overlapping. In particular, it is more preferable if the dummy pattern 308 and the inductor 111 do not overlap in plan view. The dummy pattern 308 may be made of the same material as the wiring 106. The inductor 111, the wiring 106, and the dummy pattern 308 may be made of, for example, copper, Al, or a laminated film of metal.
　また、図示はしていないが、インダクタ１１１の直下のダミーパターン３０８が平面的に見て重ならないようにしておけば、それより下層のダミーパターン３０８が平面的にみて重なっていたとしても、半導体基板１の垂直方向の距離が離れているため、寄生容量を低減する効果は発揮される。 Although not shown, if the dummy pattern 308 immediately below the inductor 111 is not overlapped in plan view, even if the lower dummy pattern 308 overlaps in plan view, the semiconductor Since the vertical distance of the substrate 1 is increased, the effect of reducing the parasitic capacitance is exhibited.
　インダクタ１１１は１つの配線層内にコイル状に形成されており、インダクタ１１１を形成する金属膜の幅は例えば数μｍから１０μｍ程度であり、当該金属膜同士の間隔は数μｍ～２０μｍ程度である。一方、配線形成領域内のダミーパターン３０７の幅は１μｍ程度、配置間隔は例えば２μｍ程度である。なお、インダクタ１１１を構成する金属膜同士の間にダミーパターン３０８が形成されていてもよい。 The inductor 111 is formed in a coil shape in one wiring layer, and the width of the metal film forming the inductor 111 is, for example, about several μm to 10 μm, and the distance between the metal films is about several μm to 20 μm. . On the other hand, the width of the dummy pattern 307 in the wiring formation region is about 1 μm, and the arrangement interval is about 2 μm, for example. A dummy pattern 308 may be formed between the metal films constituting the inductor 111.
　本実施形態の半導体装置では、ダミーパターン３０８がインダクタ１１１の直下方に配置されないので、ダミーパターンとインダクタとが平面的に見て重なる場合に比べてダミーパターン３０８とインダクタ１１１との距離を大きくすることができる。このため、ダミーパターン３０８とインダクタ１１１との間に生じる寄生容量を低減することができ、インダクタ１１１のＱ値を向上させることができる。 In the semiconductor device according to the present embodiment, since the dummy pattern 308 is not disposed immediately below the inductor 111, the distance between the dummy pattern 308 and the inductor 111 is increased as compared with the case where the dummy pattern and the inductor overlap in plan view. be able to. For this reason, the parasitic capacitance generated between the dummy pattern 308 and the inductor 111 can be reduced, and the Q value of the inductor 111 can be improved.
　　(第４の実施形態)
　図７（ａ）は、本発明の第４の実施形態に係る半導体装置を示す断面図であり、（ｂ）は、当該半導体装置の配線形成領域（左側）とインダクタ領域（右側）を示す平面図である。 (Fourth embodiment)
FIG. 7A is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention, and FIG. 7B is a plan view showing a wiring formation region (left side) and an inductor region (right side) of the semiconductor device. FIG.
　図７（ａ）、（ｂ）に示すように、本実施形態の半導体装置は、第１の実施形態に係る半導体装置と同様に、素子分離領域１０２が形成された半導体基板１０１上に形成されたＭＯＳトランジスタ１０３と、半導体基板１０１上に形成された第１の層間絶縁膜１０４と、第１の層間絶縁膜１０４上に形成された第２の層間絶縁膜５０６と、第２の層間絶縁膜５０６に形成された配線１０６と、配線１０６に接続されたコンタクトプラグ１０５と、ダミーパターン４０７と、インダクタ領域内の第２の層間絶縁膜５０６に形成されたダミーパターン４０８とを備えている。上層の配線層にはインダクタ１１１が形成されている。 As shown in FIGS. 7A and 7B, the semiconductor device according to the present embodiment is formed on the semiconductor substrate 101 on which the element isolation region 102 is formed, similarly to the semiconductor device according to the first embodiment. MOS transistor 103, first interlayer insulating film 104 formed on semiconductor substrate 101, second interlayer insulating film 506 formed on first interlayer insulating film 104, and second interlayer insulating film A wiring 106 formed on the wiring 506, a contact plug 105 connected to the wiring 106, a dummy pattern 407, and a dummy pattern 408 formed on the second interlayer insulating film 506 in the inductor region are provided. An inductor 111 is formed in the upper wiring layer.
　また、第２の層間絶縁膜５０６に設けられた配線１０６の上層には複数の配線層で構成された積層配線構造４１０が形成されており、各配線はビア１０９により接続されている。配線１０６、ダミーパターン４０７、ダミーパターン４０８は各配線層内に形成されている。 Further, a laminated wiring structure 410 composed of a plurality of wiring layers is formed above the wiring 106 provided in the second interlayer insulating film 506, and each wiring is connected by a via 109. The wiring 106, the dummy pattern 407, and the dummy pattern 408 are formed in each wiring layer.
　配線１０６の近傍に設けられたダミーパターン４０７は溝内に埋め込まれ、配線１０６の構成材料と同じ銅などからなっている。 The dummy pattern 407 provided in the vicinity of the wiring 106 is embedded in the groove and is made of the same copper as the constituent material of the wiring 106.
　本実施形態の半導体装置が第１の半導体装置と異なるのは、インダクタ領域においてインダクタ１１１の下方に形成されたダミーパターン４０８の面積率（所定領域において、基板主面の全体中のダミーパターンが占める面積の割合）が配線形成領域におけるダミーパターン４０７の面積率よりも小さいことである。なお、ダミーパターン４０８は配線１０６と同じ材料で構成されていてもよく、例えば銅やＡｌ、あるいは金属の積層膜などで構成されていてもよい。 The semiconductor device of this embodiment is different from the first semiconductor device in that the area ratio of the dummy pattern 408 formed below the inductor 111 in the inductor region (the dummy pattern in the entire main surface of the substrate occupies the predetermined region). (Area ratio) is smaller than the area ratio of the dummy pattern 407 in the wiring formation region. The dummy pattern 408 may be made of the same material as that of the wiring 106, and may be made of, for example, copper, Al, or a laminated film of metal.
　図７（ａ）、（ｂ）に示す例では、ダミーパターン４０８の大きさはダミーパターン４０７と同等にしてダミーパターン４０８の形成箇所をダミーパターン４０７よりも少なくしている。すなわち、ダミーパターン４０８のダミーパターン密度をダミーパターン４０７の密度や配線１０６の配線密度よりも小さくしている。ここでの、「ダミーパターンの密度」とは、単位面積当たりのダミーパターン面積を指す。なお、ダミーパターン４０８のサイズをダミーパターン４０７よりも小さくしてダミーパターン４０７と同等の数だけ設けてもよい。 7A and 7B, the size of the dummy pattern 408 is equal to that of the dummy pattern 407, and the number of the dummy patterns 408 formed is smaller than that of the dummy pattern 407. That is, the dummy pattern density of the dummy pattern 408 is set lower than the density of the dummy pattern 407 and the wiring density of the wiring 106. Here, “dummy pattern density” refers to a dummy pattern area per unit area. Note that the size of the dummy patterns 408 may be smaller than that of the dummy patterns 407 and may be provided in the same number as the dummy patterns 407.
　本実施形態の半導体装置では、ダミーパターン４０８の面積率をダミーパターン４０７と同様の面積率で配置した場合に比べてインダクタ１１１とダミーパターン４０８とがオーバーラップする面積を小さくすることができる。そのため、インダクタ１１１とダミーパターン４０８との間に生じる寄生容量を低減し、インダクタ１１１のＱ値を高くすることができる。 In the semiconductor device of this embodiment, the area where the inductor 111 and the dummy pattern 408 overlap can be reduced as compared with the case where the area ratio of the dummy pattern 408 is arranged at the same area ratio as the dummy pattern 407. Therefore, the parasitic capacitance generated between the inductor 111 and the dummy pattern 408 can be reduced, and the Q value of the inductor 111 can be increased.
　ダミーパターンの形成については、基板上面の平坦性を確保するために、局所的な面積率が規定されているが、実際のレイアウトを配置するに当たってはマスクレイアウトツールにて自動で発生される。そのため、通常は一定の値とならず、規定されるダミーパターンの面積率は数１０％の幅を持った値となる。本実施形態の半導体装置においては、配線形成領域とインダクタ領域のそれぞれでダミーパターンの面積率に、例えば１０％以上の差を設ける。 Regarding the formation of the dummy pattern, a local area ratio is defined in order to ensure the flatness of the upper surface of the substrate. However, when the actual layout is arranged, it is automatically generated by the mask layout tool. For this reason, it is not normally a constant value, and the area ratio of the defined dummy pattern is a value having a width of several tens of percent. In the semiconductor device of the present embodiment, a difference of, for example, 10% or more is provided in the area ratio of the dummy pattern in each of the wiring formation region and the inductor region.
　以上で説明した例は本発明の一例であって、各部材の形状や構成材料、ダミーパターンの個数、平面面積などは本発明の趣旨を逸脱しない範囲において適宜変更可能である。また、各実施形態に係る半導体装置の構成を適宜組み合わせてもよい。 The example described above is an example of the present invention, and the shape, constituent material, the number of dummy patterns, the planar area, etc. of each member can be appropriately changed without departing from the spirit of the present invention. Moreover, you may combine suitably the structure of the semiconductor device which concerns on each embodiment.
　以上説明したように、本発明の一例に係る半導体装置及びその製造方法によると、複数の配線層に形成された埋め込み型の金属配線と、インダクタとを搭載する半導体装置を形成する方法等に有用である。 As described above, according to the semiconductor device and the manufacturing method thereof according to an example of the present invention, it is useful for a method of forming a semiconductor device in which embedded metal wiring formed in a plurality of wiring layers and an inductor are mounted. It is.
１０１　　　半導体基板
１０２　　　素子分離領域
１０３　　　ＭＯＳトランジスタ
１０４　　　第１の層間絶縁膜
１０５　　　コンタクトプラグ
１０６　　　配線
１０７、２０８、３０７、３０８、４０７、４０８　　　ダミーパターン
１０８、１１４、１１５　　　空洞
１０９　　　ビア
１１０、２１０、３１０、４１０　　　積層配線構造
１１１　　　インダクタ
１１３　　　層間絶縁膜
５０６　　　第２の層間絶縁膜
５０７、５０８、５０９　溝
５１０、５１３　　　銅膜
５１４　　　レジストマスク
７０９　　　絶縁膜 101 Semiconductor substrate 102 Element isolation region 103 MOS transistor 104 First interlayer insulating film 105 Contact plug 106 Wiring 107, 208, 307, 308, 407, 408 Dummy pattern 108, 114, 115 Cavity 109 Via 110, 210, 310, 410 Laminated wiring structure 111 Inductor 113 Interlayer insulating film 506 Second interlayer insulating films 507, 508, 509 Groove 510, 513 Copper film 514 Resist mask 709 Insulating film

Claims (13)

  1. 　配線形成領域と、インダクタ領域とを備えた半導体装置であって、
    　半導体基板と、
    　前記半導体基板上または上方に形成された第１の層間絶縁膜と、
    　前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた配線と、
    　前記第１の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれた第２のダミーパターンと、
    　前記第１の層間絶縁膜の上または上方に形成された第２の層間絶縁膜と、
    　前記第２のダミーパターンの上方であって、前記第２の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれたインダクタとを備え、
    　前記第２のダミーパターンとして導電体が形成されていない半導体装置。     A semiconductor device comprising a wiring formation region and an inductor region,
    A semiconductor substrate;
    A first interlayer insulating film formed on or over the semiconductor substrate;
    A wiring embedded in a portion of the first interlayer insulating film located in the wiring formation region;
    A second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region;
    A second interlayer insulating film formed on or above the first interlayer insulating film;
    An inductor embedded in a portion of the second interlayer insulating film located in the inductor region above the second dummy pattern;
    A semiconductor device in which a conductor is not formed as the second dummy pattern.
  2. 　請求項１に記載の半導体装置において、
    　前記第２のダミーパターンは、前記第１の層間絶縁膜内に形成された空洞である半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device, wherein the second dummy pattern is a cavity formed in the first interlayer insulating film.
  3. 　請求項１に記載の半導体装置において、
    　前記第２のダミーパターンは、前記第１の層間絶縁膜に埋め込まれた絶縁膜である半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device, wherein the second dummy pattern is an insulating film embedded in the first interlayer insulating film.
  4. 　請求項３に記載の半導体装置において、
    　前記絶縁膜の誘電率は、前記第１の層間絶縁膜の誘電率よりも低い半導体装置。     The semiconductor device according to claim 3.
    A semiconductor device wherein a dielectric constant of the insulating film is lower than a dielectric constant of the first interlayer insulating film.
  5. 　請求項１に記載の半導体装置において、
    　前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた第１のダミーパターンをさらに備えている半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device further comprising a first dummy pattern embedded in a portion of the first interlayer insulating film located in the wiring formation region.
  6. 　配線形成領域と、インダクタ領域とを備えた半導体装置であって、
    　半導体基板と、
    　前記半導体基板上または上方に形成された第１の層間絶縁膜と、
    　前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた配線及び第１のダミーパターンと、
    　前記第１の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれた第２のダミーパターンと、
    　前記第１の層間絶縁膜の上または上方に形成された第２の層間絶縁膜と、
    　前記第２のダミーパターンの上方であって、前記第２の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれたインダクタとを備え、
    　前記第２のダミーパターンと前記インダクタとは、平面的に見て少なくとも一部が重ならない半導体装置。     A semiconductor device comprising a wiring formation region and an inductor region,
    A semiconductor substrate;
    A first interlayer insulating film formed on or over the semiconductor substrate;
    A wiring and a first dummy pattern embedded in a portion of the first interlayer insulating film located in the wiring formation region;
    A second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region;
    A second interlayer insulating film formed on or above the first interlayer insulating film;
    An inductor embedded in a portion of the second interlayer insulating film located in the inductor region above the second dummy pattern;
    A semiconductor device in which the second dummy pattern and the inductor do not overlap at least partially when seen in a plan view.
  7. 　請求項６に記載の半導体装置において、
    　前記第２のダミーパターンは、前記第１の層間絶縁膜に埋め込まれ、前記配線と同じ材料で構成されている半導体装置。     The semiconductor device according to claim 6.
    The second dummy pattern is a semiconductor device embedded in the first interlayer insulating film and made of the same material as the wiring.
  8. 　請求項６に記載の半導体装置において、
    　前記第２のダミーパターンと前記インダクタとは、平面的に見て重ならない半導体装置。     The semiconductor device according to claim 6.
    A semiconductor device in which the second dummy pattern and the inductor do not overlap in plan view.
  9. 　配線形成領域と、インダクタ領域とを備えた半導体装置であって、
    　半導体基板と、
    　前記半導体基板上または上方に形成された第１の層間絶縁膜と、
    　前記第１の層間絶縁膜のうち前記配線形成領域内に位置する部分に埋め込まれた配線及び第１のダミーパターンと、
    　前記第１の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれた第２のダミーパターンと、
    　前記第１の層間絶縁膜の上または上方に形成された第２の層間絶縁膜と、
    　前記第２のダミーパターンの上方であって、前記第２の層間絶縁膜のうち前記インダクタ領域内に位置する部分に埋め込まれたインダクタとを備え、
    　前記インダクタ領域内での前記第２のダミーパターンの面積率は、前記配線形成領域内での前記第１のダミーパターンの面積率よりも小さい半導体装置。     A semiconductor device comprising a wiring formation region and an inductor region,
    A semiconductor substrate;
    A first interlayer insulating film formed on or over the semiconductor substrate;
    A wiring and a first dummy pattern embedded in a portion of the first interlayer insulating film located in the wiring formation region;
    A second dummy pattern embedded in a portion of the first interlayer insulating film located in the inductor region;
    A second interlayer insulating film formed on or above the first interlayer insulating film;
    An inductor embedded in a portion of the second interlayer insulating film located in the inductor region above the second dummy pattern;
    The area ratio of the second dummy pattern in the inductor region is smaller than the area ratio of the first dummy pattern in the wiring formation region.
  10. 　請求項９に記載の半導体装置において、
    　前記第２のダミーパターンの前記インダクタ領域における密度は前記配線の前記配線形成領域における配線密度よりも小さい半導体装置。     The semiconductor device according to claim 9.
    A semiconductor device in which a density of the second dummy pattern in the inductor region is smaller than a wiring density in the wiring formation region of the wiring.
  11. 　請求項９に記載の半導体装置において、
    　前記第２のダミーパターンは、前記第１の層間絶縁膜に埋め込まれ、前記配線と同じ材料で構成されている半導体装置。     The semiconductor device according to claim 9.
    The second dummy pattern is a semiconductor device embedded in the first interlayer insulating film and made of the same material as the wiring.
  12. 　半導体基板上に形成されたトランジスタ及び前記半導体基板の上に第１の層間絶縁膜を形成する工程と、
    　前記第１の層間絶縁膜に溝を形成する工程と、
    　前記溝に導電体を埋め込むことで前記第１の層間絶縁膜のうち配線形成領域に位置する部分に配線及び第１のダミーパターンを形成した後、前記第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された前記溝内の前記導電膜を選択的に除去する工程と、
    　前記第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された前記溝内に第２のダミーパターンとなる空洞ができるように、前記第１の層間絶縁膜上に第２の層間絶縁膜を形成する工程と、
    　前記第２の層間絶縁膜の上または上方に第３の層間絶縁膜を形成する工程と、
    　前記第３の層間絶縁膜のうち前記インダクタ領域に位置する部分にインダクタを形成する工程とを備えている半導体装置の製造方法。     Forming a transistor formed on a semiconductor substrate and a first interlayer insulating film on the semiconductor substrate;
    Forming a groove in the first interlayer insulating film;
    A conductor and a first dummy pattern are formed in a portion of the first interlayer insulating film located in the wiring forming region by embedding a conductor in the groove, and then in the inductor region of the first interlayer insulating film. Selectively removing the conductive film in the groove formed in the located portion;
    A second interlayer insulating film is formed on the first interlayer insulating film so that a cavity serving as a second dummy pattern is formed in the groove formed in a portion of the first interlayer insulating film located in the inductor region. Forming a film;
    Forming a third interlayer insulating film on or above the second interlayer insulating film;
    And a step of forming an inductor in a portion of the third interlayer insulating film located in the inductor region.
  13. 　半導体基板上に形成されたトランジスタ及び前記半導体基板の上に第１の層間絶縁膜を形成する工程と、
    　前記第１の層間絶縁膜に溝を形成する工程と、
    　前記溝に導電体を埋め込むことで前記第１の層間絶縁膜のうち配線形成領域に位置する部分に配線及び第１のダミーパターンを形成した後、前記第１の層間絶縁膜のうちインダクタ領域に位置する部分に形成された前記溝内の前記導電膜を選択的に除去する工程と、
    　前記第１の層間絶縁膜のうち前記インダクタ領域に位置する部分に形成された前記溝内に第２のダミーパターンとなる絶縁膜を埋め込む工程と、
    　前記第１の層間絶縁膜の上方に第２の層間絶縁膜を形成する工程と、
    　前記第２の層間絶縁膜のうち前記インダクタ領域に位置する部分にインダクタを形成する工程とを備えている半導体装置の製造方法。     Forming a transistor formed on a semiconductor substrate and a first interlayer insulating film on the semiconductor substrate;
    Forming a groove in the first interlayer insulating film;
    A conductor and a first dummy pattern are formed in a portion of the first interlayer insulating film located in the wiring forming region by embedding a conductor in the groove, and then in the inductor region of the first interlayer insulating film. Selectively removing the conductive film in the groove formed in the located portion;
    Embedding an insulating film to be a second dummy pattern in the groove formed in a portion of the first interlayer insulating film located in the inductor region;
    Forming a second interlayer insulating film above the first interlayer insulating film;
    Forming a inductor in a portion of the second interlayer insulating film located in the inductor region.
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