TW201903957A - Methods for forming isolation blocks of the semiconductor devices, semiconductor devices and methods for manufacturing the same - Google Patents

Abstract

A method for manufacturing an insulation block of a semiconductor device includes providing a semiconductor substrate, performing an etching process to form a plurality of trenches which are parallel to each other in the semiconductor substrate, wherein a plurality of strip structures are between the trenches. The strip structures and the trenches occupied a first region in the semiconductor substrate, and the strip structures are staggerly arranged with the trenches. The method further includes performing a thermal oxidation process, such that the strip structures are oxidized to form a plurality of oxidized portions, wherein the oxidized portions extended into the trenches and connected to each other to form an isolation block in the semiconductor substrate.

Description

 Method for manufacturing isolation block of semiconductor device, semiconductor device and method of manufacturing same  

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an isolation block of a semiconductor device and a method of fabricating the same.

The semiconductor integrated circuit (IC) industry has experienced rapid growth over the past few decades. Advances in semiconductor materials and design techniques have made circuits smaller and more complex, especially in the application of high voltage components.

Since the high voltage components need to be separated by a certain distance by the isolation block, the transmission of the electrical signal is not affected by the high voltage. Since the size of the overall component is limited to this specific distance, how to achieve the most efficient space utilization by the configuration of the circuit is a major issue, and on the other hand, the cost of the semiconductor process is relatively increased. In order to reduce the size of components while saving process costs, the semiconductor integrated circuit industry is constantly improving in materials and process design, but current semiconductor integrated devices are not satisfactory in all aspects.

Therefore, the process technology in the semiconductor integrated circuit industry still has a direction to be worked out.

Embodiments of the present invention form a plurality of mutually parallel and staggered trenches and strip structures in a semiconductor substrate by an etching process, and then the foregoing strip structures are oxidized to form a plurality of interconnected by a thermal oxidation process. The oxidized portion of the trench is filled, thereby forming an isolation block having a uniform stress distribution in the semiconductor substrate, thereby avoiding the problem of warpage of the wafer due to uneven stress distribution.

In addition, embodiments of the present invention efficiently form a wide range of isolation blocks within the semiconductor substrate by etching and thermal oxidation processes, making the circuit configuration of the high voltage components more flexible and reducing the process cost of the semiconductor device.

According to some embodiments, a method of fabricating an isolation block of a semiconductor device is provided. A method of fabricating an isolation block of a semiconductor device includes providing a semiconductor substrate, performing an etching process, forming a plurality of mutually parallel trenches in the semiconductor substrate, wherein the trenches have a plurality of strip structures therebetween, the strip structures And the trenches occupy a first region in the semiconductor substrate, and the strip structures are staggered with the trenches. The method for fabricating the isolation block of the semiconductor device also includes performing a thermal oxidation process such that the strip structures are oxidized to form a plurality of oxidized portions, wherein the oxidized portions extend into the trenches and are interconnected to be in the semiconductor substrate Form an isolation block.

According to some embodiments, a method of fabricating a semiconductor device having a high voltage isolation block is provided. A method of fabricating such a semiconductor device includes providing a semiconductor substrate and forming a high voltage isolation block within the semiconductor substrate. The method of fabricating the semiconductor device also includes forming a first metal block and a fourth metal block on the semiconductor substrate, wherein the first metal block is a conductive pad of the first high voltage component, and the fourth metal block is a second high voltage Conductive pad for components. The method of fabricating the semiconductor device further includes forming a second metal block and a third metal block on the high voltage isolation block, wherein the first, second, third and fourth metal blocks are formed of the same metal layer. The method of fabricating the semiconductor device further includes forming an interconnect structure on the first, second, third, and fourth metal blocks, wherein the first metal block and the second metal block are electrically connected by an interconnect structure, and The third metal block and the fourth metal block are electrically connected by an interconnect structure.

In some embodiments, the method for forming the high voltage isolation block includes performing an etching process to form a plurality of mutually parallel trenches in the semiconductor substrate, wherein the trenches have a plurality of strip structures between the trenches. The structure and the trenches occupy a first region in the semiconductor substrate, and the strip structures are staggered with the trenches. The method for forming the high-voltage isolation block further includes performing a thermal oxidation process, such that the strip structures are oxidized to form a plurality of oxide portions, wherein the oxide portions extend into the trenches and are interconnected to be in the semiconductor substrate Form a high voltage isolation block.

According to some embodiments, a semiconductor device having a high voltage isolation block is provided. The semiconductor device includes a semiconductor substrate having a high voltage isolation block. The semiconductor device also includes a first metal block and a fourth metal block disposed on the semiconductor substrate, wherein the first metal block is a conductive pad of the first high voltage component, and the fourth metal block is a second high voltage component Conductive pad. The semiconductor device further includes a second metal block and a third metal block disposed on the high voltage isolation block, wherein the first, second, third and fourth metal blocks belong to the same metal layer. The semiconductor device further includes an interconnect structure disposed on the first, second, third and fourth metal blocks, wherein the first metal block and the second metal block are electrically connected by the interconnect structure, and the third The metal block and the fourth metal block are electrically connected by an interconnect structure.

In order to make the features and advantages of the present invention more comprehensible, some embodiments are described below, and are described in detail below with reference to the accompanying drawings.

100, 300‧‧‧ semiconductor devices

101‧‧‧Semiconductor substrate

103‧‧‧ mask pattern

105‧‧‧ openings

107‧‧‧ trench

108‧‧‧ Strip structure

109‧‧‧Shielding layer

110‧‧‧Oxidation Department

111‧‧‧Isolated block

113, 313‧‧ ‧ gap

115, 315‧‧‧ oxide layer

117a, 317a‧‧‧ first guide hole

117b, 317b‧‧‧ second guide hole

119a, 319a‧‧‧ first metal block

119b, 319b‧‧‧ second metal block

119c, 319c‧‧‧ third metal block

119d, 319d‧‧‧ fourth metal block

150‧‧‧First District

200a‧‧‧First high voltage component

200b‧‧‧second high voltage component

321, 327‧‧‧ metal layer

323‧‧‧guide hole

329‧‧‧Interlayer dielectric layer

330‧‧‧Inline structure

D1‧‧‧first distance

D2‧‧‧Second distance

D3‧‧‧ third distance

D4‧‧‧fourth distance

D5‧‧‧ fifth distance

D6‧‧‧ sixth distance

D7‧‧‧ seventh distance

The views of the present invention can be further understood by the following detailed description in conjunction with the accompanying drawings. It is worth noting that some features may not be drawn to scale according to industry standard practice. In fact, the size of these components may be increased or decreased for clarity of discussion.

1A-1E are schematic cross-sectional views showing different stages of forming a semiconductor device in accordance with some embodiments of the present invention; and FIGS. 2A-2E are top views showing different stages of forming a semiconductor device, in accordance with some embodiments of the present invention, 1A-1E is a schematic cross-sectional view along line 2A-2E of FIG. 2A-3E; FIG. 3A-3C is a schematic cross-sectional view showing different stages of forming a semiconductor device according to other embodiments of the present invention; 4A-4C are top views showing different stages of forming a semiconductor device in accordance with further embodiments of the present invention, wherein FIGS. 3A-3C are cross-sectional views along line 3-3' of FIG. 4A-4C, respectively.

The following provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of the components and their configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit the invention. For example, a reference to a first component formed over a second component in the description may include embodiments in which the first and second components are in direct contact, and may also include additional components formed between the first component and the second component. Embodiments that make them in direct contact. Furthermore, embodiments of the invention may reuse reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/

Some variations of the embodiments are described below. In the different figures and illustrated embodiments, like reference numerals have been used to It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

Some embodiments of the present invention provide methods of forming isolation regions of a semiconductor device. 1A-1E is a cross-sectional view showing different stages of forming a semiconductor device 100 and its isolation regions, in accordance with some embodiments of the present invention. 2A-2E is a top view showing different stages of forming the semiconductor device 100 in accordance with some embodiments of the present invention, wherein the 1A-1E diagrams are schematic cross-sectional views along the 2A-2E plot 1-1', respectively.

According to some embodiments, as shown in FIG. 1A, a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 can be made of germanium or other semiconductor material, or the semiconductor substrate 101 can comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 can be made of a compound semiconductor such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 comprises a silicon-on-insulator (SOI) substrate.

Referring to FIGS. 1A and 2A, a mask pattern 103 is formed on the semiconductor substrate 101. The mask pattern 103 has a plurality of openings 105 that are parallel to each other, and the opening 105 exposes a portion of the semiconductor substrate 101. The distance between one of the openings 105 and the adjacent other opening 105 is defined as a first distance d1, and one of the openings 105 has a width, the aforementioned width being defined as a second distance d2.

In the present embodiment, the first distance d1 is equal to the second distance d2, which is the most efficient process configuration, but is not limited thereto. In other embodiments, the first distance d1 may be greater than or less than the second distance d2, and the relevant configuration and its effects will be described later.

In addition, the mask pattern 103 can be by thermal oxidation, chemical vapor deposition (CVD), high-density plasma CVD (HDPCVD), atomic layer deposition (atomic layer deposition, ALD), spin coating, sputtering, metal organic chemical vapor deposition (MOCVD) or a combination of the foregoing to form a mask material layer (not shown) by A patterning process, such as a lithography and etching process, patterns the layer of masking material to form a mask pattern 103. In some embodiments, the hard mask pattern 103 may be one or more layers, and may be, for example, tantalum nitride (SiN), cerium oxide (SiO2), cerium oxynitride (SiON), tetraethoxysilane, TEOS) or a combination of the foregoing.

According to some embodiments, as shown in FIGS. 1B and 2B, the semiconductor substrate 101 is etched using the mask pattern 103 as a mask, and the mask pattern 103 is transferred into the semiconductor substrate 101 to be formed in the semiconductor substrate 101. A plurality of mutually parallel grooves 107 and strips 108 are formed, and the strip structures 108 are staggered with the grooves 107.

In some embodiments, the depth of the trenches 107 is in the range of from about 5 microns to about 100 microns, particularly in the range of from about 30 microns to about 100 microns, and the depth of the trenches 107 may need to be adjusted depending on the process. In other embodiments, the trench 107 can be a trench that digs through the semiconductor substrate 101.

Specifically, a plurality of mutually parallel trenches 107 are formed in the semiconductor substrate by an etching process, and a plurality of strip structures 108 between the trenches 107, the trenches 107 and the strip structures 108 on the semiconductor substrate 101. The first area 150 is occupied, and the position of the first area 150 is the position where the isolation block will be formed in the subsequent process.

Similar to FIG. 1A, the distance between one of the trenches 107 and the adjacent other trench 107 is approximately equal to the first distance d1, and the width of one of the trenches 107 is approximately equal to the second distance d2. In the present embodiment, the first distance d1 is equal to the second distance d2. Moreover, in some embodiments, the etching process described above may include dry etching, wet etching, or a combination of the foregoing.

According to some embodiments, as shown in FIGS. 1C and 2C, a shadowing layer 109 having an opening is formed on the semiconductor substrate 101. It is noted that in the upper view of FIG. 2C, the opening of the masking layer 109 exposes the first region 150 and a portion of the semiconductor substrate 101 that is located around the first region 150. Specifically, the sidewalls of the masking layer 109 are not aligned with the trenches 107 in the semiconductor substrate 101 at the outermost sidewalls of the first region 150, and between the sidewalls of the masking layer 109 and the sidewalls of the trenches 107 in the semiconductor substrate 101. Has a third distance d3. In some embodiments, the masking layer 109 is used to define the exact location of the isolation block. In the subsequent process, the area of the semiconductor substrate 101 that is not covered by the masking layer 109 is the location of the isolation block to be formed later.

In some embodiments, the shielding layer 109 may comprise hafnium oxide, tantalum nitride or hafnium oxynitride, and the shielding layer 109 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), high density. Plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), spin coating or a combination of the foregoing. In addition, openings of the masking layer 109 are formed by a patterning process, such as lithography and etching processes.

According to some embodiments, as shown in FIGS. 1D and 2D, a thermal oxidation process is performed such that the strip structures 108 between the trenches 107 are oxidized to form a plurality of oxidized portions 110. It is to be noted that the 1D drawing only shows one of the oxidized portions 110, but the actual number of the oxidized portions 110 is not limited thereto. These oxide portions 110 extend into the trenches 107 and are connected to each other to form a complete isolation block 111 in the semiconductor substrate 101. In the present embodiment, in addition to oxidizing the strip structure 108 between the trenches 107, the thermal oxidation process also applies to the sidewall portions of the semiconductor substrate 101 that are common to the trenches 107, that is, at the edges of the first regions 150. A portion of the semiconductor substrate 101, and a bottom portion of the trench 107 are oxidized.

In some embodiments, the temperature of the thermal oxidation process described above is in the range of from about _800 °C to about 1200 °C. Specifically, in the above thermal oxidation process, the consumption of one unit of germanium can generate about two units or more of cerium oxide. Therefore, the volume of one of the oxidized portions 110 formed by the oxidation of the strip structure 108 is the strip structure 108. One of them is more than twice the volume. As shown in FIGS. 1D and 2D, the dotted line portion is the position where the strip structure 108 and the groove 107 between the original grooves 107 are located. In general, the area and volume of the isolation block 111 formed by performing the thermal oxidation process is larger than the area and volume of the first region 150, and the top surface of the isolation block 111 is higher than the top surface of the semiconductor substrate 101.

In some embodiments, since some of the oxidized portions 110 are not completely intimately coupled to the adjacent oxidized portions 110, voids 113 may be created within the isolated blocks 111, as shown in Figures 1D and 2D, in some embodiments, The void 113 does not extend to the top surface of the semiconductor substrate 101, and therefore the isolation effect and the degree of withstanding high voltage of the isolation block 111 are not lowered by the generation of the void 113. Further, in other embodiments, the adjacent oxidized portions 110 are completely in close contact with each other, and no voids 113 are produced.

In addition, referring to FIGS. 1C and 1D, before the thermal oxidation process is performed, if the second distance d2 is smaller than the first distance d1, that is, the opening 105 and the trench 107 have a large aspect ratio, the etching forms the opening 105 and the trench. The time required for the grooves 107 is longer, but since the distance between the adjacent two structures 108 is shorter, the time required to form the isolation blocks 111 by the thermal oxidation process is less. On the other hand, if the second distance d2 is greater than the first distance d1, that is, the distance between the adjacent two structures 108 is large, the time required for forming the isolation block 111 by the thermal oxidation process is long, but due to the opening 105 and trench 107 have a smaller aspect ratio, and the time required to etch the opening 105 and trench 107 is shorter. Since in one embodiment the thermal oxidation process consumes one unit of tantalum to produce about two units of tantalum oxide, setting the first distance d1 and the second width d2 to be equal is the most efficient process configuration.

According to some embodiments, as shown in Figs. 1E and 2E, after the mask layer 109 is removed, an oxide layer 115 is formed on the semiconductor substrate 101 and the isolation block 111. In some embodiments, the masking layer 109 can be removed by an etching process. In addition, the oxide layer 115 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), spin coating, or a combination thereof. And formed. In some embodiments, after the oxide layer 115 is formed, a planarization process is performed on the oxide layer 115 such that the oxide layer 115 has a flat top surface. The planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable processes, or a combination of the foregoing.

Next, a first via hole 117a and a second via hole 117b are formed in the oxide layer 115 on the semiconductor substrate 101. The first via hole 117a is disposed on the first high voltage component 200a in the semiconductor substrate 101, and the second via hole 117b is disposed on the second high voltage component 200b in the semiconductor substrate 101. Then, a first metal block 119a, a second metal block 119b, a third metal block 119c, and a fourth metal block 119d are formed on the oxide layer 115.

In some embodiments, the first metal block 119a, the second metal block 119b, the third metal block 119c, and the fourth metal block 119d are simultaneously patterned by the same metal layer (not shown). Formed, and the first metal block 119a, the second metal block 119b, the third metal block 119c, and the fourth metal block 119d are four conductive pads belonging to the same layer.

It is to be noted that the first metal block 119a is disposed on the first high voltage component 200a, electrically connected to the first high voltage component 200a through the first via hole 117a, and the fourth metal block 119d is disposed on the other side. The second high voltage element 200b is electrically connected to the second high voltage element 200b through the second conductive hole 117b. In addition, the second metal block 119b and the third metal block 119c are disposed above the isolation block 111.

Referring to FIGS. 1E and 2E, the distance between the first metal block 119a and the second metal block 119b is defined as a fourth distance d4, and the distance between the second metal block 119b and the third metal block 119c is defined. For the fifth distance d5, in some embodiments, the fourth distance d4 and the fifth distance d5 are in the range of 30 micrometers or more, and the larger the fourth distance d4 and the fifth distance d5, the higher the isolation block 111 can withstand The voltage, therefore, the fourth distance d4 and the fifth distance d5 can be adjusted according to the actual application.

3A-3C are cross-sectional schematic views showing different stages of forming a semiconductor device 300 and its isolation regions, in accordance with further embodiments of the present invention. 4A-4C are top views showing different stages of forming a semiconductor device 300 in accordance with further embodiments of the present invention, wherein the 3A-3C diagram is a section along line 3-3' of the 4A-4C line, respectively. schematic diagram.

According to other embodiments, as shown in FIGS. 3A and 4A, similar to FIG. 1D, after the thermal oxidation process is performed, a void 313 is formed in the isolation block 111, and the void 313 extends to the top surface of the isolation block 111. In still other embodiments, the bottom of one of the voids 313 extends downwardly and exposes a portion of the semiconductor substrate 101, that is, the isolation block 111 has a void 313 with oxidized portions 110 on both sides thereof. Not joined together at all.

In order to form a complete isolation block 111, see FIGS. 3B and 3C, after the mask layer 109 is removed, an oxide layer 315 is formed on the semiconductor substrate 101 and the isolation block 111 to seal the gap 315 and is implemented on the oxide layer 315. The planarization process causes the oxide layer 315 to have a flat top surface. It is worth noting that the aforementioned planarization process does not expose the voids 315. The oxide layer 315 may be formed in the same or similar manner to the oxide layer 115, and will not be described herein.

Next, as shown in FIGS. 3C and 4C, a first via hole 317a and a second via hole 317b are formed in the oxide layer 315 on the semiconductor substrate 101. The first via hole 317a is disposed on the first high voltage component 200a in the semiconductor substrate 101, and the second via hole 317b is disposed on the second high voltage component 200b in the semiconductor substrate 101. Then, a first metal block 319a, a second metal block 319b, a third metal block 319c, and a fourth metal block 319d are formed on the oxide layer 315.

In some embodiments, the first metal block 319a, the second metal block 319b, the third metal block 319c, and the fourth metal block 319d are formed by performing a patterning process on the same metal layer (not shown). And the first metal block 319a, the second metal block 319b, the third metal block 319c, and the fourth metal block 319d are four conductive pads belonging to the same layer.

It is to be noted that the first metal block 319a is disposed on the first high voltage component 200a, and is electrically connected to the first high voltage component 200a through the first guiding hole 317a. On the other hand, the fourth metal block 319d is disposed on the first metal block 319d. The second high voltage element 200b is electrically connected to the second high voltage element 200b through the second conductive hole 317b. In addition, the second metal block 319b and the third metal block 319c are disposed above the isolation block 111.

Referring again to FIGS. 3C and 4C, the distance between the first metal block 319a and the second metal block 319b is defined as a sixth distance d6, and between the second metal block 319b and the third metal block 319c. The distance is defined as a seventh distance d7. In some embodiments, the sixth distance d6 and the seventh distance d7 are in the range of 30 micrometers or more, and the larger the sixth distance d6 and the seventh distance d7, the more the isolation block 111 can withstand. The high voltage, therefore, the sixth distance d6 and the seventh distance d7 can be adjusted according to the actual application.

Then, as shown in FIGS. 3C and 4C, an interconnect structure 330 is formed on the first metal block 319a, the second metal block 319b, the third metal block 319c, and the fourth metal block 319d. The interconnect structure 330 includes a plurality of vias 321 and 325, a plurality of metal layers 323 and 327, and a plurality of interlayer dielectric layers 329.

In some embodiments, vias 321 and 325 and metal layers 323 and 327 comprise a metal or other suitable electrically conductive material, such as: tungsten, copper, nickel, aluminum, WSix, polysilicon, or a combination thereof. On the other hand, the interlayer dielectric layer 329 contains a dielectric material such as hafnium oxide, tantalum nitride, or hafnium oxynitride. The interconnect structure 330 can be formed by a general deposition and patterning process, and will not be described herein.

In the foregoing, in some embodiments, the first metal block 319a and the second metal block 319b are electrically connected by the interconnect structure 330, and the third metal block 319c and the fourth metal block 319d are connected by the interconnect. The line structure 330 is electrically connected. In other embodiments, the second metal block 319b and the third metal block 319c can also be electrically connected by the interconnect structure 330.

In some embodiments, the external electronic signal is transmitted to the second metal block 319b through the interconnect structure 330, and then transferred from the second metal block 319b to the first metal block 319a via the interconnect structure 330. The first high voltage component 200a; similarly, the external electronic signal is transmitted to the third metal block 319c through the interconnect structure 330, and then transferred from the third metal block 319c to the fourth metal through the interconnect structure 330. Block 319d and second high voltage component 200b. Since the semiconductor substrate 101 and any two adjacent metal blocks on the isolation block 111, for example, the distance between the second metal block 319b and the third metal block 319c is sufficiently large, that is, between adjacent two metal blocks The insulating block is separated by a sufficiently thick layer. Therefore, the embodiment of the present invention can smoothly transfer the electronic signal from one integrated circuit (IC) to another integrated circuit under a high voltage state.

Embodiments of the present invention form a plurality of mutually parallel and staggered trenches and strip structures in a semiconductor substrate by an etching process, and then the foregoing strip structures are oxidized to form a plurality of interconnected by a thermal oxidation process. The oxidized portion of the trench is filled, whereby an isolation block having a uniform stress distribution can be formed in the semiconductor substrate, thereby avoiding the problem of warpage of the wafer due to uneven stress distribution.

In addition, embodiments of the present invention efficiently form a wide range of isolation blocks within the semiconductor substrate by etching and thermal oxidation processes, making the circuit configuration of the high voltage components more flexible, such as passing between two high voltage components. The isolator of the electronic signal is changed from the vertical configuration to the horizontal configuration, and is disposed in a centralized high-voltage isolation block. Furthermore, embodiments of the present invention can effectively reduce the process cost of a semiconductor device.

The embodiments are summarized above in order to provide a better understanding of the present invention in the technical field of the invention. It will be appreciated by those of ordinary skill in the art that the present invention can be practiced or modified in other embodiments and/or structures in accordance with the embodiments of the present invention. It is also to be understood by those of ordinary skill in the art that the present invention is not to be construed as Various changes, substitutions and substitutions.

Claims (20)

 A method of fabricating an isolation block of a semiconductor device, comprising: providing a semiconductor substrate; performing an etching process, forming a plurality of mutually parallel trenches in the semiconductor substrate, wherein the plurality of strip structures are between the trenches The strip structures and the trenches occupy a first region in the semiconductor substrate, and the strip structures are staggered with the trenches; and a thermal oxidation process is performed to oxidize the strip structures A plurality of oxidized portions are formed, wherein the oxidized portions extend into the trenches and are connected to each other to form an isolation block in the semiconductor substrate.    The method of manufacturing an isolation block of a semiconductor device according to claim 1, wherein an area of the isolation block is larger than an area of the first area.    The method of fabricating an isolation block for a semiconductor device according to claim 1, wherein a volume of one of the oxidation portions is more than twice the volume of one of the strip structures.    The method of fabricating an isolation block for a semiconductor device according to claim 1, wherein the thermal oxidation process is performed to oxidize sidewalls of the semiconductor substrate and bottoms of the trenches.    The method of fabricating an isolation block for a semiconductor device according to claim 1, wherein a top surface of the isolation block is higher than a top surface of the semiconductor substrate.    The method of fabricating an isolation block for a semiconductor device according to claim 1, wherein a width of one of the trenches is equal to a width of one of the strip structures.    The method for manufacturing an isolation block of a semiconductor device according to claim 1, further comprising: forming a shielding layer on the semiconductor substrate before the performing the thermal oxidation process, and the shielding layer exposing the first Area.    The method of manufacturing an isolation block of a semiconductor device according to claim 7, wherein the exposed area of the shielding layer is larger than the area of the first area.    The method of fabricating an isolation block for a semiconductor device according to claim 1, wherein the isolation block has a void therein.    The method for fabricating an isolation block for a semiconductor device according to claim 9, further comprising: forming an oxide layer on the isolation block, wherein the gap extends to a top surface of the isolation block, and the oxidizing A layer seals the void; and a planarization process is performed on the oxide layer, the planarization process not exposing the void.    A method of fabricating a semiconductor device having a high voltage isolation block, comprising: providing a semiconductor substrate; forming a high voltage isolation block in the semiconductor substrate; forming a first metal block and a fourth metal region on the semiconductor substrate a block, wherein the first metal block is a conductive pad of a first high voltage component, and the fourth metal block is a conductive pad of a second high voltage component; forming a second metal block on the high voltage isolation block And a third metal block, wherein the first, second, third and fourth metal blocks are formed by the same metal layer; and an interconnect structure is formed on the first, second, third and fourth metal blocks, The first metal block and the second metal block are electrically connected by the interconnect structure, and the third metal block and the fourth metal block are electrically connected by the interconnect structure.    The method for fabricating a semiconductor device having a high voltage isolation block according to claim 11, wherein the step of forming the high voltage isolation block further comprises: performing an etching process to form a plurality of mutually parallel in the semiconductor substrate a trench, wherein the trenches have a plurality of strip structures therebetween, the strip structures and the trenches occupy a first region in the semiconductor substrate, and the strip structures are interlaced with the trenches Arranging; and performing a thermal oxidation process such that the strip structures are oxidized to form a plurality of oxidized portions, wherein the oxidized portions extend into the trenches and are interconnected to form a high voltage isolation block in the semiconductor substrate .    The method of fabricating a semiconductor device having a high voltage isolation block according to claim 12, wherein the area of the high voltage isolation block is larger than the area of the first area.    The method of fabricating a semiconductor device having a high voltage isolation block according to claim 12, wherein a width of one of the trenches is equal to a width of one of the strip structures.    The method of fabricating a semiconductor device having a high voltage isolation block according to claim 12, wherein a volume of one of the oxidation portions is more than twice the volume of one of the strip structures.    The method of fabricating a semiconductor device having a high voltage isolation block according to claim 11, wherein the high voltage isolation block has a void therein.    A method of fabricating a semiconductor device having a high voltage isolation block according to claim 11, wherein the high voltage isolation block does not have any conductive portion.    A semiconductor device having a high voltage isolation block, comprising: a semiconductor substrate having a high voltage isolation block; a first metal block and a fourth metal block disposed on the semiconductor substrate, wherein the first metal region The block is a conductive pad of a first high voltage component, and the fourth metal block is a conductive pad of a second high voltage component; a second metal block and a third metal block are disposed on the high voltage isolation block Wherein the first, second, third and fourth metal blocks belong to the same metal layer; and an interconnect structure is disposed on the first, second, third and fourth metal blocks, wherein the first metal block The second metal block is electrically connected to the second metal block by the interconnect structure, and the third metal block and the fourth metal block are electrically connected by the interconnect structure.    A semiconductor device having a high voltage isolation region as described in claim 18, wherein the high voltage isolation block has a void therein.    The semiconductor device having a high voltage isolation region according to claim 18, wherein the second metal block and the third metal block are electrically connected by the interconnect structure.