JP2007311818A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of improving surface planarity of the material members buried in a plurality of trenches without bringing increase of manufacturing process time. <P>SOLUTION: Dummy patterns can be arranged up to the proximity of the boundary between a device forming area DA and a dummy area FA by arranging first dummy patterns DP<SB>1</SB>of a relatively large area and a second dummy patterns DP<SB>2</SB>of a relatively small area in the dummy area FA. Thereby, it is possible to improve surface planarity of the silicon oxide film buried in isolation trenches in the whole region of the dummy area FA. Furthermore, by occupying relatively wide regions of the dummy area FA with the first dummy patterns DP<SB>1</SB>, increase in the data volume for the mask can be restrained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device including a planarization process using a CMP (chemical mechanical polishing) method in its manufacturing process.

  One isolation that electrically isolates adjacent semiconductor elements from each other is trench isolation formed by providing a trench in a semiconductor substrate serving as an element isolation region and embedding an insulating film therein. .

  This trench isolation is formed by the following method, for example. First, a trench having a depth of, for example, about 0.4 μm is formed in the element isolation region of the semiconductor substrate by dry etching, and then the semiconductor substrate is subjected to a thermal oxidation process, so that, for example, A first insulating film having a thickness of about 20 nm is formed. Thereafter, a second insulating film is deposited on the semiconductor substrate to fill the inside of the groove, and then the surface of the second insulating film is polished by, for example, a CMP method to remove the second insulating film outside the groove. Then, the trench isolation is formed by leaving the second insulating film only inside the trench.

  By the way, when the width of the element isolation region becomes relatively large, the polishing of the second insulating film is locally accelerated in the CMP process, so that a so-called dishing phenomenon in which the central portion of the groove is depressed tends to occur. However, as a method for suppressing the dishing phenomenon and improving the flatness of the surface of the second insulating film in the element isolation region, several methods have been proposed, and one of them is a method of providing a dummy pattern.

  For example, in Japanese Patent Laid-Open No. 10-92921 (Patent Document 1), each dummy structure is formed in a portion without an active device so that the occupation density of a portion without an active device and a portion with an active device are equal. A method is disclosed that is disposed and thereby equalizes the polishing rate across the surface of the semiconductor substrate.

  The inventor has also studied a method for regularly arranging dummy patterns in the element isolation region. The following is a technique studied by the present inventor, and its outline is as follows.

FIG. 28 shows a first dummy pattern placement method investigated by the present inventors. A plurality of dummy patterns DPA ₁ are regularly formed in a dummy area (area outside the broken line frame in the figure) FA where a semiconductor element other than DA is formed in an element forming area where the semiconductor element is formed (area inside the broken line frame in the figure) DA. Is arranged. The plurality of dummy patterns DPA ₁ have the same shape and the same dimensions, and are laid out in the dummy area FA at the same interval.

The element formation area DA and the dummy area FA other than the active area AC are element isolation areas IS, and trench isolation is usually formed in the entire isolation area IS. For this reason, in particular, in the dummy area FA far from the active area AC, dishing in the CMP process is likely to occur, and it is difficult to obtain the flatness of the surface of the buried insulating film. However, by disposing a plurality of dummy patterns DP _1, it becomes possible to prevent dishing in the dummy region FA, it is possible to improve the flatness of the surface of the buried insulating film in the dummy region FA.

FIG. 29 shows a second dummy pattern placement method investigated by the present inventors. As in FIG. 28, a plurality of dummy patterns DPA ₂ are regularly arranged in a dummy area FA where semiconductor elements other than the element formation area DA where the semiconductor elements are formed are not formed, and dishing in the dummy area FA is performed. It is possible to prevent. The size of the dummy pattern DPA ₂ is smaller than the size of the dummy pattern DPA ₁ and reaches the dummy region FA near the boundary BL (indicated by a frame line in the drawing) between the element formation region DA and the dummy region FA. A dummy pattern DPA ₂ can be arranged.
JP-A-10-92921

  However, as a result of examination by the present inventor, when a dummy structure is disposed in a portion without the active device, some of the dummy structures are complicated in shape, and in particular, the dummy structure is partitioned. There was a problem that the insulating film was not completely embedded in the inside of the film. Moreover, since the process of removing the dummy structure which is too small to form is required, it is considered that the time required for the manufacturing process increases.

  Furthermore, the present inventor has found that the first dummy pattern placement method and the second dummy pattern placement method have the following problems.

First, in the first dummy pattern placement method, since the size of the dummy pattern DPA ₁ is relatively large, the dummy pattern DPA ₁ is placed in the dummy area FA close to the boundary BL between the element formation area DA and the dummy area FA. It has become clear that dishing occurs when a region that cannot be produced occurs and this region becomes relatively wide.

In the second dummy pattern placement method, since the size of the dummy pattern DPA ₂ is relatively small, the dummy pattern DPA ₂ can be placed near the boundary BL between the element formation region DA and the dummy region FA. Thereby, since the dummy pattern DPA ₂ can be arranged also in the region where the dummy pattern DPA ₁ could not be arranged, in the second dummy pattern arranging method, as compared with the first dummy pattern arranging method, The flatness of the surface of the buried insulating film can be improved up to the dummy area FA close to the boundary BL.

However, the use of the second dummy pattern arrangement method, the greater the number of dummy patterns DPA ₂ arranged in the dummy region FA, the coordinate data amount for creating the mask is increased considerably. This increases the calculation processing time in the computer and further increases the time for drawing the pattern on the mask substrate, which causes a problem that the throughput of creating the mask is significantly reduced. In particular, if the second dummy pattern placement method is employed in an ASIC (application specific integrated circuit), the time required to create a mask increases, which hinders the development of an ASIC in a short period of time. There is a problem.

  The objective of this invention is providing the technique which can improve the flatness of the member surface embedded in the several recessed part.

  It is another object of the present invention to provide a technique capable of improving the flatness of the surface of a member embedded in a plurality of recesses without increasing the time required for the manufacturing process of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor device according to the present invention includes an element formation region in which circuit elements are defined by boundaries, and a dummy region in which circuit elements adjacent to the boundaries are not formed, and the dummy region has at least two dummy pattern groups. In each dummy pattern group, a plurality of dummy patterns having the same shape and the same dimensions as each other in a plane are arranged in a matrix and are separated from each other in the row direction of the plurality of dummy patterns and / or Alternatively, the dimension in the column direction is different between each dummy pattern group.
(2) In the method of manufacturing a semiconductor device according to the present invention, an element formation region where a circuit element is formed and a dummy region where a circuit element is not formed are defined by a boundary, and at least two dummy pattern groups are formed in the dummy region. A method for manufacturing a semiconductor device, comprising:
Formed on the main surface of the semiconductor substrate are a first separation groove for defining an active region of an element formation region and a second separation groove for dividing a plurality of dummy patterns forming each dummy pattern group of the dummy region in a matrix. A step of depositing an insulating film so as to cover the element formation region and the dummy region so as to embed the first separation groove and the second separation groove; and polishing the surface of the insulating film to thereby form the first separation groove and the second separation A step of removing an insulating film outside the trench, and each dummy pattern group is formed with a plurality of dummy patterns having the same shape and the same size as each other, The dimensions in the row direction and / or the column direction are different between the dummy pattern groups.

  According to the above-described means, a plurality of dummy patterns can be arranged near the boundary between the element formation region and the dummy region. Thereby, the flatness of the surface of the insulating film embedded in the isolation trench can be improved over the entire dummy region.

  Furthermore, a relatively wide area of the dummy area can be occupied by a plurality of dummy patterns having a relatively large area, and the remaining relatively narrow area can be occupied by a plurality of dummy patterns having a relatively small area. It is possible to suppress an increase in the number of dummy patterns arranged. Thereby, it is possible to suppress an increase in the amount of coordinate data when creating a mask, and it is possible to suppress an increase in calculation processing time in the computer, pattern drawing time on the mask substrate, and the like.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to improve the flatness of the surface of a member embedded in a plurality of recesses by arranging at least two dummy pattern groups.

  Furthermore, by occupying a relatively large area of the dummy area with a dummy pattern having a relatively large area, it is possible to suppress an increase in the time required for mask creation by suppressing an increase in the amount of coordinate data when creating a mask. it can. As a result, it is possible to improve the flatness of the surface of the member embedded in the plurality of recesses without increasing the time required for the manufacturing process of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the shape described in the present embodiment, the shape expression such as “square” and “rectangular” is a design thinking shape, a shape on the mask pattern data, a shape on the mask, and a pattern on the patterned integrated circuit device. It includes an actual pattern shape, and substantially includes a corner portion or the like that is slightly deformed from a geometric shape due to processing problems such as lithography.

(Embodiment 1)
An example of the arrangement of dummy patterns according to the first embodiment will be described with reference to FIGS. 1 is a plan view of an essential part showing an example of a logic integrated circuit device, FIG. 2 is a cross-sectional view taken along line AA of FIG. 1, and FIG. 3 is a plan view for explaining the pitch and dimensions of dummy patterns. FIG. 4 is a plan view for explaining an example of the arrangement of dummy patterns, and FIG. 5 is a process diagram showing an example of a method for creating dummy patterns.

  As shown in FIG. 1, the inside of the boundary BL indicated by a broken line is an element forming area DA where a semiconductor element is formed, and the outside of the boundary BL is a dummy area FA where no semiconductor element is formed.

  The boundary BL between the element formation area DA and the dummy area FA is determined from the layout of the conductor film extending on the element isolation area IS and the layout of the active area AC. If a dummy pattern is formed below the conductor film, a problem such as an increase in capacitive load occurs. Therefore, it is necessary to determine the boundary BL so that the conductor film and the dummy pattern do not overlap. In the first embodiment, on the basis of the layout of the conductive film extending on the element isolation region IS and the layout of the active region AC, the margin dimension necessary for reducing the capacitive load, the alignment accuracy in the lithography technique, and the like are added. Considering the above, the boundary BL is determined.

As shown in FIGS. 1 and 2, complementary metal oxide semiconductor field effect transistors (CMOSFETs) C ₁ , C ₂ , and C ₃ are formed in the element formation region DA. An active region AC is defined by an element isolation region IS in which a silicon oxide film 3 is embedded in an isolation groove 2 a formed in the main surface of the semiconductor substrate 1.

  A p-type well 4 and an n-type well 5 are formed on the main surface of the semiconductor substrate 1. An n-channel MISFET (metal insulator semiconductor FET) is formed in the p-type well 4, and a p-channel MISFET is formed in the n-type well 5. Is done. A gate electrode 7 is formed on the main surface of the semiconductor substrate 1 via a gate insulating film 6 of an n-channel MISFET and a p-channel MISFET. The gate insulating film 6 can be a silicon oxide film formed by, for example, a thermal oxidation method, and the gate electrode 7 can be a polycrystalline silicon film formed by, for example, a CVD (chemical vapor deposition) method. A silicide layer for reducing electric resistance may be formed on the surface of the polycrystalline silicon film. The gate electrode 7 is formed so as to extend from the active region AC onto the element isolation region IS.

  Sidewall spacers 8 are formed on the side walls of the gate electrodes 7 of the n-channel MISFET and the p-channel MISFET. The sidewall spacer 8 can be a silicon oxide film or a silicon nitride film, for example. A source / drain extension region 9a is formed in the p-type well 4 on both sides of the gate electrode 7 of the n-channel MISFET so as to sandwich the channel region. Further, a source / drain diffusion region 9b is formed outside the source / drain extension region 9a. Is formed. Similarly, although not shown, a source / drain extension region is formed in the n-type well 5 on both sides of the gate electrode 7 of the p-channel MISFET with the channel region interposed therebetween, and further, a source, A drain diffusion region is formed. The sources and drains of the n-channel MISFET and the p-channel MISFET have a so-called LDD (lightly doped drain) structure.

CMOSFETs C ₁ , C ₂ , and C ₃ formed in the element formation region DA are covered with an interlayer insulating film 10, and the interlayer insulating film 10 includes a p-type well 4 and an n-type well 5 in the active region AC, and a gate. A contact hole 11 reaching the electrode 7 is formed. The interlayer insulating film 10 can be a silicon oxide film, for example, and its surface is preferably planarized by an etch back method or a CMP method. Although wiring is formed on the interlayer insulating film 10, its illustration is omitted.

The dummy area FA includes a plurality of first dummy patterns DP _{1 having} a relatively large area (indicated by relatively thin hatching in FIG. 1) and a plurality of second dummy patterns DP having a relatively small area. ₂ (semiconductor islands shown by relatively dark hatching in FIG. 1) are regularly arranged. As shown in FIG. 3, the first dummy pattern DP ₁ is a side dimension of the row direction, a La in the column direction both formed of a semiconductor islands square corresponding to the active region AC, the relative of the dummy area Occupy a large area. The second dummy pattern DP ₂ is a side dimension of the row direction, a Lb in the column direction both formed of a semiconductor islands square corresponding to the active region AC, are disposed relatively narrow region of the dummy region Yes.

Here, the dimension La of the first dummy pattern DP ₁ a side is set larger than the size Lb of the second dummy pattern DP ₂ a side, adjacent to the space dimension between the first dummy pattern DP ₁ adjacent the space dimension between second dummy pattern DP ₂ are set to the same space size Sa, the first dummy pattern DP ₁ and the second dummy pattern DP ₂ are separated at the same intervals from each other.

As shown in FIG. 4, the pattern size obtained by adding the space dimension Sa to the dimension La of one side of the first dummy pattern DP ₁ is the dimension Lb of one side of the second dummy pattern DP _{2 in both} the row direction and the column direction. It is an integral multiple of the pattern size including the space dimension Sa, and satisfies the relationship La + Sa = N × (Lb + Sa) (N ≧ 1). Accordingly, since the dummy region FA first different sizes dummy pattern DP ₁ and the second dummy pattern DP ₂ can be regularly multiple arrangement also coordinate data for creating mask is increased, computer It is possible to suppress an increase in calculation processing time in

The first dummy patterns DP ₁ dimension La, dimensions Lb and space size Sa of the second dummy pattern DP ₂ is set to greater than or equal to the minimum allowable dimension (minimum dimension allowed on the pattern design). If these values are smaller than the minimum allowable dimension, when forming the element isolation region IS, the resist pattern is peeled off, the processing of the isolation groove in the dry etching process is poor, or the silicon oxide film is not embedded in the isolation groove. This is because the problem arises. For example, the dimension La of one side of the first dummy pattern DP ₁ is set to 2.0 μm, the dimension Lb of one side of the second dummy pattern DP ₂ is set to 0.8 μm, and the space dimension Sa is set to 0.4 μm.

Next, a dummy pattern arranging method will be described with reference to FIG. First, the arrangement data of the dummy pattern is created by the computer using an automatic program. Next, a dummy pattern is drawn on the mask substrate based on the arrangement data, and the dummy pattern is transferred to the semiconductor substrate through the mask. Here, a description will be given of a first dummy pattern DP ₁ and the second method of creating placement data of the dummy pattern DP ₂ using an automatic Puraguramu.

First, the first dummy pattern DP ₁ and the second dummy pattern DP ₂ arrangement prohibited area Request (element formation region DA) (step 100 in FIG. 5). As described above, based on the layout of the conductive film extending on the element isolation region IS and the layout of the active region AC, taking into account the extra dimensions necessary for reducing the capacitive load, the alignment accuracy in the lithography technology, and the like. Thus, the placement prohibited area is determined. That is, standard dimension data is added to the coordinate data of the conductor film extending on the element isolation region IS and the coordinate data of the active region AC, respectively, and the coordinate data of the placement prohibited region is obtained by taking or of all the obtained data. Is required. For example, a region 2 μm away from the active region AC where CMOSFETs C ₁ , C ₂ , and C ₃ are formed is defined as a first disposition prohibiting region, and a region 1 μm away from the gate electrodes of CMOSFETs C ₁ , C ₂ , and C ₃ is disposed as a second region and prohibition region, and the first placement prohibiting region and said the or region of the second arrangement inhibition region first dummy pattern DP ₁ and the second dummy pattern DP ₂ of the arrangement inhibition region.

Next, we laid the first dummy pattern DP ₁ large relative area in most of the dummy region FA (step 101 in FIG. 5). For example, after the mesh is generated at a first pitch on the entire surface of the semiconductor substrate 1, to remove the mesh required for placement prohibiting region of the first dummy pattern DP ₁ and the second dummy pattern DP _2. Or, after the mesh is generated in the first pitch on the entire surface of the semiconductor substrate 1, the mesh of the first dummy pattern DP ₁ and the second placement prohibiting region of the dummy pattern DP ₂ is removed, further removed following mesh minimum allowable dimension To do. Thereafter, placing a first dummy pattern DP ₁ mesh. Note that the first pitch wherein a pattern size obtained by adding the space size Sa to the size La of the first dummy pattern DP ₁ a side (La + Sa).

Next, determine the smaller second placement prohibiting region of the dummy pattern DP ₂ relatively area (step 102 in FIG. 5). The first dummy pattern DP ₁ and the second dummy pattern DP ₂ of the arrangement inhibition region which has been determined by the step 100, by adding a region in which the first dummy pattern DP ₁ was laid in the step 101, the second dummy pattern DP ₂ This is a prohibited area.

Next, we laid a second dummy pattern DP ₂ having a relatively small area in the dummy region FA (step 103 in FIG. 5). For example, after the mesh is generated by a second pitch over the entire surface of the semiconductor substrate 1, to remove the mesh required for placement prohibiting region of the second dummy pattern DP _2. Or, after the mesh is generated in the second pitch over the entire surface of the semiconductor substrate 1, the mesh of the second dummy pattern DP ₂ of the arrangement inhibition region is removed, further removed the following meshes minimum allowable dimension. Thereafter, placing a second dummy pattern DP ₂ to mesh. Note that the second pitch here, a pattern size obtained by adding the space size Sa to the size Lb of the second dummy pattern DP ₂ side (Lb + Sa), further second second pitch of the dummy pattern DP ₂ is The first dummy pattern DP1 is _{1 /} integer (N) of the first pitch, that is, 1/2. From easiness of placement of the second dummy pattern DP _2, preferably the second second pitch of the dummy pattern DP ₂ and an integral fraction of the first first pitch of the dummy pattern DP _1.

In the first embodiment, the element formation regions are arranged a plurality of first dummy patterns DP ₁ to distant dummy region FA from DA, the element formation region a first dummy pattern of a plurality close dummy region FA to DA DP ₂ Needless to say, this is not a limitation. For example in the dummy region FA of the first dummy pattern DP ₁ more placed near the device formation area DA, may be disposed a plurality of second dummy patterns DP ₂ from the element forming region DA far dummy region FA, or dummy disposing a plurality of first dummy patterns DP ₁ over substantially the entire area FA, may be arranged a plurality of second dummy patterns DP ₂ between the first dummy pattern DP ₁ adjacent the second pitch has occurred.

In the first embodiment, CMOSFETs C ₁ , C ₂ , and C ₃ are illustrated as semiconductor elements formed in the element formation region DA. However, other semiconductor elements such as Bi-CMOS transistors may be used.

Thus, according to the first embodiment, it is possible to arrange the first dummy pattern DP ₁ and the second dummy pattern DP ₂ to a boundary BL near the device formation area DA and the dummy region FA, separation grooves The flatness of the surface of the silicon oxide film 3 embedded in 2 and 2a can be improved throughout the dummy area FA.

Furthermore, by occupying the first dummy pattern DP ₁ large relative area of the relatively wide region of the dummy region FA, the number of arranged small second dummy pattern DP ₂ relatively area is relatively small Therefore, an increase in the data amount of the mask can be suppressed. Further, by making the first dummy pattern DP ₁ and the second dummy pattern DP ₂ shape a square, first dummy pattern DP ₁ and the second dummy pattern DP ₂ is expressed in the least amount of data of the origin coordinates and XY coordinates can do. Accordingly, it is possible to suppress an increase in the amount of coordinate data when creating a mask, and it is possible to suppress an increase in calculation processing time in the computer, pattern drawing time on the mask substrate, and the like.

  Next, an example of a method for manufacturing the logic integrated circuit device according to the first embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 6, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is prepared. Next, the semiconductor substrate 1 is thermally oxidized to form a thin silicon oxide film 12 having a thickness of about 10 nm on the surface, and then a silicon nitride film 13 having a thickness of about 120 to 200 nm is deposited thereon by a CVD method. Thereafter, the silicon nitride film 13, the silicon oxide film 12, and the semiconductor substrate 1 are sequentially dry-etched using the resist pattern as a mask to form isolation grooves 2 and 2a having a depth of about 0.3 to 0.4 μm in the semiconductor substrate 1. To do. The dummy region FA, the entire region first dummy pattern DP ₁ and the second dummy pattern DP ₂ so as not to isolation groove is provided.

  Next, in order to clean the interface state of the inner walls of the separation grooves 2 and 2a, the semiconductor substrate 1 is subjected to thermal oxidation treatment, and although not shown, the exposed surface of the semiconductor substrate 1 has a thickness of about 10 to 30 nm. A thin silicon oxide film is formed. Subsequently, as shown in FIG. 7, a silicon oxide film 3 is deposited on the semiconductor substrate 1 by a CVD method or a plasma CVD method. The film thickness of the silicon oxide film 3 is, for example, about 600 to 700 nm, and the surface of the silicon oxide film 3 embedded in the relatively large isolation groove 2a that is easily formed in the boundary BL or the element formation region DA is silicon nitride. It is formed so as to be higher than the surface of the film 13.

  Next, a reversal pattern mask of the separation groove 2 is prepared. On the mask, a pattern of only the relatively large separation groove 2a, which is easily formed in the boundary BL or the element formation area DA, is drawn out of the inverted pattern. For example, the pattern has a specific dimension of 0.6 μm or less. The pattern is removed. Using this mask, a resist pattern 14 is formed on the silicon oxide film 3, and as shown in FIG. 8, the silicon oxide film 3 is about 1/2 of the film thickness (for example, about 300 nm) using the resist pattern 14 as a mask. Etch away. This can improve the flatness of the surface of the silicon oxide film 3 embedded in the relatively large isolation trench 2a that is easily formed in the boundary BL or the element formation region DA in the subsequent CMP process. In addition, although the square-shaped protrusion is formed in the silicon oxide film 3 under the resist pattern 14, this protrusion is polished in a later CMP process.

  Next, as shown in FIG. 9, after removing the resist pattern 14, as shown in FIG. 10, the silicon oxide film 3 is polished by CMP to form the silicon oxide film 3 inside the isolation grooves 2 and 2a. leave. At this time, the silicon nitride film 13 is made to function as a stopper layer at the time of polishing by utilizing the polishing rate of the silicon nitride film 13 and the silicon oxide film 3 so that the silicon nitride film 13 is not scraped off. The scraping amount of the silicon nitride film 13 is suppressed to about 60 nm, for example. Subsequently, the semiconductor substrate 1 is heat-treated at about 1000 ° C., so that the silicon oxide film 3 embedded in the separation groove 2 is densified (baked). Next, as shown in FIG. 11, the silicon nitride film 13 is removed by wet etching using hot phosphoric acid, and then the underlying silicon oxide film 12 is removed.

  Next, as shown in FIG. 12, a p-type impurity, for example, boron (B) for forming the p-type well 4 is ion-implanted in the n-channel MISFET formation region of the semiconductor substrate 1 to form the p-channel MISFET formation region. An n-type impurity for forming the n-type well 5, for example, phosphorus (P) is ion-implanted. Further, although not shown, impurities are ion-implanted into the channel region. Thereafter, the semiconductor substrate 1 is thermally oxidized to form a gate insulating film 6 on the surface of the semiconductor substrate 1 with a thickness of about 2 nm, for example.

  Next, as shown in FIG. 13, after depositing a polycrystalline silicon film on the semiconductor substrate 1 by the CVD method, the polycrystalline silicon film is etched using the resist pattern as a mask, and the gate electrodes of the n-channel MISFET and the p-channel MISFET 7 is formed. Subsequently, the semiconductor substrate 1 is subjected to a dry oxidation process of about 800 ° C., for example.

Next, after covering the n-type well 5 with a resist film, an n-type impurity such as arsenic (As) is ion-implanted into the p-type well 4 using the gate electrode 7 of the n-channel MISFET as a mask, and the source and drain of the n-channel MISFET An extended region 9a is formed. Similarly, after covering the p-type well 4 with a resist film, a p-type impurity such as boron fluoride (BF ₂ ) is ion-implanted into the n-type well 5 using the gate electrode 7 of the p-channel MISFET as a mask, and the p-channel MISFET Source / drain extension regions 15a are formed.

  Next, as shown in FIG. 14, after an insulating film such as a silicon oxide film or a silicon nitride film is deposited on the semiconductor substrate 1 by the CVD method, this insulating film is anisotropically etched by the RIE (reactive ion etching) method. Then, sidewall spacers 8 made of an insulating film are formed on the side walls of the gate electrode 7 of the n-channel MISFET and the gate electrode 7 of the p-channel MISFET.

  Next, after covering the n-type well 5 with a resist film, an n-type impurity, for example, arsenic is ion-implanted into the p-type well 4 using the gate electrode 7 and the sidewall spacer 8 of the n-channel MISFET as a mask, and the source of the n-channel MISFET The drain diffusion region 9b is formed. Similarly, after covering the p-type well 4 with a resist film, a p-type impurity, for example, boron fluoride is ion-implanted into the n-type well 5 using the gate electrode 7 of the p-channel MISFET as a mask, and the source and drain of the p-channel MISFET A diffusion region 15b is formed.

  Next, as shown in FIG. 15, after an interlayer insulating film 10 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1, the surface of the interlayer insulating film 10 is etched or etched using a CMP method. Flatten. Next, the interlayer insulating film 10 is etched using the resist pattern as a mask, and contact holes 11 reaching the source and drain diffusion regions 9b of the n-channel MISFET and the source and drain diffusion regions 15b of the p-channel MISFET are opened. Although not shown, a contact hole reaching the gate electrode 7 of the n-channel MISFET and the p-channel MISFET is formed at the same time.

  Next, as shown in FIG. 16, a metal film, for example, a tungsten (W) film is deposited on the interlayer insulating film 10, and the surface of the metal film is planarized by, for example, a CMP method. A plug 16 is formed by embedding a metal film therein. Thereafter, the metal film deposited on the upper layer of the interlayer insulating film 10 is etched to form the first layer wiring 17.

  Thereafter, the logic integrated circuit device is substantially completed by forming a wiring above the first layer wiring 17 and further forming a surface protective film.

(Embodiment 2)
In the second embodiment, another manufacturing method in the case of forming the structure of FIG. 1 described in the first embodiment will be described.

  FIGS. 17 and 18 for explaining the second embodiment are cross-sectional views of the main part of the semiconductor substrate after the manufacturing steps explained in FIGS. 6 to 7 in the first embodiment.

  Here, first, isolation grooves 2 and 2 a having a depth of about 0.3 to 0.4 μm are formed in the semiconductor substrate 1, and then a silicon oxide film 3 is deposited on the semiconductor substrate 1 by a CVD method or a plasma CVD method.

  Next, as shown in FIG. 17, a coatable insulating film 18, for example, an SOG (spin on glass) film is formed on the silicon oxide film 3. The coatable insulating film 18 can flatten the surface even when there is a fine step due to its fluidity. Therefore, even when a depression is generated on the surface of the silicon oxide film 3, the surface of the coatable insulating film 18 is flattened. Subsequently, the semiconductor substrate 1 is subjected to heat treatment to remove the solvent in the coatable insulating film 18 and densify it. This heat treatment temperature can be set to, for example, about 400 to 500 ° C. in the case of furnace annealing, and about 700 to 800 ° C. in the case of RTA (rapid thermal annealing).

  Next, as shown in FIG. 18, the coatable insulating film 18 is etched by an etch back method. At this time, etching is performed until substantially all of the coatable insulating film 18 is removed using a condition in which the etching rate of the silicon oxide film 3 and the etch rate of the coatable insulating film 18 are substantially the same. Flatten the surface. Next, as shown in FIG. 10, the silicon oxide film 3 on the silicon nitride film 2 is polished by CMP to leave the silicon oxide film 3 inside the isolation trenches 2 and 2a.

  Since the subsequent steps are the same as those described with reference to FIG. 11 and subsequent drawings of the first embodiment, the description thereof is omitted.

  As described above, according to the second embodiment, it is possible to improve the flatness of the surface of the silicon oxide film 3 embedded in the relatively large isolation trench 2a that is easily formed in the boundary BL or the element formation region DA. Further, since the mask for transferring the resist pattern 14 used for planarizing the surface of the silicon oxide film 3 in the first embodiment is not required, the manufacturing cost can be reduced compared with the first embodiment.

(Embodiment 3)
In the third embodiment, another manufacturing method for forming the structure of FIG. 1 described in the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 19, the semiconductor substrate 1 made of, for example, p-type single crystal silicon is thermally oxidized to form a gate insulating film 19 made of a thin silicon oxide film having a thickness of about 2 to 3 nm on the surface thereof. Next, a first silicon film 20 having a thickness of about 50 nm and a silicon nitride film 21 having a thickness of about 120 to 200 nm are sequentially deposited thereon by CVD, and then the silicon nitride film 21, the first silicon film 20 and the gate are formed using a resist pattern as a mask. The insulating film 19 is sequentially dry etched. The first silicon film 20 is made of amorphous silicon or polycrystalline silicon. Subsequently, after removing the resist pattern, the semiconductor substrate 1 is dry-etched using the silicon nitride film 21 as a mask to form isolation grooves 2 and 2a having a depth of about 0.3 to 0.4 μm in the semiconductor substrate 1. . The dummy region FA, the entire region first dummy pattern DP ₁ and the second dummy pattern DP ₂ so as not to isolation groove is provided.

  Next, although not shown, after a thin silicon oxide film having a thickness of about 10 to 30 nm is formed on the exposed surface of the semiconductor substrate 1, a CVD method or a plasma CVD method is performed on the semiconductor substrate 1 as shown in FIG. A silicon oxide film 3 having a thickness of about 600 to 700 nm is deposited. Next, as shown in FIG. 21, the silicon oxide film 3 is left inside the isolation trenches 2 and 2a, for example, in the same manner as in the manufacturing method described with reference to FIGS.

Next, as shown in FIG. 22, the silicon nitride film 21 is removed by wet etching using hot phosphoric acid. At this time, the first silicon film 20 is not removed and used as a part of the gate electrodes of the CMOSFETs C ₁ , C ₂ , and C ₃ . Next, a p-type impurity for forming the p-type well 4 is ion-implanted in the n-channel MISFET formation region of the semiconductor substrate 1, and an n-type impurity for forming the n-type well 5 is formed in the p-channel MISFET formation region. Ion implantation. Further, although not shown, impurities are ion-implanted into the channel region. Thereafter, a second silicon film 22 is formed on the semiconductor substrate 1, and the gate electrodes of CMOSFETs C ₁ , C ₂ , and C ₃ are configured by the laminated film including the first silicon film 20 and the second silicon film 22.

  Since the subsequent steps are the same as those described with reference to FIG. 13 and subsequent drawings of the first embodiment, the description thereof is omitted.

As described above, according to the third embodiment, the first silicon film used for the formation of the element isolation region IS is used as a part of the gate electrodes of the CMOSFETs C ₁ , C ₂ , and C _3. It is possible to prevent kinks occurring in the drain current-gate voltage characteristics due to the roundness of the end of the isolation trench due to the drop of the silicon oxide film 3 embedded in the gate electrode.

(Embodiment 4)
An example of the arrangement of another dummy pattern according to the fourth embodiment will be described with reference to FIGS. FIG. 23 is a main part plan view showing another example of the logic integrated circuit device, and FIG. 24 is a plan view for explaining the pitch and dimension of the dummy pattern.

As shown in FIG. 23, as in the first embodiment, the inside of the boundary BL indicated by a broken line is an element formation region DA where a semiconductor element is formed, and this region includes CMOSFETs C ₁ , C ₂ , C ₃ is formed. Further, the outside of the boundary BL is a dummy area FA where no semiconductor element is formed.

Dummy region The FA, in addition to the first dummy pattern DP ₁ and the second dummy pattern DP ₂ described in the first embodiment, is further disposed a third dummy pattern DP ₃ of the area is larger rectangle than these Yes. That is, three types of dummy patterns (first dummy pattern DP ₁ , second dummy pattern DP ₂ , third dummy pattern DP ₃ ) having different shapes and areas are regularly arranged in the dummy area FA. The third dummy pattern DP ₃ is (in FIG. 23, a relatively thin shaded hatching) rectangular semiconductor islands corresponding to active region AC is composed of.

Fig As shown in 24, the dimensions of the third dummy long side of the pattern DP ₃ dimensions Laa and short La is set larger than the size Lb of the second dummy pattern DP ₂ one side, adjacent third space dimension between the dummy pattern DP ₃ is the same as the space size Sa between the second dummy pattern DP ₂ adjacent.

Further, the dimensions of one side of the third dummy pattern DP ₃ is the row direction, and an integral multiple of the pattern size obtained by adding the space size Sa to the size Lb of the second dummy pattern DP ₂ a side in the column direction both, Laa + Sa = The relationship N1 (Lb + Sa), La + Sa = N2 × (Lb + Sa) (N1, N2 ≧ 1) is satisfied. Accordingly, a plurality of first dummy patterns DP ₁ , second dummy patterns DP _2, and third dummy patterns DP ₃ having different dimensions can be regularly arranged in the dummy area FA. Even if increases, it is possible to suppress an increase in calculation processing time in the computer.

The arrangement data of the first dummy pattern DP ₁ , the second dummy pattern DP _2, and the third dummy pattern DP ₃ is created using the first dummy pattern DP ₁ and the first dummy pattern DP ₁ described with reference to the process diagram of FIG. It performed in the same manner as the method for creating placement data of the second dummy pattern DP _2.

First, an arrangement prohibition area (element formation area DA) of the first dummy pattern DP ₁ , the second dummy pattern DP ₂ and the third dummy pattern DP ₃ is obtained. Then, it laid the third dummy pattern DP ₃ the majority of the dummy region FA. For example, after a mesh is created on the entire surface of the semiconductor substrate 1 at a third pitch, the mesh over the arrangement prohibition region of the first dummy pattern DP ₁ , the second dummy pattern DP ₂ and the third dummy pattern DP ₃ is removed. Thereafter, placing a third dummy pattern DP ₃ to the mesh. Here, the third pitch and the pattern size (Laa + Sa) obtained by adding the space size Sa to the long side dimension Laa one side the third dummy pattern DP _3, the short side of the other side is the third dummy pattern DP ₃ The pattern size (La + Sa) is obtained by adding the space dimension Sa to the dimension La.

Then, determine the first placement prohibiting region of the dummy pattern DP _1. The placement of the first dummy pattern DP ₁ is prohibited by adding an area where the third dummy pattern DP ₃ is spread to the placement prohibited area of the first dummy pattern DP ₁ , the second dummy pattern DP ₂ and the third dummy pattern DP _3. This is an area. Then, he laid the first dummy pattern DP ₁ in the dummy region FA. For example, after the mesh is generated at a first pitch on the entire surface of the semiconductor substrate 1, to remove the mesh applied to the first placement prohibiting region of the dummy pattern DP _1. Thereafter, placing a first dummy pattern DP ₁ mesh. Note that the first pitch wherein a pattern size obtained by adding the space size Sa to the size La of the first dummy pattern DP ₁ a side (La + Sa).

Next, determine the second placement prohibiting region of the dummy pattern DP _2. An area where the first dummy pattern DP ₁ and the third dummy pattern DP ₃ are laid out is added to the arrangement prohibited area of the first dummy pattern DP ₁ , the second dummy pattern DP ₂ and the third dummy pattern DP ₃ , and the second the placement prohibited area of the dummy pattern DP _2. Then, he laid a second dummy pattern DP ₂ in the dummy region FA. For example, after the mesh is generated by a second pitch over the entire surface of the semiconductor substrate 1, to remove the mesh required for placement prohibiting region of the second dummy pattern DP _2. Thereafter, placing a second dummy pattern DP ₂ to mesh. Note that the second pitch here, a pattern size obtained by adding the space size Sa to the size Lb of the second dummy pattern DP ₂ side (Lb + Sa).

As described above, according to the fourth embodiment, the dummy pattern can be selected in any shape regardless of the size of the area, and three or more types of dummy patterns can be combined. Thereby, the degree of freedom of arrangement of the dummy patterns is increased, and the flatness of the surface of the silicon oxide film 3 embedded in the isolation grooves 2 and 2a can be improved. Furthermore, by increasing the number of arranged large dummy pattern DP ₃ relatively area, it is possible to suppress an increase in the data amount of the mask.

(Embodiment 5)
An arrangement example of the wiring dummy pattern according to the fifth embodiment will be described with reference to FIGS. FIG. 25 is a plan view of an essential part showing an example of a wiring dummy pattern, FIG. 26 is a plan view for explaining the pitch and dimensions of the wiring dummy pattern, and FIG. 27 is a logic integration using the dummy pattern for the wiring. It is principal part sectional drawing which shows an example of a circuit device.

  There is a wiring dummy method as one of the methods for overcoming the inconvenience caused by the surface step in the wiring process. This method is a method of laying a dummy pattern (conductive island) made of the same material as the wiring between the wirings, and is an effective means for flattening the insulating film covering the wirings and for reducing the surface step. . A fifth embodiment in which the present invention is applied to this wiring dummy system will be described below.

  As shown in FIG. 25, the inside of the boundary BL indicated by a broken line is an element formation area DA where the wiring ML is formed, and the outside of the boundary BL is a dummy area FA where the wiring ML is not formed.

In the dummy area FA, a plurality of first dummy wirings DML _{1 having} a relatively large area and a plurality of second dummy wirings DML ₂ having a relatively small area made of the same conductive layer as the wiring ML are regularly arranged. ing.

As shown in FIG. 26, the first dummy wiring DML ₁ occupying a relatively large area in the dummy area FA has a rectangular conductive island having a long side dimension Lca and a short side dimension Lc (in FIG. 25, The second dummy wiring DML ₂ is formed of a square conductive island having a side dimension Ld in both the row direction and the column direction (in FIG. 25, a relatively dark hatching). (Shown by hatching).

Further, the inter-row space dimension between the adjacent first dummy wirings DML _{1 and the} inter-row space dimension between the adjacent second dummy wirings DML ₂ are set to the same space dimension Sc, and the column between the adjacent first dummy wirings DML ₁ is set. The inter-space dimension and the inter-row space dimension between the adjacent second dummy wirings DML ₂ are set to the same space dimension Sd. The widths Lca and Lc of the first dummy wiring DML ₁ and the width Ld of the second dummy wiring DML ₂ are set to be equal to or larger than the minimum line width required by the lithography technique and the dry etching technique, and the spaces Sc and Sd are the lithography technique and the dry etching. The minimum space width required by the technology should be exceeded.

Here, the pattern size obtained by adding the space dimension Sc to the long side dimension Lca of the first dummy wiring DML ₁ is an integral multiple of the pattern size obtained by adding the space dimension Sc to the one side dimension Ld of the second dummy wiring DML _2. Therefore, the relationship of Lca + Sc = N (Ld + Sc) (N ≧ 1) is satisfied. Similarly, the pattern size obtained by adding the space dimension Sd to the short side dimension Lc of the first dummy wiring DML ₁ is an integral multiple of the pattern size obtained by adding the space dimension Sd to the one side dimension Ld of the second dummy wiring DML _2. Thus, the relationship of Lc + Sd = N (Ld + Sd) (N ≧ 1) is satisfied.

  FIG. 27 is a fragmentary cross-sectional view of a semiconductor substrate showing an example of a logic integrated circuit device to which the wiring dummy method of the fifth embodiment is applied.

For example, the interlayer insulating film 10 is formed so as to cover the CMOSFETs C ₁ , C ₂ , and C ₃ described in FIG. 2 of the first embodiment, and the first layer wiring 17 is formed on the interlayer insulating film 10. The surface of the interlayer insulating film 10 is planarized by a CMP method or an etch back method. Further, the first layer wiring 17 is covered with an interlayer insulating film 23. The surface of the interlayer insulating film 23 is planarized by an etch back method or the like.

A second layer wiring 24 and a dummy wiring 25 are formed in the upper layer of the interlayer insulating film 23. Here, for example, the first dummy wiring DML ₁ and the second dummy wiring DML ₂ are used as the dummy wiring 25. The second layer wiring 24 and the dummy wiring 25 are made of the same material and formed in the same process. Examples of the material include metals such as aluminum (Al) and copper (Cu).

The second layer wiring 24 and the dummy wiring 25 are covered with an interlayer insulating film 26. The interlayer insulating film 26 is a laminated film made of, for example, a silicon oxide film, SOG (spin on glass), and a silicon oxide film. The silicon oxide film is made of TEOS (tetraethyl orthosilicate: Si (OC ₂ H ₅ ) ₄ ). A TEOS oxide film deposited by plasma CVD using ozone (O ₃ ) as a source gas can be obtained. The surface of the interlayer insulating film 26 is polished by the CMP method, and the surface is flattened by using the dummy wiring 25 (first dummy wiring DML ₁ , second dummy wiring DML ₂ ).

  Further, a third layer wiring 27 is formed above the interlayer insulating film 26, and although not shown, a passivation film which is the uppermost insulating film is formed.

  In the fifth embodiment, the dummy wiring 25 is arranged in the formation process of the second layer wiring 24. However, the dummy wiring may be arranged in the formation process of the first layer wiring 17 or the third layer wiring 27. In addition, even when the wiring above the third layer wiring 27 is formed, it is also possible to arrange dummy wiring in the wiring forming process.

Thus, according to the fifth embodiment, by using the first dummy wiring DML ₁ having a relatively large area and the second dummy wiring DML ₂ having a relatively small area, the entire dummy area FA can be provided. Since the dummy wiring 25 can be disposed, the flatness of the surface of the interlayer insulating film 26 formed on the second layer wiring 24 is improved. Further, by occupying a relatively large area of the dummy area FA with the first dummy wiring DML ₁ having a relatively large area, the number of the second dummy wirings DML ₂ having a relatively small area is relatively small. Therefore, an increase in the data amount of the mask can be suppressed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, although the shape of the dummy pattern is a square or a rectangle in the above embodiment, the shape is not limited to this, and may be a triangular system, a trapezoid, a circle, or another polygon.

  The present invention can be applied to a semiconductor device including a planarization process using a CMP method in its manufacturing process.

1 is a plan view of a principal part showing an example of a logic integrated circuit device according to a first embodiment; It is sectional drawing of the AA line of FIG. It is a top view for demonstrating the pitch and dimension of a dummy pattern. It is a top view for demonstrating an example of arrangement | positioning of a dummy pattern. It is process drawing which shows an example of the creation method of a dummy pattern. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view of the principal part of the semiconductor substrate showing an example of the method of manufacturing the logic integrated circuit device according to the first embodiment in the order of steps. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the logic integrated circuit device which is this Embodiment 2 in order of a process. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the logic integrated circuit device which is this Embodiment 2 in order of a process. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the logic integrated circuit device which is this Embodiment 3 in process order. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the logic integrated circuit device which is this Embodiment 3 in process order. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the logic integrated circuit device which is this Embodiment 3 in process order. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the logic integrated circuit device which is this Embodiment 3 in process order. It is a principal part top view which showed an example of the other logic integrated circuit device of this Embodiment 4. It is a top view for demonstrating the pitch and dimension of a dummy pattern. It is a principal part top view which shows an example of the dummy pattern of the wiring of this Embodiment 5. It is a top view for demonstrating the pitch and dimension of the dummy pattern of wiring. It is principal part sectional drawing which shows an example of the logic integrated circuit device which used the dummy pattern for the wiring of this Embodiment 5. FIG. It is a top view which shows the arrangement | positioning method of the 1st dummy pattern which this inventor examined. It is a top view which shows the arrangement | positioning method of the 2nd dummy pattern which this inventor examined.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation groove 2a Separation groove 3 Silicon oxide film 4 P-type well 5 N-type well 6 Gate insulating film 7 Gate electrode 8 Side wall spacer 9a Source, drain extended region 9b Source, drain diffusion region 10 Interlayer insulating film 11 Contact Hole 12 Silicon oxide film 13 Silicon nitride film 14 Resist pattern 15 a Source, drain extension region 15 b Source, drain diffusion region 16 Plug 17 First layer wiring 18 Coating insulating film 19 Gate insulating film 20 First silicon film 21 Silicon nitride film 22 2nd silicon film 23 Interlayer insulation film 24 2nd layer wiring 25 Dummy wiring 26 Interlayer insulation film 27 3rd layer wiring DA Element formation area FA Dummy area AC Active area IS Element isolation area BL Boundary ML wiring DP ₁ 1st dummy pattern DP ₂ Second dummy pattern DP ₃ 3rd dummy pattern DML ₁ 1st dummy wiring DML ₂ 2nd dummy wiring DPA ₁ Dummy pattern DPA ₂ Dummy pattern C ₁ CMOSFET
C ₂ CMOSFET
C ₃ CMOSFET

Claims (8)

An element isolation region formed in a semiconductor substrate, an element formation region defined by the element isolation region, a semiconductor element formed in the element formation region, an interlayer insulating film covering the semiconductor element, and the interlayer insulating film A semiconductor device having a plurality of wirings formed thereon,
The element isolation region is a region in which an insulating film is embedded in a groove formed in the semiconductor substrate,
The element formation region includes an active region where the semiconductor element is formed and a dummy region where the semiconductor element is not formed,
The dummy region includes a plurality of first dummy patterns and a plurality of second dummy patterns having a smaller shape than the plurality of first dummy patterns,
The plurality of wirings include a plurality of first dummy wirings and a plurality of second dummy wirings having a shape smaller than that of the plurality of first dummy wirings,
The semiconductor device, wherein the plurality of first dummy wirings and the plurality of second dummy wirings are formed above the plurality of first dummy patterns and the plurality of second dummy patterns. An element isolation region formed in a semiconductor substrate, an element formation region defined by the element isolation region, a semiconductor element formed in the element formation region, an interlayer insulating film covering the semiconductor element, and the interlayer insulating film A semiconductor device having a plurality of wirings formed thereon,
The element isolation region is a region in which an insulating film is embedded in a groove formed in the semiconductor substrate,
The element formation region includes an active region where the semiconductor element is formed and a dummy region where the semiconductor element is not formed,
The dummy region includes a plurality of first dummy patterns and a plurality of second dummy patterns having a smaller shape than the plurality of first dummy patterns,
The plurality of first dummy patterns are formed in the same shape and are regularly arranged,
The plurality of second dummy patterns are each formed in the same shape and are regularly arranged,
The plurality of wirings include a plurality of first dummy wirings and a plurality of second dummy wirings having a shape smaller than that of the plurality of first dummy wirings,
The plurality of first dummy wirings are formed in the same shape and are regularly arranged,
The plurality of second dummy wirings are formed in the same shape and are regularly arranged,
The semiconductor device, wherein the plurality of first dummy wirings and the plurality of second dummy wirings are formed above the plurality of first dummy patterns and the plurality of second dummy patterns.   3. The semiconductor device according to claim 1, wherein the shapes of the plurality of first dummy patterns and the shapes of the plurality of second dummy patterns are each quadrangular.   4. The semiconductor device according to claim 3, wherein a value obtained by adding an interval between the plurality of second dummy patterns to a dimension of one side of the second dummy pattern is equal to the plurality of dimensions of one side of the first dummy pattern. The semiconductor device is characterized by being an integral number of a value obtained by adding the interval between the first dummy patterns.   5. The semiconductor device according to claim 1, wherein the plurality of wirings further include a wiring electrically connected to the semiconductor element, the plurality of first dummy wirings and the plurality of first wirings. 2. The semiconductor device according to claim 2, wherein the second dummy wiring is a wiring that is not electrically connected to the semiconductor element.   6. The semiconductor device according to claim 1, wherein each of the plurality of first dummy wirings and each of the plurality of second dummy wirings is a quadrangle.   7. The semiconductor device according to claim 6, wherein a value obtained by adding a distance between the plurality of first dummy wirings to a dimension of one side of the first dummy wiring is equal to the dimension of one side of the second dummy wiring. The semiconductor device is characterized by being an integral multiple of a value obtained by adding an interval between the second dummy wirings.   8. The semiconductor device according to claim 1, wherein the plurality of wirings are made of copper.

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