JPS61289635A - Surface flatterning - Google Patents
Surface flatterningInfo
- Publication number
- JPS61289635A JPS61289635A JP13159485A JP13159485A JPS61289635A JP S61289635 A JPS61289635 A JP S61289635A JP 13159485 A JP13159485 A JP 13159485A JP 13159485 A JP13159485 A JP 13159485A JP S61289635 A JPS61289635 A JP S61289635A
- Authority
- JP
- Japan
- Prior art keywords
- incident angle
- ion beam
- etching rate
- theta
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
〔概 要〕
イオン・ビーム・ミリングd二よるエラ?自パックで、
表面の平坦化を行なう方法であって、イオン・ビームの
入射角度を段差部における基板に平行な方向のエツチン
グ速度が平坦部の深さ方向エツチング速度l:比べて大
きくなる角1[C設定する。[Detailed description of the invention] [Summary] Ion beam milling error due to d2? With your own pack,
In this method, the incident angle of the ion beam is set such that the etching rate in the direction parallel to the substrate at the stepped portion is larger than the etching rate in the depth direction l: at the flat portion. .
それにより、少ない工程で容易に平坦化ができる。Thereby, planarization can be easily achieved with fewer steps.
本発明は、半導体素子の製造工程における表面平坦化技
術としてのイオン・ビーム−ミリングによるエッチ・パ
ック法に関するものである。The present invention relates to an etch pack method using ion beam milling as a surface planarization technique in the manufacturing process of semiconductor devices.
現在、半導体素子の高密度化、高速化のための多層配線
において1段差部における断線を防ぐため層間絶縁膜或
は、配線金属の平坦化が必須の技術とされている。平坦
化の方法として従来行なわれているエッチeパック法、
スパッタ・エッチ法について説明する。Currently, planarization of an interlayer insulating film or metal wiring is considered to be an essential technique in order to prevent disconnection at one step in multilayer wiring for increasing the density and speed of semiconductor devices. The etch e-pack method, which is conventionally used as a planarization method,
The sputter etch method will be explained.
1)エッチ・バック法C;よる平坦化例二第4図(α)
のよう::、絶縁暎11上に金属配線バタン12による
段差かある場合、例えば、絶嫌侠としてSi0.15に
スパッタ堆積又はプラズマCVD法により堆積させ、さ
ら(:、レジスト等14 ’&塗布し、レジストの流動
性を利用してレジスト表面を平坦化する(第4図(b)
)。その後、例えばCF番/ Oxプラズマにより、レ
ジスト14とSzO,13のエツチング速度が等しい条
件でエツチングを行なう(第4図(O))。以上の工程
I:より、凹領域を絶縁膜で埋めて1.1diiを平坦
化Tることができる。しかし、この方法では、深い段差
を平坦化する場合、レジスト(:よる表面の平坦化が困
難であること及びレジストと平坦化丁べき材料のエツチ
ング速度を等しくしなければならないという厳しい制限
が課せられる等の問題が生じる。1) Example 2 of planarization using etch-back method C; Fig. 4 (α)
If there is a step formed by the metal wiring batten 12 on the insulating layer 11, for example, it is absolutely necessary to deposit Si0.15 by sputter deposition or plasma CVD method, and then apply a resist etc. Then, the resist surface is flattened using the fluidity of the resist (Fig. 4(b)).
). Thereafter, etching is performed using, for example, CF/Ox plasma under conditions where the etching speed of the resist 14 and the SzO, 13 are equal (FIG. 4(O)). According to the above step I, the recessed region can be filled with an insulating film and 1.1dii can be planarized. However, with this method, when planarizing deep steps, there are severe limitations in that it is difficult to planarize the surface due to the resist, and that the etching speeds of the resist and the material to be planarized must be equal. Problems such as this arise.
2) スパッタ・エツチング1;よる平坦化例:第5図
(α)のようζ;絶縁膜21上ζ;金属配線バタン22
による段差がある場合、例えば絶縁膜としてSin、
25 kスパッタ堆積又はプラズマCVD法により堆積
させる(第5図(b))。その後表面なArプラズマに
よりスパッタ・エツチングする。スパッタ効率の角度依
存性から段差部の角が選択的にエツチングされ、・段差
が緩やか1;なる(第5図(C))。この方法では段差
部の角を選択的d:エッチングするだけC:止まり、十
分な平坦化とはならない。2) Example of planarization by sputter etching 1: ζ as shown in FIG. 5 (α); ζ on the insulating film 21;
For example, if there is a step difference due to
It is deposited by 25K sputter deposition or plasma CVD method (FIG. 5(b)). After that, the surface is sputter etched using Ar plasma. Due to the angular dependence of sputtering efficiency, the corners of the stepped portion are selectively etched, resulting in a gradual step (FIG. 5(C)). This method only selectively etches the corners of the stepped portions, and sufficient planarization is not achieved.
上述のよう1:、従来法では、深い段差の平坦化が困難
であったり、エツチングの条件が厳しい、或は、段差部
の角を選択的にエツチングするにとどまり、十分な平坦
化ができない等、尚不十分であった。As mentioned above, 1: With the conventional method, it is difficult to flatten deep steps, the etching conditions are strict, or only the corners of the step are selectively etched and sufficient planarization cannot be achieved. , it was still insufficient.
本発明は、基板!1面区二段差と同程度乃至それ以上の
膜厚を有する薄膜を形成し、それ艦;より形成される凹
凸をもつ薄膜層Inイオン・ビーム・ミリングC;より
エッチ・バックする際、イオン・ビームの入射角度を段
差部にSける1板に平行な方向のエツチング速度が平坦
部の深さ方向エツチング速度C;比べ大きくなる角度に
設定することを特徴とする。The present invention is a substrate! Forming a thin film with a thickness equal to or greater than that of the two-step difference between the first and second sections; In ion beam milling; It is characterized in that the incident angle of the beam is set to such an angle that the etching rate in the direction parallel to one plate in the stepped portion S is greater than the etching rate C in the depth direction of the flat portion.
上記によれば、エツチング速度のイオン会ビーム入射角
度依存性を利用し、表面の凸部な選択的1ニエツチング
し、表面を平坦化することができる。According to the above, by utilizing the dependence of the etching rate on the incident angle of the ion beam, it is possible to selectively etch the convex portions of the surface and flatten the surface.
イオン入射角度を第5図(α)のように、基板法線1;
対する角度0で定義すると、一般C;イオン・ビーム・
ミリングのエツチング速度のビーム入射角度依存性は、
例えばAhのよう霞:垂直入射(0■0)で最大となる
もの(第5図(j)−51)と、例えばSiのよう1:
θ−40°〜60°で最大となるもの(第5図(b)−
32)と(:大別される。いずれの場合でもイオン入射
角度θが60°以上ではエツチング速度は入射角度の増
大ととも感−減少し90°でゼロとなる。The ion incidence angle is set to the substrate normal 1 as shown in Figure 5 (α);
When defined at an angle of 0 with respect to the general C; ion beam
The dependence of the etching speed in milling on the beam incidence angle is
For example, haze like Ah: Maximum at normal incidence (0■0) (Fig. 5 (j)-51) and 1 like Si:
Maximum at θ-40° to 60° (Fig. 5(b)-
32) and (:). In either case, when the ion incidence angle θ is 60° or more, the etching rate decreases as the incidence angle increases and becomes zero at 90°.
したがって、第2図に示すように段差をもつ表面をイオ
ン入射角度θでエッチ・パックする場合、段差斜面への
入射角度θはθくθであり、エツチング速度のイオン・
ビーム入射角度依存性と段差形状C=より段差斜面のエ
ツチング速度R(θ)が平坦部でのエツチング速度R(
θ)に比べ大きくなるθが存在する。この入射角度での
エッチ・パックにより凸部の薄膜上選択的にエツチング
することができる(以下斜めイオン会ビーム争ミリング
と呼ぶ)。Therefore, when a surface with steps is etched and packed at an ion incidence angle θ as shown in FIG.
From the dependence of the beam incidence angle and the step shape C=, the etching speed R(θ) on the step slope is the same as the etching speed R(θ) on the flat part.
There is a θ that is larger than θ). The etch pack at this incident angle allows selective etching on the thin film on the convex portion (hereinafter referred to as oblique ion beam milling).
本発明の実施例として、幅1μm、厚さ0.5μ罵のS
in、膜バタンかう成る凹領域のみC:A塾を残し、表
面を平坦化する場合を第1図に示す。上記S g Q
を膜パタン51から成る凹凸表面全面ζ;Au52を例
えばスパッタ堆積法C;より0.4μ簿堆積する(第1
図(α))。その後例えば約70°のイオン入射角度を
もつイオン・ビーム・ミリング(イオン・ビーム55)
によりエッチ・バックを行なう。どの時、段差斜面のエ
ツチング速度は平坦部のエツチング速度に比べ約5倍で
あり、凸部のAs&t/選択的C:エツチングすること
ができる(第1図(b))。上述エッチ・バックfsi
O1膜が露出するまで行なうことによリ、Sin、パタ
ンの凹領域のみにAmを残し、表面は平坦化される(第
1図(C))。As an example of the present invention, S with a width of 1 μm and a thickness of 0.5 μm is used.
FIG. 1 shows a case where only the concave region formed by the film bump is left with C:A cram, and the surface is flattened. Above S g Q
Au 52 is deposited on the entire surface of the uneven surface ζ consisting of the film pattern 51 by, for example, 0.4μ by sputter deposition method C (first
Figure (α)). Then, for example, ion beam milling (ion beam 55) with an ion incidence angle of about 70°
Perform sex back. At any given time, the etching speed of the stepped slope is about five times that of the flat part, and As&t/selective C: etching of the convex part can be performed (FIG. 1(b)). The above sex back fsi
By performing this process until the O1 film is exposed, the surface is flattened, leaving only the Sin and Am in the concave areas of the pattern (FIG. 1C).
以上説明したように、斜めイオン・ビーム・ミリングに
よるエッチ・バックにより、少ない工程で、容易i二平
坦化することができる。この平坦化エッチ・パック法は
、多層配線1二必要な平坦化、及び凹パタンを利用した
自己整合的バタン形成等。As explained above, by etching back using oblique ion beam milling, planarization can be easily achieved with a small number of steps. This planarization etch-pack method includes the necessary planarization of the multilayer wiring 12 and self-aligned batten formation using a concave pattern.
幅広い応用分野をもつという利点がある0It has the advantage of having a wide range of application fields0
第1因−)〜(ff)は本発明の実施例の要部工程断面
図、
第2因≠構は本発明の詳細な説明するための図。
第3図(a) 、 1k)はそれぞれイオン入射角度の
定義を説明する因及びイオン入射角度とエツチング速度
の関係を示す図、
第4図+8) 〜(C)及び第5図(a) 〜<01は
それぞ、れ第1の従来例及び第2の従来例の工程図であ
る。
11・・・絶縁膜、12・・・金属配線、13・・・層
間絶縁膜、21・・・絶縁膜、22・・・金属配線、2
5・・・層間絶縁j[,51・・・Sin!(バタン)
、52・・・Aμ、53・・・イオン・ビーム
特許出願人 日本電信電話株式会社
代理人 弁運士 玉蟲久五部(外2名)1JJIT+
発明の実施例の工程圏
第 1 図
発明の詳細な説明する図
第2母
ItJIRIIJマターン
1フ
第1の従来例を示す工程口
第 4 図
第2の従来例を示す図
第5 図The first factor -) to (ff) are cross-sectional views of the main steps of the embodiment of the present invention, and the second factor≠structure is a diagram for explaining the present invention in detail. Figures 3(a) and 1k) are diagrams for explaining the definition of the ion incidence angle and the relationship between the ion incidence angle and the etching rate, Figure 4+8) ~ (C) and Figure 5 (a) ~ <01 are process diagrams of the first conventional example and the second conventional example, respectively. DESCRIPTION OF SYMBOLS 11... Insulating film, 12... Metal wiring, 13... Interlayer insulating film, 21... Insulating film, 22... Metal wiring, 2
5... Interlayer insulation j[,51...Sin! (bang)
, 52... Aμ, 53... Ion beam patent applicant Nippon Telegraph and Telephone Corporation Agent Benten clerk Gobe Tamamushi (2 others) 1JJIT+ Process area of embodiments of the invention Figure 1 Details of the invention Fig. 5 shows the second conventional example.
Claims (1)
至それ以上の膜厚を有する薄膜を堆積する工程と、 基板法線に対するイオン入射角度を、段差斜面における
基板に平行な方向へのエッチング速度が平坦部の深さ方
向エッチング速度に比べ大きくなるような角度に設定し
、イオン・ミリングにより薄膜をエッチ・バックする工
程とを含むことを特徴とする表面平坦化方法。[Claims] A step of depositing a thin film on the surface of a substrate having a step on the surface, the thickness of which is comparable to or thicker than the step; surface flattening characterized by including the step of etching back the thin film by ion milling at an angle such that the etching rate in the direction parallel to the flat part is higher than the etching rate in the depth direction of the flat part. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13159485A JPS61289635A (en) | 1985-06-17 | 1985-06-17 | Surface flatterning |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13159485A JPS61289635A (en) | 1985-06-17 | 1985-06-17 | Surface flatterning |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61289635A true JPS61289635A (en) | 1986-12-19 |
JPH0551174B2 JPH0551174B2 (en) | 1993-07-30 |
Family
ID=15061704
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13159485A Granted JPS61289635A (en) | 1985-06-17 | 1985-06-17 | Surface flatterning |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61289635A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4966885A (en) * | 1989-08-25 | 1990-10-30 | At&T Bell Laboratories | Method of producing a device comprising a metal oxide superconductor layer |
US5744400A (en) * | 1996-05-06 | 1998-04-28 | Accord Semiconductor Equipment Group | Apparatus and method for dry milling of non-planar features on a semiconductor surface |
US7378029B2 (en) | 2004-02-23 | 2008-05-27 | Tdk Corporation | Method for manufacturing magnetic recording medium |
US8578594B2 (en) | 2011-06-06 | 2013-11-12 | Western Digital (Fremont), Llc | Process for fabricating a magnetic pole and shields |
US8597528B1 (en) | 2011-03-30 | 2013-12-03 | Western Digital (Fremont), Llc | Method and system for defining a read sensor using an ion mill planarization |
US9053735B1 (en) | 2014-06-20 | 2015-06-09 | Western Digital (Fremont), Llc | Method for fabricating a magnetic writer using a full-film metal planarization |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9780366B2 (en) * | 2013-08-29 | 2017-10-03 | Stmicroelectronics (Tours) Sas | Silicon microstructuring method and microbattery |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5432985A (en) * | 1977-08-19 | 1979-03-10 | Mitsubishi Electric Corp | Flattening method for substrate surface with protrusion |
JPS55143035A (en) * | 1979-04-24 | 1980-11-08 | Nec Corp | Manufacture of pattern |
JPS5882536A (en) * | 1981-11-10 | 1983-05-18 | Fujitsu Ltd | Preparation of semiconductor device |
-
1985
- 1985-06-17 JP JP13159485A patent/JPS61289635A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5432985A (en) * | 1977-08-19 | 1979-03-10 | Mitsubishi Electric Corp | Flattening method for substrate surface with protrusion |
JPS55143035A (en) * | 1979-04-24 | 1980-11-08 | Nec Corp | Manufacture of pattern |
JPS5882536A (en) * | 1981-11-10 | 1983-05-18 | Fujitsu Ltd | Preparation of semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4966885A (en) * | 1989-08-25 | 1990-10-30 | At&T Bell Laboratories | Method of producing a device comprising a metal oxide superconductor layer |
US5744400A (en) * | 1996-05-06 | 1998-04-28 | Accord Semiconductor Equipment Group | Apparatus and method for dry milling of non-planar features on a semiconductor surface |
US7378029B2 (en) | 2004-02-23 | 2008-05-27 | Tdk Corporation | Method for manufacturing magnetic recording medium |
US8597528B1 (en) | 2011-03-30 | 2013-12-03 | Western Digital (Fremont), Llc | Method and system for defining a read sensor using an ion mill planarization |
US8578594B2 (en) | 2011-06-06 | 2013-11-12 | Western Digital (Fremont), Llc | Process for fabricating a magnetic pole and shields |
US9053735B1 (en) | 2014-06-20 | 2015-06-09 | Western Digital (Fremont), Llc | Method for fabricating a magnetic writer using a full-film metal planarization |
Also Published As
Publication number | Publication date |
---|---|
JPH0551174B2 (en) | 1993-07-30 |
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Legal Events
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EXPY | Cancellation because of completion of term |