JPH02273922A - Formation of through hole - Google Patents

Formation of through hole

Info

Publication number
JPH02273922A
JPH02273922A JP9671589A JP9671589A JPH02273922A JP H02273922 A JPH02273922 A JP H02273922A JP 9671589 A JP9671589 A JP 9671589A JP 9671589 A JP9671589 A JP 9671589A JP H02273922 A JPH02273922 A JP H02273922A
Authority
JP
Japan
Prior art keywords
film
hole
insulating film
silicon nitride
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9671589A
Other languages
Japanese (ja)
Inventor
Junichiro Tojo
東條 潤一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9671589A priority Critical patent/JPH02273922A/en
Publication of JPH02273922A publication Critical patent/JPH02273922A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make the etching rate of the upper layer of an interlayer insulating film differ from that of the lower layer of the insulating film and to make it possible to form properly the taper angle of a through hole by a method wherein the film quality of the upper layer is made to differ from that of the lower layer. CONSTITUTION:An interlayer insulating film 14 is constituted of a lower layer 15, which is a silicon nitride film of fine film quality, and an upper layer 16, which is a silicon nitride film of rough film quality. That is, as the etching rate of the silicon nitride film, which is the upper layer 16 of rough film quality, is larger than that of the silicon nitride film, which is the lower layer 15 of fine film quality, a through hole 19 having a proper taper angle of 30 to 50 deg. can be formed by performing an isotropic etching using a resist pattern 17 as a mask.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は適切なテーパー角を有するスルーホールの形成
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of forming a through hole having an appropriate taper angle.

(ロ)従来の技術 半導体装置においてはその高密度化に伴い多層配線構造
が多用されており、さらには上層と下層の配線層を接続
する為のスルーホールは上層配線のステップカバレージ
の改善からテーパー状とすることが例えば特開昭62−
9638号公報に記載されている。
(b) Conventional technology Multilayer wiring structures are frequently used in semiconductor devices due to their increasing density, and through holes for connecting upper and lower wiring layers are tapered to improve step coverage of upper layer wiring. For example, JP-A-62-
It is described in Publication No. 9638.

第2図に従来の多層配線構造におけるスルーホールの一
例を示す。同図において、(1)は半導体基板、(2)
はSin、膜、(3)は第1層目のAゑ配線層、(4)
は層間絶縁膜、り5)はスルーホール、(6)は第2層
目のA!配線層である。
FIG. 2 shows an example of a through hole in a conventional multilayer wiring structure. In the figure, (1) is a semiconductor substrate, (2)
is a Sin, film, (3) is the first layer Ae wiring layer, (4)
is the interlayer insulating film, 5) is the through hole, and (6) is the second layer A! This is a wiring layer.

スルーホール(5)は、第1層目Affi配線層(3)
上にシリコン窒化膜等の層間絶縁膜(4)を堆積し、そ
の上にレジストパターンを形成すると共にレジストパタ
ーンをマスクとしてプラズマエツチングによる等方エツ
チングを行うことにより、側壁をテーパー状に形成して
いた。
The through hole (5) is the first layer Affi wiring layer (3)
An interlayer insulating film (4) such as a silicon nitride film is deposited thereon, a resist pattern is formed thereon, and isotropic etching is performed using plasma etching using the resist pattern as a mask, thereby forming the side walls into a tapered shape. Ta.

(ハ)発明が解決しようとする課題 しかしながら、シリコン窒化膜は耐湿性等、届悶絶縁膜
(4)として適切な特性を持たせる為には膜質を密とす
ることが望まれる一方、膜質を密にするとスルーホール
(5)のテーパー角θが大きくなり、2層目AP配線(
6)のステップカバレージが次第に悪化して断線不良等
を発生する欠点があった。
(c) Problems to be Solved by the Invention However, in order for a silicon nitride film to have moisture resistance and other appropriate properties as a high-performance insulating film (4), it is desirable to have a dense film quality; If the density is increased, the taper angle θ of the through hole (5) will increase, and the second layer AP wiring (
6) The step coverage gradually deteriorates, resulting in failures such as disconnection.

(ニ)課題を解決するための手段 本発明は上記従来の課題に鑑み成されたもので、層間絶
縁膜(14)をシリコン窒化膜の膜質が密なる下層(1
5)と膜質が粗なる上Jl(16)とで構成することに
より、良好なテーパー形状を得ることのできるスルーホ
ールの形成方法を提供するものである。
(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems.
The present invention provides a method for forming a through-hole that can obtain a good tapered shape by forming the through-hole (5) and Jl (16), which has a rough film quality.

(ホ)作用 本発明によれば、膜質が密な下層(15)のシリコン窒
化膜よりも膜質が粗である上層(16)のシリコン窒化
膜の方がエツチングし−トが大きいので、レジストパタ
ーン(17)をマスクとして等方エツチングを行うこと
により、30〜50°の適切なテーパー角を持つスルー
ホール(19)を形成できる。
(E) Effect According to the present invention, the silicon nitride film of the upper layer (16), which has a rougher film quality, is etched more than the silicon nitride film of the lower layer (15), which has a denser film quality. By performing isotropic etching using (17) as a mask, a through hole (19) having an appropriate taper angle of 30 to 50 degrees can be formed.

(へ)実施例 以下本発明の一実施例を図面を参照しながら詳細に説明
する。
(F) EXAMPLE An example of the present invention will be described below in detail with reference to the drawings.

第1図A−Fは本発明によるスルーホールの形成方法を
工程順に示す断面図であり、 先ず第1図Aのように、TR,IC,MO5LSI等を
構成する半導体素子を形成したシリコン半導体基板(1
1)の表面に、シリコン酸化膜(12)を介してアルミ
ニウム(A2)等の電極材料を形成し、これをバターニ
ングすることにより第1層目配線層(13)を形成する
FIGS. 1A to 1F are cross-sectional views showing the method for forming through holes according to the present invention in the order of steps. First, as shown in FIG. (1
An electrode material such as aluminum (A2) is formed on the surface of 1) via a silicon oxide film (12), and this is patterned to form a first wiring layer (13).

次に第1図Bのように、プラズマCVD法により、第1
層目配線層(13)を覆うようにして膜厚10000〜
20000人のシリコン窒化膜(SixNy)から成る
層間絶縁膜(14)の下層(15)を形成する。プラズ
マ窒化膜の形成は、(SiH4+ NHs )あるいは
(SiHa + N* )ガス系で数時間、生成温度2
00〜400℃、生成圧力0.1〜I Torrの条件
で行い、且つSi、N、で表わされるプラズマ窒化膜の
組成が出来るだけ熱分解反対により形成されるSi、N
Next, as shown in FIG. 1B, the first
The film thickness is 10,000~ to cover the wiring layer (13).
A lower layer (15) of an interlayer insulating film (14) made of a silicon nitride film (SixNy) of 20,000 yen is formed. The plasma nitride film is formed in a (SiH4+NHs) or (SiHa+N*) gas system for several hours at a production temperature of 2.
The plasma nitride film is heated under the conditions of 00 to 400°C and a generation pressure of 0.1 to I Torr, and the composition of the plasma nitride film represented by Si, N is as low as possible by Si, N, which is formed by opposite thermal decomposition.
.

に近接し膜質が密となるように(膜緻密性に優れる)形
成する。
The film is formed so that it is close to the film and has a dense film quality (excellent film density).

そして第1図Cのように、再度プラズマCVD法により
下層(15)の上に下II(15)のシリコン窒化膜よ
り膜質が粗なるシリコン窒化膜を膜厚100〜1000
人に堆積して層間絶縁膜(14)の上層(16)とする
。膜質のコントロールは、基板温度、生成圧力、ガス流
量、印加する高周波数と電力等によりコントロールが可
能で、下層(16)よりはエツチングレートが犬になる
ような組成とする。また、下層(16)を堆積した後ウ
ェハーを一部取り出し、再度同じ装置で且つ下層(15
)と同じ生成条件で装置投入後数分間の堆積処理を行う
ことにより、膜質が粗く薄いシリコン窒化膜を形成する
ことが可能である。これはおそらく、ウェハーを一部取
り出した為にウェハー温度が低下することや、処理時間
が短い為にプラズマCVD装置内の温度や圧力が上層(
16)形成時の条件に達する以前の不安定な条件で膜生
成が行われる為と考えられる。
Then, as shown in FIG. 1C, a silicon nitride film having a rougher quality than the silicon nitride film of the lower layer II (15) is deposited on the lower layer (15) again to a thickness of 100 to 1000 using the plasma CVD method.
This layer is deposited on top to form the upper layer (16) of the interlayer insulating film (14). The film quality can be controlled by substrate temperature, production pressure, gas flow rate, applied high frequency and power, etc., and the composition is such that the etching rate is lower than that of the lower layer (16). Also, after depositing the lower layer (16), a part of the wafer is taken out and the lower layer (15) is deposited again using the same apparatus.
), it is possible to form a thin silicon nitride film with rough film quality by performing the deposition process for several minutes after the device is turned on under the same formation conditions. This is probably due to a drop in wafer temperature due to the removal of a portion of the wafer, or a decrease in the temperature and pressure inside the plasma CVD equipment due to the short processing time (
16) This is thought to be because the film is formed under unstable conditions before the conditions at the time of formation are reached.

その後、第1図りのように上fl<16)表面にレジス
ト(17)をスピンオン塗布、露光、現象して開孔部(
18)を形成し、 第1図Eのようにレジスト(17)をマスクとしてCF
、ガスによるプラズマエツチングを行うことにより、層
間絶縁膜(14)を等方エツチングしてテーパー状のス
ルーホール(19)を形成する。層間絶縁膜(14)は
、上層(16)と下層(15)との膜質の差により・上
方(16)の方がエツチングレートが大きいので、エツ
チングは層間絶縁膜(14)の膜厚方向に進むより上J
!(16)が横方向に除去される方が速く進む。従って
、このエツチングにより層間絶縁膜(14)の上層部は
より広く開孔され、従来よりスルーホール(19)のテ
ーパー角θは30〜50°と小さく適切な角度で形成で
きる。尚、膜質の全てを等方エツチングする本実施例の
外、プラズマエッチによる等方エツチングとR・工・E
による異方エツチングでも良い。
Then, as shown in the first diagram, a resist (17) is spin-on coated on the upper fl<16) surface, exposed, and developed to form the opening (
18) and then conduct a CF using the resist (17) as a mask as shown in Figure 1E.
By performing plasma etching using gas, the interlayer insulating film (14) is isotropically etched to form a tapered through hole (19). The interlayer insulating film (14) is etched in the thickness direction of the interlayer insulating film (14) due to the difference in film quality between the upper layer (16) and the lower layer (15).The upper layer (16) has a higher etching rate. Above J
! (16) proceeds faster when removed laterally. Therefore, by this etching, the upper layer of the interlayer insulating film (14) is opened more widely, and the taper angle .theta. of the through hole (19) can be formed at a smaller and appropriate angle of 30 to 50 degrees than in the past. In addition to this example in which the entire film quality is isotropically etched, isotropic etching by plasma etching and R/E etching are also used.
Anisotropic etching may also be used.

そして、第1図Fのように、レジスト(17)を除去し
た後スパッタ法や電子ビーム蒸着法によりアルミニウム
(Af!、)を形成し、これをバターニングすることに
よりスルーホール(19)を介して第1層目配線層(1
3)とコンタクトする第2WI目の配線層(20)を形
成する。
Then, as shown in FIG. 1F, after removing the resist (17), aluminum (Af!) is formed by sputtering or electron beam evaporation, and by buttering this, the through hole (19) is formed. and the first wiring layer (1
A second WI wiring layer (20) is formed in contact with 3).

斯る形成方法によれば、スルーホール(19)のテーパ
ー角が適切でなだらかな段差を有するので、第2M目配
線層(20)のステップカバレージに優れ、段線不良等
を防止できる。
According to such a formation method, the through hole (19) has an appropriate taper angle and has a gentle step, so that the step coverage of the 2Mth wiring layer (20) is excellent and it is possible to prevent defects such as broken lines.

尚、本実施例は2M構造について言及したが、3層、4
層構造でも同様であることは言うまでもない。
Although this example refers to a 2M structure, 3-layer, 4-layer
Needless to say, the same applies to the layered structure.

(ト)発明の効果 以上に説明した通り、本発明によればスルーボール(1
9)のテーパー角を適切に形成できるので、層間接続の
信頼性が高い半導体装置を提供できる。また、層間絶縁
膜(14)としてシリコン窒化膜を使用しているので、
Sin、膜よりは耐湿性、耐圧性、ステップカバレージ
に優れた構造が得られ、きらには膜質を変えることでエ
ツチングレートを変えるので、特に工程を複雑にしなく
て済むという利点を有する。
(g) Effects of the invention As explained above, according to the present invention, a through ball (1
Since the taper angle (9) can be appropriately formed, a semiconductor device with high reliability of interlayer connections can be provided. In addition, since a silicon nitride film is used as the interlayer insulating film (14),
A structure with better moisture resistance, pressure resistance, and step coverage than that of a Sin film can be obtained, and since the etching rate can be changed by changing the film quality, it has the advantage that the process does not need to be particularly complicated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A乃至第1図Fは本発明の形成方法を工程順に示
す断面図、第2図は従来例を説明する為の断面図である
1A to 1F are cross-sectional views showing the forming method of the present invention in the order of steps, and FIG. 2 is a cross-sectional view for explaining a conventional example.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に配線金属を形成する工程、前記配
線金属の上に下層の絶縁膜よりもエッチングレートが大
となるような膜質が粗の絶縁膜を上層にして複数層の絶
縁膜を形成する工程、前記最上層の絶縁膜の上にレジス
トパターンを形成し該レジストパターンをマスクとして
前記複数層の絶縁膜をエッチングしテーパー状のスルー
ホールを形成する工程、とを具備することを特徴とする
スルーホールの形成方法。
(1) A step of forming wiring metal on a semiconductor substrate, in which multiple layers of insulating films are formed on the wiring metal, with an upper layer of an insulating film of rough quality that has a higher etching rate than the underlying insulating film. forming a resist pattern on the uppermost insulating film, and using the resist pattern as a mask, etching the plurality of layers of insulating films to form a tapered through hole. How to form a through hole.
(2)前記絶縁膜はプラズマCVD法によるシリコン窒
化膜(Si_xN_y)であることを特徴とする請求項
第1項に記載のスルーホールの形成方法。
(2) The method for forming a through hole according to claim 1, wherein the insulating film is a silicon nitride film (Si_xN_y) formed by plasma CVD.
JP9671589A 1989-04-17 1989-04-17 Formation of through hole Pending JPH02273922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9671589A JPH02273922A (en) 1989-04-17 1989-04-17 Formation of through hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9671589A JPH02273922A (en) 1989-04-17 1989-04-17 Formation of through hole

Publications (1)

Publication Number Publication Date
JPH02273922A true JPH02273922A (en) 1990-11-08

Family

ID=14172443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9671589A Pending JPH02273922A (en) 1989-04-17 1989-04-17 Formation of through hole

Country Status (1)

Country Link
JP (1) JPH02273922A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336891B1 (en) * 1998-12-16 2003-06-12 주식회사 현대 디스플레이 테크놀로지 Protective Film Formation Method of Thin Film Transistor Liquid Crystal Display Device
JP2007103569A (en) * 2005-10-03 2007-04-19 Nec Lcd Technologies Ltd Thin film transistor, array substrate thereof, liquid crystal display, and their manufacturing method
JP2012038965A (en) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd Semiconductor device and manufacturing method of the same
JPWO2013190838A1 (en) * 2012-06-21 2016-02-08 株式会社Joled TFT substrate and manufacturing method thereof, organic EL display device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336891B1 (en) * 1998-12-16 2003-06-12 주식회사 현대 디스플레이 테크놀로지 Protective Film Formation Method of Thin Film Transistor Liquid Crystal Display Device
JP2007103569A (en) * 2005-10-03 2007-04-19 Nec Lcd Technologies Ltd Thin film transistor, array substrate thereof, liquid crystal display, and their manufacturing method
JP2012038965A (en) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd Semiconductor device and manufacturing method of the same
JPWO2013190838A1 (en) * 2012-06-21 2016-02-08 株式会社Joled TFT substrate and manufacturing method thereof, organic EL display device and manufacturing method thereof
US9564474B2 (en) 2012-06-21 2017-02-07 Joled Inc. TFT substrate, method for producing same, organic EL display device, and method for manufacturing organic EL display device

Similar Documents

Publication Publication Date Title
US4894351A (en) Method for making a silicon IC with planar double layer metal conductors system
JPH05206064A (en) Manufacture of semiconductor device
JPH0563940B2 (en)
JPH02273922A (en) Formation of through hole
KR950006343B1 (en) Fabricating method of semiconductor device
JP2716156B2 (en) Method for manufacturing semiconductor device
JPS6376351A (en) Formation of multilayer interconnection
JPS5893328A (en) Method of flattening insulating layer
JP2646878B2 (en) Semiconductor device and manufacturing method thereof
JPH0346977B2 (en)
JPS63258043A (en) Manufacture of semiconductor device
JP3279737B2 (en) Method for manufacturing semiconductor device
JPH02156538A (en) Manufacture of semiconductor device
JPS63262856A (en) Manufacture of semiconductor device
JPS61239646A (en) Formation of multilayer interconnection
JPS61107743A (en) Manufacture of semiconductor device
JPH04207054A (en) Manufacture of semiconductor device
JPH0685068A (en) Manufacture of semiconductor device
JPS62118539A (en) Formation of multilayer interconnection
JPH05243388A (en) Manufacture of semiconductor device
JPH0555164A (en) Manufacture of semiconductor device
JPH04102321A (en) Manufacture of semiconductor device
JPH0289318A (en) Manufacture of multilayer interconnected semiconductor integrated circuit device
JPS60234344A (en) Manufacture of semiconductor device
JPS60124846A (en) Manufacture of semiconductor device