KR100336891B1 - Protective Film Formation Method of Thin Film Transistor Liquid Crystal Display Device - Google Patents
Protective Film Formation Method of Thin Film Transistor Liquid Crystal Display Device Download PDFInfo
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- KR100336891B1 KR100336891B1 KR10-1998-0055255A KR19980055255A KR100336891B1 KR 100336891 B1 KR100336891 B1 KR 100336891B1 KR 19980055255 A KR19980055255 A KR 19980055255A KR 100336891 B1 KR100336891 B1 KR 100336891B1
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- 239000010408 film Substances 0.000 title claims abstract description 88
- 230000001681 protective effect Effects 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 230000008021 deposition Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011521 glass Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 33
- 238000007740 vapor deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 19
- 230000008569 process Effects 0.000 description 10
- 238000002161 passivation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, CD 바이어스를 감소시키기 위한 보호막 형성방법에 관한 것이다. 본 발명의 박막 트랜지스터 액정표시소자의 보호막 형성방법은, 액정으로부터 박막 트랜지스터를 보호하기 위해 상기 박막 트랜지스터가 형성된 유리기판의 전면 상에 형성하는 보호막 형성방법에 있어서, 서로 다른 식각 속도를 갖는 2 종류의 절연막을 순차적으로 증착하여 형성하되, 상부에 증착되는 상부 절연막은 그 하부의 하부 절연막 보다 식각 속도가 1.5 내지 2배 빠르게 되도록 증착하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of forming a protective film for reducing CD bias. The protective film forming method of the thin film transistor liquid crystal display device of the present invention is a protective film forming method which is formed on the entire surface of a glass substrate on which the thin film transistor is formed to protect the thin film transistor from liquid crystal. The insulating film is formed by sequentially depositing the upper insulating film deposited on the upper surface of the lower insulating film, characterized in that the deposition rate is deposited to be 1.5 to 2 times faster.
Description
본 발명은 박막트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, CD 바이어스를 감소시키기 위한 박막 트랜지스터 액정표시소자의 보호막 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of forming a protective film of a thin film transistor liquid crystal display device for reducing the CD bias.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소에 스위칭 소자로서 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 높은 화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 표시 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD having a thin film transistor (TFT) as a switching element in each pixel arranged in a matrix form is comparable to a CRT because of the advantages of having high-speed response characteristics and suitable for high pixel count. It is greatly contributing to realizing high screen quality, large size, and color.
이러한 TFT LCD는 통상 매트릭스 형태로 배열된 각 화소마다 TFT가 배열되어 있는 하부기판과, 컬러필터가 반복·배열된 상부기판이 소정 간격을 두고 대향하게 합착되고, 그들 사이의 공간에는 액정이 봉입된 형태를 이루고 있다.In such a TFT LCD, a lower substrate in which TFTs are arranged for each pixel arranged in a matrix form and an upper substrate in which color filters are repeated and arranged are bonded to face each other at predetermined intervals, and liquid crystal is enclosed in a space therebetween. Form.
도 1은 상기한 TFT LCD의 하부기판을 도시한 단면도로서, 도시된 바와 같이, 유리기판(1) 상에 게이트 전극(2)이 형성되어 있으며, 상기 게이트 전극(2)이 덮혀지도록 유리기판(1) 전면에는 SiON막으로된 게이트 절연막(3)이 도포되어 있다. 그리고, 게이트 전극(2) 상부의 게이트 절연막(3) 상에는 패턴의 형태로 반도체층(4)이 형성되어 있고, 이 반도체층(4) 상에는 소오스/드레인 전극(5a, 5b)이 형성되어 TFT가 구성되어져 있다.FIG. 1 is a cross-sectional view illustrating a lower substrate of the TFT LCD. As shown in the drawing, a gate electrode 2 is formed on a glass substrate 1, and a glass substrate is formed to cover the gate electrode 2. 1) A gate insulating film 3 made of a SiON film is coated on the entire surface. The semiconductor layer 4 is formed on the gate insulating film 3 on the gate electrode 2 in the form of a pattern. The source / drain electrodes 5a and 5b are formed on the semiconductor layer 4 to form a TFT. It is composed.
한편, 도시되지는 않았지만, 소오스/드레인 전극을 형성하기 이전에 반도체층 상에 에치 스톱퍼를 형성할 수도 있다.Although not shown, an etch stopper may be formed on the semiconductor layer before forming the source / drain electrodes.
계속해서, 유리기판(1)의 전면 상에는 액정으로부터 TFT를 보호하기 위한SiNX재질의 보호막(6)이 형성되어 있고, 이러한 보호막(6) 상에는 그의 내부에 형성된 콘택홀을 통해 TFT의 소오스 전극(5a)과 콘택되는 ITO 금속 재질의 화소 전극(7)이 형성되어 있다.Subsequently, a protective film 6 made of SiN X is formed on the entire surface of the glass substrate 1 to protect the TFT from liquid crystal, and the source electrode of the TFT is formed on the protective film 6 through a contact hole formed therein. A pixel electrode 7 made of ITO metal which is in contact with 5a) is formed.
한편, 상기와 같은 구조를 갖는 TFT LCD의 하부기판 제조시는 통상 소오스 전극을 노출시키는 콘택홀 형성을 위한 식각 공정과, 주변 영역에 배치되는 전극패드 부분을 노출시키기 위한 식각 공정을 동시에 실시하게 된다.Meanwhile, in manufacturing the lower substrate of the TFT LCD having the above structure, an etching process for forming a contact hole for exposing a source electrode and an etching process for exposing an electrode pad portion disposed in a peripheral area are performed at the same time. .
그런데, 일반적으로 전극패드 부분에는 게이트 절연막과 보호막이 덮혀져 있기 때문에, 상기 전극패드를 노출시키기 위해서는 상기 막들을 동시에 식각하게 되는데, 이 경우에는, SiON막의 식각 속도가 SiNX막의 식각 속도 보다 빠른 것에 기인하여 게이트 절연막은 정의 식각 프로파일을 갖고, 보호막은 게이트 절연막과 반대의 식각 프로파일을 갖게 된다.However, since the gate insulating film and the protective film are generally covered with the electrode pad portion, the films are simultaneously etched to expose the electrode pad. In this case, the etching rate of the SiON film is faster than that of the SiN X film. As a result, the gate insulating film has a positive etching profile, and the protective film has an etching profile opposite to that of the gate insulating film.
이에 따라, 보호막과 게이트 절연막의 테이퍼 각이 서로 반대가 되는 것에 기인하여 이러한 부분에 외부 회로 단자를 연결하게 되면, 신호 전달이 제대로 이루어지 않게 되는 문제점이 발생된다.Accordingly, due to the taper angles of the protective film and the gate insulating film being opposite to each other, connecting an external circuit terminal to such a portion causes a problem in that signal transmission is not properly performed.
따라서, 종래에는 보호막의 식각 프로파일이 게이트 절연막과 동일하게 정의 프로파일을 갖을 수 있도록, SiNX막의 증착 조건을 달리하여 2층의 절연막 구조로 보호막을 형성하는 방법이 실시되고 있으며, 이때, 각 절연막들의 증착 조건은 하기의 표 1과 같다.Therefore, in the related art, a method of forming a protective film in a two-layer insulating film structure by varying the deposition conditions of the SiN X film so that the etching profile of the protective film has the same positive profile as the gate insulating film is performed. Deposition conditions are shown in Table 1 below.
하기 표 1에서 하부 절연막과 상부 절연막에 대한 식각 속도는 상기 절연막들의 증착 조건과는 별개이며, 이러한 식각 속도는 HF와 NH4F 및 H2O가 6:30:64의 중량비(wt%)로 혼합되어져 있는 BOE 용액을 이용한 습식 식각 공정에서 측정된 결과이다.In Table 1, the etching rates for the lower insulating film and the upper insulating film are independent of the deposition conditions of the insulating films, and the etching rate is HF, NH 4 F and H 2 O in a weight ratio (wt%) of 6:30:64. This is the result measured in the wet etching process using the mixed BOE solution.
(표 1)Table 1
그러나, 상기와 같이 SiNX막을 그 증착 조건을 달리하여 2층의 절연막 구조로 보호막을 형성한 후에, BOE 용액을 사용하여 2층 구조의 보호막과 게이트 절연막을 동시에 식각하게 되면, 전술한 바와 같이, 보호막과 그 하부의 게이트 절연막의 식각 포로파일이 모두 정의 식각 프로파일을 갖도록 할 수는 있으나, 표 1에서와 같이 상부 절연막의 식각 속도가 하부 절연막의 식각 속도에 비해 4배 정도로 상당히 높기 때문에, 도 2에 도시된 바와 같이, 식각 프로파일이 대략 15°정도가 됨은 물론 CD(Critical Dimension) 바이어스(Bias), 즉, 실제 얻고자하는 패턴의양측에 여분으로 더 형성되는 패턴 폭이 양측 각각 4.5㎛ 정도가 됨으로써, 그 합이 9㎛ 정도가 되는 것에 기인하여 공정 마진을 확보하기가 어렵게 되는 문제점이 있었다.However, as described above, after the SiN X film is formed with a two-layer insulating film structure by varying its deposition conditions, the protective film and the gate insulating film of the two-layer structure are simultaneously etched using a BOE solution, as described above. Although the etching profile of both the passivation layer and the gate insulating layer below it may have a positive etching profile, as shown in Table 1, since the etching rate of the upper insulating layer is considerably higher than that of the lower insulating layer, FIG. As shown in FIG. 6, the etching profile is approximately 15 °, and the CD (Critical Dimension) bias, that is, the pattern width additionally formed on both sides of the pattern to be actually obtained is about 4.5 μm on each side. As a result, the sum is about 9 µm, which makes it difficult to secure process margins.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 보호막으로 사용되는 상부 절연막의 증착 압력을 변경시키는 것에 의해 상기 상부 절연막의 식각 속도가 하부 절연막의 식각 속도에 비해 1.5 내지 2배 정도가 되도록 함으로써, 보호막과 게이트 절연막을 동시에 식각하는 경우에 식각 프로파일에 대한 그 테이퍼 각은 증가되고, 반대로, CD 바이어스는 감소되도록 하는 TFT LCD의 보호막 형성방법을 제공하는데, 그 목적이 있다.Therefore, the present invention devised to solve the above problems, by changing the deposition pressure of the upper insulating film used as a protective film, the etching rate of the upper insulating film is about 1.5 to 2 times the etching rate of the lower insulating film. By providing a protective film forming method of a TFT LCD in which the taper angle with respect to an etching profile is increased when the protective film and the gate insulating film are simultaneously etched, on the contrary, the CD bias is reduced.
도 1은 종래 기술에 따른 박막 트랜지스터 액정표시소자의 단면 구조를 도시한 도면.1 is a cross-sectional structure of a thin film transistor liquid crystal display device according to the prior art.
도 2는 종래의 문제점을 설명하기 위한 사진.Figure 2 is a photograph for explaining the conventional problem.
도 3은 테이퍼 각에 따른 CD 바이어스의 변화를 설명하기 위한 도면.3 is a view for explaining a change in CD bias according to a taper angle.
도 4는 본 발명의 실시예에 따른 보호막 및 게이트 절연막의 적층막에 대한 식각 프로파일을 보여주는 사진.4 is a photograph showing an etching profile of a stacked layer of a protective layer and a gate insulating layer according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 절연막11 glass substrate 12 gate insulating film
13 : 하부 절연막 14 : 상부 절연막13 lower insulating film 14 upper insulating film
15 : 감광막15 photosensitive film
상기와 같은 목적을 달성하기 위한 본 발명의 TFT LCD의 보호막 형성방법은, 액정으로부터 TFT를 보호하기 위해 상기 TFT가 형성된 유리기판의 전면 상에 형성하는 보호막 형성방법에 있어서, 서로 다른 식각 속도를 갖는 2 종류의 절연막을 순차적으로 증착하여 형성하되, 상부에 증착되는 상부 절연막은 그 하부의 하부 절연막 보다 식각 속도가 1.5 내지 2배 빠르게 되도록 증착하는 것을 특징으로 한다.The protective film forming method of the TFT LCD of the present invention for achieving the above object, in the protective film forming method formed on the entire surface of the glass substrate on which the TFT is formed to protect the TFT from the liquid crystal, having a different etching rate Formed by depositing two kinds of insulating films in sequence, the upper insulating film deposited on the upper is characterized in that the etching rate is deposited so that 1.5 to 2 times faster than the lower insulating film of the lower.
본 발명에 따르면, 보호막으로 사용되는 상부 절연막의 증착 압력을 조절하여 그 식각 속도가 하부 절연막의 식각 속도에 비해 1.5 내지 2배가 되도록 함으로써, 식각 프로파일의 그 테이퍼 각은 증가시키고, 반면에, CD 바이어스는 감소시킬 수 있으며, 이에 따라, 공정 마진을 향상시킬 수 있다.According to the present invention, the taper angle of the etching profile is increased by adjusting the deposition pressure of the upper insulating film used as the protective film so that the etching rate is 1.5 to 2 times the etching rate of the lower insulating film, whereas the CD bias is increased. Can be reduced, thereby improving the process margin.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 테이퍼 각에 따른 CD BIAS의 변화를 설명하기 위한 도면으로서, 도시된 바와 같이, CD 바이어스(A)는 테이퍼 각(θ)이 감소됨에 따라 그 값이 증가된다. 여기서, 도면부호 11은 유리기판, 12는 게이트 절연막, 13은 하부 절연막, 14는 상부 절연막, 그리고, 15는 식각 마스크로 사용되는 감광막이다.3 is a view for explaining the change of the CD BIAS according to the taper angle. As shown in the drawing, the CD bias A increases as the taper angle θ decreases. Here, reference numeral 11 is a glass substrate, 12 is a gate insulating film, 13 is a lower insulating film, 14 is an upper insulating film, and 15 is a photoresist film used as an etching mask.
도 4는 본 발명의 실시예에 따른 보호막과 게이트 절연막에 대한 식각 프로파일을 보여주는 사진으로서, 보여지는 바와 같이, 상·하부 절연막으로된 보호막과 게이트 절연막의 테이퍼 각은 대략 45°정도이며, CD 바이어스는 종래 보다 짧은 1.5㎛ 정도이다.4 is a photograph showing an etching profile of the passivation layer and the gate insulating layer according to an embodiment of the present invention, as shown, the taper angle of the passivation layer and the gate insulating layer of the upper and lower insulating layer is approximately 45 degrees, CD bias It is about 1.5 micrometers shorter than before.
상기와 같은 결과를 얻기 위해 본 발명의 실시예에서는 보호막으로 사용되는 상부 절연막의 증착 압력을 종래와 다르게 하는데, 보호막으로 사용되는 하부 절연막과 상부 절연막의 증착 조건은 하기의 표 2에 도시된 바와 같다.In order to obtain the results as described above, the deposition pressure of the upper insulating film used as the protective film is different from the conventional method, and the deposition conditions of the lower insulating film and the upper insulating film used as the protective film are shown in Table 2 below. .
(표 2)Table 2
표 2에서 하부 절연막과 상부 절연막의 식각 속도는 종래와 마찬가지로 상기 절연막들의 증착 조건과는 별개이며, HF와 NH4F 및 H2O가 6:30:64의 중량비(wt%)로 혼합되어져 있는 BOE 용액을 이용한 습식 식각 공정에서 측정된 결과이다.In Table 2, the etching rates of the lower insulating film and the upper insulating film are separate from the deposition conditions of the insulating films as in the prior art, and HF, NH 4 F, and H 2 O are mixed in a weight ratio (wt%) of 6:30:64. This is the result measured in the wet etching process using the BOE solution.
여기서, 하부 절연막의 경우에는 종래와 동일한 증착 조건으로 증착하지만, 상부 절연막의 경우에는 종래와 비교해서 파워, 전극간의 거리, 및 소오스 가스의 양은 동일하게 하지만, 증착 압력은 종래 보다 작은 1,700∼1,900 mTorr 정도로 한다.Here, the lower insulating film is deposited under the same deposition conditions as in the prior art, while the upper insulating film has the same power, the distance between electrodes, and the amount of source gas as compared with the conventional one, but the deposition pressure is 1,700 to 1,900 mTorr, which is smaller than the conventional one. It is enough.
그런데, 상부 절연막의 증착 압력을 1,700∼1,900 mTorr 정도로 하게 되면, 상부 절연막의 식각 속도는 종래와는 달리 하부 절연막의 식각 속도에 비해 1.5 내지 2배 정도가 되기 때문에, 2층 구조의 보호막과 게이트 절연막을 동시에 식각하게 되면, 도 4에 도시된 바와 같이, 그 테이퍼 각은 종래의 테이퍼 각인 15° 보다는 큰 45°정도가 된다.However, when the deposition pressure of the upper insulating film is about 1,700 to 1,900 mTorr, since the etching speed of the upper insulating film is 1.5 to 2 times that of the lower insulating film, unlike the conventional method, the protective film and the gate insulating film of the two-layer structure When the etched at the same time, as shown in Figure 4, the taper angle is about 45 ° than the conventional taper angle of 15 °.
따라서, 전술한 바와 같이, CD 바이어스는 테이퍼 각에 의존하기 때문에, 본 발명의 실시예에 다른 식각 프로파일에서의 테이퍼 각이 종래 보다 큰 45°가 되는 것에 기인하여 CD 바이어스는 종래 보다 작은 치수인 1.5㎛ 정도로 감소하게 되고, 그 합은 3㎛ 정도가 된다.Therefore, as described above, since the CD bias depends on the taper angle, the CD bias is smaller than the conventional 1.5 because the taper angle in the etching profile according to the embodiment of the present invention is 45 ° larger than the conventional one. The thickness is reduced to about 탆, and the sum is about 3 탆.
그러므로, 2층 구조의 보호막을 형성하는 경우에, 상부 절연막의 증착 압력만을 변경시킴으로써, 테이퍼 각을 증가시키는 것에 의해 비교적 쉽게 CD 바이어스를 감소시킬 수 있게 되고, 이에 따라, 식각 공정에 의해 노출시키게 되는 전극패드와 TFT의 소오스/드레인 전극의 크기를 감소시킬 수 있는 등의 공정마진을 향상시킬 수 있게 된다.Therefore, in the case of forming the protective film of the two-layer structure, by changing only the deposition pressure of the upper insulating film, it is possible to reduce the CD bias relatively easily by increasing the taper angle, and thus exposed by the etching process. It is possible to improve process margins such as reducing the size of the source / drain electrodes of the electrode pad and the TFT.
이상에서와 같이, 본 발명은 두 개의 절연막을 적층시켜 보호막을 형성하는 경우에, 상부 절연막의 증착 압력을 변경시켜, 상기 상부 절연막의 식각 속도가 하부 절연막의 식각 속도에 비해 1.5 내지 2배 정도가 되도록 함으로써, 식각시의 테이퍼 각을 증가시킬 수 있는 것에 기인하여 CD 바이어스를 감소시킬 수 있으며, 이에 따라, 공정 마진을 향상시킬 수 있다.As described above, when the two insulating films are stacked to form a protective film, the deposition pressure of the upper insulating film is changed so that the etching rate of the upper insulating film is 1.5 to 2 times higher than the etching rate of the lower insulating film. By doing so, the CD bias can be reduced due to being able to increase the taper angle at the time of etching, thereby improving the process margin.
또한, CD 바이어스의 감소로 인하여 불투명의 소오스/드레인 전극의 크기를 감소시킬 수 있기 때문에, TFT LCD의 개구율도 향상시킬 수 있다.In addition, since the size of the opaque source / drain electrodes can be reduced due to the reduction of the CD bias, the aperture ratio of the TFT LCD can also be improved.
게다가, 전극 패드를 오픈시키기 위한 식각시에는 소오스/드레인 전극의 일부분을 오픈시키기 위한 콘택홀 형성 공정도 동시에 수행되는데, CD 바이어스의 감소로 인하여 이러한 부분에서의 화소 전극의 콘택 불량 및 데이터 라인의 오픈 불량을 방지할 수 있기 때문에, TFT LCD의 신뢰성도 향상시킬 수 있다.In addition, during the etching for opening the electrode pad, a contact hole forming process for opening a portion of the source / drain electrode is also performed simultaneously, and the contact of the pixel electrode and the opening of the data line in such a portion due to the reduction of the CD bias are performed. Since the defect can be prevented, the reliability of the TFT LCD can also be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202953A (en) * | 1987-02-19 | 1988-08-22 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH02273922A (en) * | 1989-04-17 | 1990-11-08 | Sanyo Electric Co Ltd | Formation of through hole |
| JPH0455802A (en) * | 1990-06-25 | 1992-02-24 | Victor Co Of Japan Ltd | Production of optical integrated circuit |
| JPH0685257A (en) * | 1992-09-02 | 1994-03-25 | Toshiba Corp | Manufacture of thin film transistor |
| JPH09197435A (en) * | 1996-01-17 | 1997-07-31 | Toshiba Corp | Liquid crystal display device and its production |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202953A (en) * | 1987-02-19 | 1988-08-22 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH02273922A (en) * | 1989-04-17 | 1990-11-08 | Sanyo Electric Co Ltd | Formation of through hole |
| JPH0455802A (en) * | 1990-06-25 | 1992-02-24 | Victor Co Of Japan Ltd | Production of optical integrated circuit |
| JPH0685257A (en) * | 1992-09-02 | 1994-03-25 | Toshiba Corp | Manufacture of thin film transistor |
| JPH09197435A (en) * | 1996-01-17 | 1997-07-31 | Toshiba Corp | Liquid crystal display device and its production |
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