KR100279265B1 - Protective film formation method of thin film transistor liquid crystal display device - Google Patents
Protective film formation method of thin film transistor liquid crystal display device Download PDFInfo
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- KR100279265B1 KR100279265B1 KR1019980045621A KR19980045621A KR100279265B1 KR 100279265 B1 KR100279265 B1 KR 100279265B1 KR 1019980045621 A KR1019980045621 A KR 1019980045621A KR 19980045621 A KR19980045621 A KR 19980045621A KR 100279265 B1 KR100279265 B1 KR 100279265B1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
Abstract
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, 박막 트랜지스터를 보호하기 위한 보호막 형성방법에 관한 것이다. 본 발명의 박막트랜지스터 액정표시소자의 보호막 형성방법은, 박막 트랜지스터가 형성되어진 유리기판의 전면 상에 상기 박막 트랜지스터를 액정으로부터 보호하기 위하여 SiN막재질의 보호막을 형성하는 박막 트랜지스터 액정표시소자의 보호막 형성방법으로서, 상기 SiN막은, 그 증착 시간은 51초, RF 파워는 1,600±100W, 전극간의 간격은 750±10mils, 반응 가스인 N2가스는 3,500±10sccm, NH3가스는 2,800±10sccm, SiH4가스는 350±10sccm으로 하는 증착 조건으로 형성하는 것을 특징으로 한다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of forming a protective film for protecting a thin film transistor. The protective film forming method of the thin film transistor liquid crystal display device according to the present invention comprises forming a protective film of a thin film transistor liquid crystal display device in which a protective film of SiN film is formed on the entire surface of the glass substrate on which the thin film transistor is formed to protect the thin film transistor from liquid crystal. As a method, the SiN film had a deposition time of 51 seconds, an RF power of 1,600 ± 100 W, an interval between electrodes of 750 ± 10 mils, a reaction gas of N 2 gas of 3,500 ± 10 sccm, NH 3 gas of 2,800 ± 10 sccm, SiH 4 The gas is formed under deposition conditions of 350 ± 10 sccm.
Description
본 발명은 박막트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, 박막 트랜지스터를 보호하기 위한 보호막 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of forming a protective film for protecting a thin film transistor.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소에 스위칭 소자로서 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 높은 화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 표시 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD having a thin film transistor (TFT) as a switching element in each pixel arranged in a matrix form is comparable to a CRT because of the advantages of having high-speed response characteristics and suitable for high pixel count. It is greatly contributing to realizing high screen quality, large size, and color.
이러한 TFT LCD는 통상 매트릭스 형태로 배열된 각 화소마다 TFT가 배열되어있는 하부기판과, 컬러필터가 반복·배열된 상부기판이 소정 간격을 두고 대향하게 합착되고, 그들 사이의 공간에는 액정이 봉입된 형태를 이루고 있다.In such a TFT LCD, a lower substrate in which TFTs are arranged in each pixel arranged in a matrix form and an upper substrate in which color filters are repeated and arranged are bonded to face each other at predetermined intervals, and liquid crystal is enclosed in a space therebetween. Form.
도 1은 상기한 TFT LCD의 하부기판을 도시한 단면도로서, 도시된 바와 같이, 유리기판(1) 상에 게이트 전극(2)이 형성되어 있으며, 이러한 게이트 전극(2)이 덮혀지도록 유리기판(1) 전면에는 게이트 절연막(3)이 도포되어 있고, 상기 게이트전극(2) 상부의 게이트 절연막(3) 상에는 패턴의 형태로 반도체층(4)이 형성되어 있으며, 이 반도체층(4) 상에는 소오스/드레인 전극(5a, 5b)이 형성되어 TFT가 구성되어져 있다.FIG. 1 is a cross-sectional view illustrating a lower substrate of the TFT LCD. As illustrated, a gate electrode 2 is formed on a glass substrate 1, and a glass substrate (2) is covered so that the gate electrode 2 is covered. 1) A gate insulating film 3 is coated on the entire surface, and a semiconductor layer 4 is formed on the gate insulating film 3 on the gate electrode 2 in a pattern form, and a source is formed on the semiconductor layer 4. Drain electrodes 5a and 5b are formed to constitute a TFT.
한편, 도시되지는 않았지만, 소오스/드레인 전극(5a, 5b)을 형성하기 전에 반도체층(4) 상에 상기 반도체층(4)을 보호하기 위한 에치 스톱퍼를 형성할 수도 있다.Although not shown, an etch stopper for protecting the semiconductor layer 4 may be formed on the semiconductor layer 4 before the source / drain electrodes 5a and 5b are formed.
또한, 유리기판(1)의 전면 상에는 액정으로부터 TFT를 보호하기 위한 보호막(6)이 형성되어 있고, 이러한 보호막(6) 상에는 그의 내부에 형성된 콘택홀을 통해 TFT의 소오스 전극(5a)과 콘택되는 ITO(Indium Tin Oxide) 재질의 화소 전극(7)이 형성되어 있다.In addition, a protective film 6 is formed on the entire surface of the glass substrate 1 to protect the TFT from liquid crystal, and the protective film 6 is in contact with the source electrode 5a of the TFT through a contact hole formed therein. A pixel electrode 7 made of indium tin oxide (ITO) is formed.
상기에서, 보호막(6)은 일반적으로 SiN막으로 이루어지며, 이러한 SiN막은 통상 PECVD법으로 형성하고, 여기서, 상기 SiN막의 증착 조건은 하기의 표 1에 나타낸 바와 같다.In the above, the protective film 6 is generally made of a SiN film, and this SiN film is usually formed by PECVD, where the deposition conditions of the SiN film are as shown in Table 1 below.
(표 1)Table 1
그러나, 상기와 같은 방법으로 형성되는 SiN막은 그 증착 두께가 하부 층의 토폴로지(Topology)에 의해 의존되기 때문에, 예컨데, 하부 층의 토폴로지가 나쁠 경우에는 상기 SiN막의 증착 두께가 모든 부분에서 균일하게 유지되지 못하게 되고, 특히, 도 2에서 보여지는 바와 같이, 데이터 라인(1), 즉, 소오스/드레인 전극의 측부 부분(A)에서의 SiN막(2)의 두께가 다른 부분에서의 두께 보다 얇게 되는 것에 기인하여, 후속 공정, 예컨데, ITO 금속막을 식각하여 화소전극을 형성하는 공정시에, 상대적으로 얇게 증착되어 있는 SiN막 부분으로 식각액이 침투됨으로써, 데이터 라인의 측부 및 그 하부의 또 다른 금속막들이 상기 식각액에 의해 손상을 받게 되어, 결과적으로는, TFT LCD의 전기적 특성은 물론 신뢰성이 저하되는 문제점이 있었다.However, since the deposition thickness of the SiN film formed by the above method depends on the topology of the lower layer, for example, if the topology of the lower layer is bad, the deposition thickness of the SiN film is kept uniform in all parts. In particular, as shown in FIG. 2, the thickness of the SiN film 2 in the side portion A of the data line 1, that is, the source / drain electrode becomes thinner than the thickness in other portions. Due to this, in the subsequent process, for example, in the process of etching the ITO metal film to form the pixel electrode, the etchant penetrates into the relatively thinly deposited SiN film portion, whereby another metal film on the side of the data line and the lower portion thereof. They are damaged by the etchant, and as a result, there is a problem that the reliability as well as the electrical characteristics of the TFT LCD.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 하부층의 토폴로지에 관계없이 균일한 막 두께를 유지할 수 있도록 하는 TFT LCD의 보호막 형성방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a protective film of a TFT LCD which can maintain a uniform film thickness regardless of the topology of an underlying layer.
도 1은 종래 기술에 따른 박막 트랜지스터 액정표시소자의 단면 구조를 도시한 도면.1 is a cross-sectional structure of a thin film transistor liquid crystal display device according to the prior art.
도 2는 종래의 문제점을 설명하기 위한 사진.Figure 2 is a photograph for explaining the conventional problem.
도 3은 본 발명의 실시예에 따라 형성된 보호막을 보여주는 사진.3 is a photograph showing a protective film formed according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 데이터 라인 12 : SiN막11: data line 12: SiN film
상기와 같은 목적을 달성하기 위한 본 발명의 TFT LCD의 보호막 형성방법은, TFT가 형성되어진 유리기판의 전면 상에 상기 TFT를 액정으로부터 보호하기 위하여 SiN막 재질의 보호막을 형성하는 TFT LCD의 보호막 형성방법으로서, 상기 SiN막은, 증착 시간은 51초, RF 파워는 1,600±100W, 전극간의 간격은 750±10mils, 반응 가스인 N2가스는 3,500±10sccm, NH3가스는 2,800±10sccm, SiH4 가스는 350±10sccm으로 하는 증착 조건으로 형성하는 것을 특징으로 한다.The protective film forming method of the TFT LCD of the present invention for achieving the above object, the protective film formation of the TFT LCD to form a protective film of SiN film material to protect the TFT from the liquid crystal on the front surface of the glass substrate on which the TFT is formed As a method, the SiN film has a deposition time of 51 seconds, an RF power of 1,600 ± 100 W, an interval between electrodes of 750 ± 10 mils, a reaction gas of N 2 gas of 3,500 ± 10 sccm, NH 3 gas of 2,800 ± 10 sccm, and SiH4 gas of It is characterized by forming under deposition conditions of 350 ± 10sccm.
본 발명에 따르면, SiN막의 증착 압력을 최적화시키는 것에 의해, 상기 SiN막의 스텝 커버리지를 개선시킬 수 있으며, 이에 따라, TFT LCD의 전기적 특성 및 신뢰성의 저하를 방지할 수 있다.According to the present invention, the step coverage of the SiN film can be improved by optimizing the deposition pressure of the SiN film, whereby the degradation of the electrical characteristics and the reliability of the TFT LCD can be prevented.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
우선, 본 발명의 실시예에서는 SiN막의 증착 두께가 모든 부분에서 균일하게 되도록 하기 위하여, 그 증착 조건을 하기의 표 2에서와 같은 조건으로 수행한다.First, in the embodiment of the present invention, in order to make the deposition thickness of the SiN film uniform in all parts, the deposition conditions are performed under the conditions shown in Table 2 below.
(표 2)Table 2
표 2에서, 본 발명에서는 SiN막의 증착 압력을 종래 보다 낮은 1,500±100mTorr로 수행하는데, 이 경우에, 실리콘과 수소의 결합(Si-H)비대 질소와 수소의 결합(N-H)비가 종래에는 29 : 16인데 반하여, 그 비를 21 : 18 정도로 변경시킬 수 있게 되고, 이에 따라, SiN막의 스텝 커버리지를 향상시킬 수 있게 된다.In Table 2, in the present invention, the deposition pressure of the SiN film is performed at 1,500 ± 100 mTorr, which is lower than that of the conventional art. In this case, the bond (Si-H) ratio of silicon and hydrogen (NH) ratio is 29: While the ratio is 16, the ratio can be changed to about 21:18, thereby improving the step coverage of the SiN film.
즉, 실리콘과 수소의 결합비대 질소와 수소의 결합비는 SiN막의 스텝 커버리지에 대하여 매우 중요한 변수로 작용하게 되는데, 일반적으로, 증착 압력을 종래와 유사하게 2,500±100 mTorr 정도의 높은 압력으로 하게 되면, 실리콘과 수소의 결합이 늘어나게 됨으로써, 증착된 SiN막에 대하여 당업자에게 공지되어 있는 FTIR 장비를 사용하여 수소 결합비, 예컨데, 상기 실리콘과 수소간의 결합비와 질소와 수소간의 결합비 사이의 비율이 적당치가 못하게 되어, 구조적으로는 치밀하지가 못하게 되고, 이에 따라, 증착된 SiN막의 두께는 모든 부분에서 균일하게 유지되지 못한다.In other words, the bonding ratio between silicon and hydrogen is a very important variable for the step coverage of the SiN film. In general, when the deposition pressure is as high as 2,500 ± 100 mTorr, similar to the conventional method, As the bond between silicon and hydrogen increases, the hydrogen bonding ratio, ie, the ratio between the bonding ratio between silicon and hydrogen and the bonding ratio between nitrogen and hydrogen, is increased using FTIR equipment known to those skilled in the art for the deposited SiN film. Inappropriate values, and structurally less dense, therefore, the thickness of the deposited SiN film is not kept uniform in all parts.
또한, 증착 압력을 1,500±100 mTorr 이하로 낮추는 경우에는, 장비상의 문제점이 발생됨은 물론 실리콘과 수소의 결합이 감소하게 되어 절연막의 막 특성,즉, 절연막의 유전률이 적절하게 유지되지 못하게 됨으로써, 결과적으로는, TFT의 전기적 특성을 저하시키게 된다.In addition, when the deposition pressure is lowered to 1,500 ± 100 mTorr or less, equipment problems occur and the bond between silicon and hydrogen is reduced, so that the film characteristics of the insulating film, that is, the dielectric constant of the insulating film are not maintained properly, This lowers the electrical characteristics of the TFT.
이에 반하여, 본 발명의 실시예와 같이 SiN막의 증착 조건들을 종래와 동일하게 하되, 증착 압력은 1,500±100 mTorr 정도로 하게 되면, 전술한 바와 같이, 실리콘과 수소간의 결합비대 질소와 수소간의 결합비가 21 : 18 정도로 비슷한 비율을 갖게 되고, 이러한 비율을 갖는 SiN막은 구조적으로 매우 치밀하게 됨으로써, SiN막은 하부 층의 토폴로지에 상관없이 모든 부분에서 균일한 막 두께를 갖게 된다.On the contrary, as in the embodiment of the present invention, the deposition conditions of the SiN film are the same as before, but the deposition pressure is about 1,500 ± 100 mTorr. As described above, the bonding ratio between silicon and hydrogen is 21 and the bonding ratio between nitrogen and hydrogen is 21. The ratio is about 18: SiN film having such a ratio is structurally very dense, so that the SiN film has a uniform film thickness in all parts irrespective of the topology of the underlying layer.
따라서, 본 발명의 실시예와 같은 증착 조건으로 SiN막을 형성하게 되면, 도 3에서 보여지는 바와 같이, SiN막(12)이 균일한 두께를 유지하기 때문에, 후속공정시에 테이터 라인(11)이 식각액에 의해 손상되는 것을 방지할 수 있게 되고, 이에 따라, TFT LCD의 전기적 특성 및 신뢰성의 저하를 방지할 수 있게 된다.Therefore, when the SiN film is formed under the same deposition conditions as in the embodiment of the present invention, as shown in FIG. 3, since the SiN film 12 maintains a uniform thickness, the data line 11 is formed during the subsequent process. It can be prevented from being damaged by the etchant, and therefore, it is possible to prevent the degradation of the electrical characteristics and the reliability of the TFT LCD.
한편, 본 발명의 실시예에서는 상기와 같은 증착 조건으로 SiN막을 증착하되, 증착·완료된 SiN막의 굴절율이 대략 1.0±0.3 정도가 되도록하여 막 특성의 저하가 발생되지 않도록 한다.Meanwhile, in the embodiment of the present invention, the SiN film is deposited under the deposition conditions as described above, so that the refractive index of the deposited and completed SiN film is approximately 1.0 ± 0.3 so as not to deteriorate the film properties.
이상에서와 같이, 본 발명은 실리콘과 수소간의 결합비대 질소와 수소간의 결합비가 비슷하게 되는 증착 압력으로 SiN막을 형성하기 때문에, 구조적으로 치밀하게 할 수 있는 것에 기인하여 하부 토폴로지에 관계없이 모든 부분에서 균일한 막 두께를 유지시킬 수 있고, 이에 따라, 후속 공정에서 하부 금속 막들이 식각액에 의해 손상되어 데이터 라인, 또는, 화소전극의 오픈 등과 결함이 발생되는 것을 방지할 수 있기 때문에, TFT LCD의 전기적 특성 및 신뢰성을 향상시킬 수 있다.As described above, since the present invention forms the SiN film at a deposition pressure at which the bonding ratio between silicon and hydrogen is similar, the bonding ratio between nitrogen and hydrogen is uniform in all parts irrespective of the underlying topology due to the structural compactness. It is possible to maintain a film thickness, thereby preventing the lower metal films from being damaged by the etchant in the subsequent process, thereby preventing defects such as opening of data lines or pixel electrodes, and the like. And reliability can be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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