KR20010004016A - Method of manufacturing TFT-LCD - Google Patents
Method of manufacturing TFT-LCD Download PDFInfo
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- KR20010004016A KR20010004016A KR1019990024601A KR19990024601A KR20010004016A KR 20010004016 A KR20010004016 A KR 20010004016A KR 1019990024601 A KR1019990024601 A KR 1019990024601A KR 19990024601 A KR19990024601 A KR 19990024601A KR 20010004016 A KR20010004016 A KR 20010004016A
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims abstract description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 42
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 30
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 12
- 229910017604 nitric acid Inorganic materials 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000011259 mixed solution Substances 0.000 description 7
- 239000002253 acid Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- -1 accordingly Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
- G02F1/13685—Top gates
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- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 박막 트랜지스터 액정표시소자에 관한 것으로, 보다 상세하게는,탑 ITO 구조의 박막 트랜지스터 어레이 기판을 제조함에 있어서, ITO 에천트에 의해 데이터 라인이 손상되는 것을 방지하기 위한 박막 트랜지스터 액정표시소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to manufacturing a thin film transistor array substrate having a top ITO structure, wherein a thin film transistor liquid crystal display device is used to prevent data lines from being damaged by an ITO etchant. It relates to a manufacturing method.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자 (Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소마다 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT-LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 화면의 고화질화, 대형화 및 컬러화 등을 실현하고 있다.Liquid crystal displays (hereinafter, LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, TFT-LCDs equipped with thin film transistors (TFTs) for each pixel arranged in a matrix form have high speed response characteristics and are suitable for high pixel numbers, so that the screen quality comparable to that of CRTs can be improved. Larger and more colorful are realized.
이러한 TFT-LCD는 TFT 및 화소전극이 형성된 TFT 어레이 기판과, 컬러필터 및 상대전극이 형성된 컬러필터 기판이 액정층의 개재하에 합착된 구조이다.Such a TFT-LCD has a structure in which a TFT array substrate on which a TFT and a pixel electrode are formed, and a color filter substrate on which a color filter and a counter electrode are formed are bonded together through a liquid crystal layer.
여기서, TFT 어레이 기판의 제조 공정을 단순화시키는 것은, 즉, 포토 공정의 수를 줄이는 것은 제조비용 측면에서 TFT-LCD의 상용화에 크게 영향을 미친다. 따라서, 포토 공정의 수를 감소시키기 위한 여러 가지 구조들이 제안되고 있으며, 한 예로, ITO 금속막으로 이루어진 화소전극을 최상부에 배치시키는 탑 ITO 구조는 5단계의 포토 공정에 의해 제작되기 때문에 6 또는 7단계의 포토 공정을 요구하는 통상의 TFT 어레이 기판의 제조 공정 보다 그 제조공정의 단순화 및 제조비용의 절감 효과를 얻을 수 있다.Here, simplifying the manufacturing process of the TFT array substrate, that is, reducing the number of photo processes greatly affects the commercialization of the TFT-LCD in terms of manufacturing cost. Therefore, various structures have been proposed to reduce the number of photo processes. For example, a top ITO structure in which a pixel electrode made of an ITO metal film is disposed on the top thereof is manufactured by a five-step photo process, so that 6 or 7 It is possible to simplify the manufacturing process and reduce the manufacturing cost than the manufacturing process of the conventional TFT array substrate which requires the photo process of the step.
도 1은 종래 기술에 따른 탑 ITO 구조의 TFT 어레이 기판을 도시한 단면도로서, 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a TFT array substrate having a top ITO structure according to the prior art, which will be described below.
먼저, 유리기판(1) 상에 게이트 라인(2)이 형성되고, 이를 덮도록 유리기판(1)의 전면 상에 게이트 절연막(3)이 도포된다. 그런다음, 비도핑된 비정질실리콘층으로 이루어진 반도체층(4)이 상기 게이트 전극(2) 상부의 게이트 절연막(3) 부분 상에 형성되며, 상기 반도체층(4) 상에 도핑된 비정질실리콘층으로 이루어진 오믹층(5)이 형성된다. 이어서, 소오스/드레인 전극(6a, 6b)을 포함하는 데이터 라인(도시안됨)이 형성되고, 이 결과로, TFT(10)가 구성된다.First, a gate line 2 is formed on the glass substrate 1, and a gate insulating film 3 is coated on the entire surface of the glass substrate 1 so as to cover it. Then, a semiconductor layer 4 composed of an undoped amorphous silicon layer is formed on a portion of the gate insulating film 3 above the gate electrode 2, and is a doped amorphous silicon layer on the semiconductor layer 4. An ohmic layer 5 is formed. Subsequently, a data line (not shown) including the source / drain electrodes 6a and 6b is formed, and as a result, the TFT 10 is constructed.
계속해서, TFT(10)가 보호되도록, 상기 결과물의 상부에 보호막(11)이 도포되고, 상기 보호막(11)에는 공지된 식각 공정을 통해 TFT(10)의 소오스 전극(6a)을 노출시키는 콘택홀(12)이 형성된다. 그리고나서, 상기 보호막(11) 상에 ITO 금속막이 증착되고, 이러한 ITO 금속막이 식각되어, 상기 콘택홀(12)을 통해 소오스 전극(6a)과 콘택되는 화소전극(13)이 형성된다.Subsequently, a protective film 11 is applied to the upper portion of the resultant so that the TFT 10 is protected, and the contact for exposing the source electrode 6a of the TFT 10 to the protective film 11 through a known etching process. The hole 12 is formed. Then, an ITO metal film is deposited on the protective film 11, and the ITO metal film is etched to form a pixel electrode 13 contacting the source electrode 6a through the contact hole 12.
그러나, 상기와 같은 탑 ITO 구조의 TFT 어레이 기판의 제조시에는, 화소전극을 형성하기 위한 ITO 금속막의 식각시에, 상기 ITO 금속막을 식각하기 위하여 사용되는 식각 용액(이하, ITO 에천트라 칭함)에 의해, 도 1에 도시된 바와 같이, 소오스/드레인 전극(6a, 6b)을 포함한 데이터 라인이 손상됨으로써, 심한 경우에, 데이터 라인의 오픈 불량이 발생하게 되는 문제점이 있다.However, in manufacturing a TFT array substrate having a top ITO structure as described above, an etching solution (hereinafter referred to as an ITO etchant) used to etch the ITO metal film during etching of the ITO metal film for forming the pixel electrode. As a result, as illustrated in FIG. 1, when the data line including the source / drain electrodes 6a and 6b is damaged, there is a problem that an open failure of the data line occurs in severe cases.
자세하게, 소오스/드레인 전극을 포함한 데이터 라인은, 통상, Al 금속막, 또는, 이를 기본으로 하는 Mo/Al/Mo의 적층 구조로 형성되는데, 상기 Al 금속막은 ITO 에천트로 사용되는 강산, 예를들어, 염산(HCl)과 질산(HNO3)의 혼합 용액에 매우 취약한 단점이 있다. 또한, 보호막의 형성시에는 하부층의 표면 단차로 인하여, 그 스텝 커버리지 불량이 발생되기 때문에, 데이터 라인의 일부분이 보호막으로 덮히지 않는 현상이 발생하게 되고, 아울러, 보호막의 증착시에는 그 내부에 파티클이나, 스트레스에 의한 크랙이 발생하게 된다.In detail, a data line including a source / drain electrode is usually formed of an Al metal film or a stacked structure of Mo / Al / Mo based thereon, wherein the Al metal film is a strong acid, for example, used as an ITO etchant. However, there is a disadvantage that is very vulnerable to a mixed solution of hydrochloric acid (HCl) and nitric acid (HNO 3 ). In addition, when the protective film is formed, the step coverage defect occurs due to the surface step of the lower layer, so that a part of the data line is not covered with the protective film, and when the protective film is deposited, the particles are formed therein. However, cracks are caused by stress.
그런데, 보호막을 형성한 후에, ITO 공정을 수행하게 되면, ITO 금속막에 대한 식각 공정이 수행되는 동안, 보호막으로 덮히지 않고 노출되어 있는 데이터 라인 부분이 ITO 에천트에 의해 손상되는 문제점이 발생되며, 아울러, 보호막 내에서 발생된 파티클 또는 크랙을 통해 ITO 에천트가 데이터 라인으로 침투됨으로써, 데이터 라인의 손상이 발생하게 된다.However, when the ITO process is performed after the protective film is formed, a problem occurs that the exposed data line part is not covered by the protective film and is damaged by the ITO etchant during the etching process of the ITO metal film. In addition, the ITO etchant penetrates into the data line through particles or cracks generated in the passivation layer, thereby causing damage to the data line.
이 결과, ITO 에천트에 의한 손상으로 인하여, 데이터 라인의 특성이 저하되고, 심한 경우에는 데이터 라인의 오픈 불량이 발생하게 됨으로써, TFT 어레이 기판의 제조수율에 치명적인 악영향을 미치게 된다.As a result, due to the damage caused by the ITO etchant, the characteristics of the data line are degraded and, in severe cases, the open defect of the data line is generated, which has a fatal adverse effect on the production yield of the TFT array substrate.
한편, ITO 에천트에 의한 데이터 라인의 손상을 방지하기 위하여, 염산과 질산으로 이루어진 강산 계열의 혼합 용액 대신에, 상기 혼합 용액에 비해 약산인 염산과 초산(CH3COOH)의 혼합 용액을 이용하는 방법도 실시되고 있으나, 이 방법은, 데이터 라인의 손상을 감소시킬 수 있다는 장점은 있지만, 염산과 질산의 혼합 용액을 이용하는 경우 보다 식각 시간이 길다는 단점이 있기 때문에, 장비 운영 능력 측면에서 그 적용이 어려운 문제점이 있다.On the other hand, in order to prevent damage to the data line by the ITO etchant, a method of using a mixed solution of hydrochloric acid and acetic acid (CH 3 COOH) which is weak acid compared to the mixed solution instead of the mixed solution of the strong acid series consisting of hydrochloric acid and nitric acid Although this method has the advantage of reducing the damage of the data line, the method has a disadvantage in that the etching time is longer than using a mixed solution of hydrochloric acid and nitric acid, so the application in terms of equipment operation ability There is a difficult problem.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, ITO 에천트에 의한 데이터 라인의 손상을 방지할 수 있는 TFT-LCD의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a TFT-LCD which can prevent damage to a data line caused by an ITO etchant.
도 1은 종래 탑 ITO 구조의 박막 트랜지스터 어레이 기판을 도시한 단면도.1 is a cross-sectional view showing a thin film transistor array substrate of a conventional top ITO structure.
도 2는 본 발명의 실시예에 따라 제작된 탑 ITO 구조의 박막 트랜지스터 어레이 기판을 도시한 단면도.2 is a cross-sectional view showing a thin film transistor array substrate having a top ITO structure manufactured according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : 유리기판 2 : 게이트 라인1: glass substrate 2: gate line
3 : 게이트 절연막 4 : 반도체층3: gate insulating film 4: semiconductor layer
5 : 오믹층 6a : 소오스 전극5: ohmic layer 6a: source electrode
6b : 드레인 전극 10 : 박막 트랜지스터6b: drain electrode 10: thin film transistor
11 : 보호막 12 : 콘택홀11: protective film 12: contact hole
13 : 화소전극13: pixel electrode
상기와 같은 목적을 달성하기 위한 본 발명의 TFT-LCD의 제조방법은, 절연성 기판 상에 수직 교차하는 수 개의 게이트 라인들 및 데이터 라인들과, 상기 게이트 라인과 데이터 라인의 교차부에 배치되며, 게이트 전극과 반도체층 및 소오스/드레인 전극을 포함하는 TFT를 형성하는 단계; 상기 결과물의 상부에 보호막을 도포하고, 상기 보호막의 소정 부분을 선택적으로 식각하여 상기 TFT의 소오스 전극을 노출시키는 콘택홀을 형성하는 단계; 상기 보호막 상에 ITO 금속막을 증착하는 단계; 및 상기 ITO 금속막을 식각하여, 상기 TFT의 소오스 전극과 콘택하는 화소전극을 형성하는 단계를 포함하여 이루어지는 TFT-LCD의 제조방법에 있어서, 상기 ITO 금속막은 비정질의 결정 구조를 갖도록 상온에서 증착하는 것을 특징으로 한다.The TFT-LCD manufacturing method of the present invention for achieving the above object is disposed on the intersection of the gate line and the data line, and several gate lines and data lines perpendicularly intersecting on the insulating substrate, Forming a TFT comprising a gate electrode and a semiconductor layer and a source / drain electrode; Applying a protective film over the resultant, and selectively etching a predetermined portion of the protective film to form a contact hole exposing the source electrode of the TFT; Depositing an ITO metal film on the protective film; And etching the ITO metal film to form a pixel electrode in contact with the source electrode of the TFT, wherein the ITO metal film is deposited at room temperature to have an amorphous crystal structure. It features.
본 발명에 따르면, ITO 금속막을 증착하되, 그 결정 구조가 비정질 상태가 되도록 함으로써, ITO 금속막의 식각 속도를 증대시킬 수 있으며, 이에 따라, ITO 에천트로서 Al 금속막에 미치는 영향이 적은 염산과 초산의 혼합 용액을 이용하면서도, ITO 금속막에 대한 식각 시간을 단축시킬 수 있다.According to the present invention, by depositing the ITO metal film, but the crystal structure is in an amorphous state, it is possible to increase the etching rate of the ITO metal film, accordingly, hydrochloric acid and acetic acid with less effect on the Al metal film as ITO etchant While using a mixed solution of, the etching time for the ITO metal film can be shortened.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
ITO 금속막은 인듐 산화막(In2O3)에 주석(Sn)을 도핑하여, 그 케리어 농도를 증가시킨 금속막이다. 일반적으로, 200℃ 이상의 온도에서 증착된 결정질의 ITO 금속막은 Sn4+가 주된 케리어의 역할을 하기 때문에, 그 자체로 전도성을 갖게 되지만, 상온에서 증착되는 ITO 금속막은 비정질의 ITO 금속막은 산소 공공(Oxygen Vacancy)이 주된 케리어의 역할을 하기 때문에, 그 자체로는 전도성이 부족하며, 특히, 높은 비저항을 나타내게 된다.The ITO metal film is a metal film obtained by doping tin (Sn) to an indium oxide film (In 2 O 3 ) to increase its carrier concentration. In general, the crystalline ITO metal film deposited at a temperature of 200 ° C. or more has conductivity by itself since Sn 4+ plays a major carrier, but the ITO metal film deposited at room temperature has an oxygen vacancies. Oxygen Vacancy) acts as a major carrier, and thus in itself lacks conductivity, and in particular, exhibits high specific resistance.
그런데, 비정질의 ITO 금속막은 높은 비저항을 갖는데 반하여, 결정질 ITO 금속막에 비해, 대략 4배 정도 빠른 식각 속도를 나타낸다.By the way, while the amorphous ITO metal film has a high specific resistance, it exhibits an etching rate about 4 times faster than the crystalline ITO metal film.
따라서, 본 발명의 실시예에서는 ITO 금속막의 증착 공정을 상온에서 수행하여, 후속에서 진행되는 ITO 금속막의 식각 속도를 증가시킴으로써, ITO 에천트에 의해 데이터 라인이 손상되는 것을 방지한다.Therefore, in the embodiment of the present invention, the deposition process of the ITO metal film is performed at room temperature, thereby increasing the etching rate of the ITO metal film which is subsequently performed, thereby preventing the data line from being damaged by the ITO etchant.
자세하게, 본 발명의 실시예에 따른 ITO 금속막의 증착 조건은 다음과 같다.In detail, the deposition conditions of the ITO metal film according to the embodiment of the present invention are as follows.
ITO 금속막의 증착 챔버 내에 온도는 상온, 즉, 25℃로 유지하고, 챔버 내의 압력은 0.3∼1.8Pa로 유지하며, 전력은 3.5∼3.9KW로 유지하고, 그리고, 아르곤 가스의 유량은 90∼110SCCM, 산소 가스의 유량은 3.6∼7.2SCCM 정도로 한다. 여기서, 증착 온도를 상온으로 유지시키는 것은, 전술한 바와 같이, ITO 금속막의 비정질화를 통해 식각 속도의 향상을 얻기 위함이며, 산소 가스의 유량을 1.2SCCM 정도로 하는 종래의 경우 보다 그 유량을 증가시킨 것은 비정질 ITO 금속막의 경우에는 산소 공공이 주된 케리어이기 때문에, 비저항을 낮추기 위함이다.The temperature in the deposition chamber of the ITO metal film is kept at room temperature, that is, 25 ° C., the pressure in the chamber is maintained at 0.3 to 1.8 Pa, the power is maintained at 3.5 to 3.9 KW, and the flow rate of argon gas is 90 to 110 SCCM. , The flow rate of oxygen gas is about 3.6 to 7.2 SCCM. Here, maintaining the deposition temperature at room temperature is to obtain an improvement in the etching rate through the amorphousization of the ITO metal film as described above, and the flow rate of the oxygen gas is increased to 1.2 SCCM as in the conventional case. This is because the oxygen vacancies are the main carrier in the case of the amorphous ITO metal film, so as to lower the specific resistance.
다음으로, 비정질의 ITO 금속막에 대한 식각 공정을 살펴보면 다음과 같다.Next, the etching process for the amorphous ITO metal film is as follows.
우선, 종래에는 염산과 질산 및 물이 20:1:10의 부피비(vol%)로 혼합되어진 ITO 에천트를 이용해서, 3회에 걸쳐 각각 30∼43초, 30∼43초, 30∼44초 결정질의 ITO 금속막에 대한 식각 공정을 수행하거나, 또는, 염산과 초산 및 물이 22:6:72의 중량비(wt%)로 혼합되어진 ITO 에천트를 이용해서, 3회에 걸쳐 각각 70∼90초 동안 결정질의 ITO 금속막에 대한 식각 공정을 수행하고 있다.First, conventionally, ITO etchant in which hydrochloric acid, nitric acid, and water are mixed in a volume ratio of 20: 1: 10 (vol%) is used for 30 times, 43 seconds, 30 seconds, 43 seconds, 30 seconds, 44 seconds respectively. Etching the crystalline ITO metal film, or using an ITO etchant in which hydrochloric acid, acetic acid and water are mixed in a weight ratio of 22: 6: 72 (wt%), each of 70 to 90 three times. The etching process is performed on the crystalline ITO metal film for a second.
그러나, 염산과 질산으로 이루어진 ITO 에천트는 ITO 금속막을 식각하는 동안 데이터 라인의 재질인 Al 금속막을 심하게 손상시키기 때문에, 이 결과로, 데이터 라인의 오픈 불량을 유발하게 된다. 이에 반해, 염산과 초산으로 이루어진 ITO 에천트는 Al 금속막을 손상시키게 되는 정도는 적지만, 식각 속도가 느리다는 단점이 있다.However, since the ITO etchant consisting of hydrochloric acid and nitric acid severely damages the Al metal film, which is the material of the data line, during etching of the ITO metal film, this results in an open defect of the data line. On the other hand, ITO etchant consisting of hydrochloric acid and acetic acid is small enough to damage the Al metal film, but the etching rate is slow.
그런데, 비정질의 ITO 금속막은 결정질의 ITO 금속막에 비해 그 식각 속도가 빠르기 때문에, 본 발명의 실시예에서는 Al 금속막을 손상시키는 정도가 큰 염산과 질산으로 이루어진 ITO 에천트 대신에 상대적으로 약산인 염산과 초산으로 이루어진 ITO 에천트, 예를들어, 염산:초산:물이 25:5:70의 중량비로 혼합된어진 혼합 용액을 사용하여, 20∼50℃의 온도에서 3회 걸쳐 각각 20∼40초 동안 비정질의 ITO 금속막에 대한 식각 공정을 수행한다.However, since the amorphous ITO metal film has a faster etching rate than the crystalline ITO metal film, hydrochloric acid, which is a relatively weak acid instead of an ITO etchant composed of hydrochloric acid and nitric acid, which has a high degree of damaging the Al metal film in the embodiment of the present invention ITO etchant consisting of and acetic acid, for example, 20-40 seconds each over three times at a temperature of 20-50 ° C., using a mixed solution in which hydrochloric acid: acetic acid: water is mixed in a weight ratio of 25: 5: 70. During the etching process for the amorphous ITO metal film.
여기서, 염산과 초산으로 이루어진 ITO 에천트를 이용한 ITO 금속막의 식각시, 그 식각 시간은 종래의 경우에는 전체적으로 210∼270초 정도가 소요되지만, 본 발명의 실시예의 경우에는 전체적으로 60∼120초 정도가 소요되기 때문에, 염산과 초산으로 이루어진 ITO 에천트를 사용함에도 불구하고, 그 식각 시간은 염산과 질산으로 이루어진 ITO 에천트를 이용하는 경우와 유사하게 된다.Here, when etching an ITO metal film using an ITO etchant consisting of hydrochloric acid and acetic acid, the etching time is generally about 210 to 270 seconds in the conventional case, but in the case of the embodiment of the present invention is about 60 to 120 seconds in total As required, despite the use of ITO etchant consisting of hydrochloric acid and acetic acid, the etching time is similar to that of using ITO etchant consisting of hydrochloric acid and nitric acid.
따라서, Al 금속막으로 이루어진 데이터 라인의 손상을 최소화시키면서, 그 식각 시간은 종래 보다 단축시킬 수 있다.Therefore, the etching time can be shorter than before while minimizing damage to the data line made of the Al metal film.
또한, 식각 시간을 더 감소시키기 위해서, 염산과 질산으로 이루어진 ITO 에천트를 사용하여 비정질의 ITO 금속막에 대한 식각 공정을 수행할 수도 있다. 이 경우, 종래에는 데이터 라인의 재질인 Al 금속막이 상기한 ITO 에천트에 의해 심하게 손상되지만, 본 발명의 경우는 비정질 ITO 금속막의 식각 속도가 빠른 것에 기인하여, Al 금속막의 손상이 그 만큼 감소되기 때문에, 적용 가능하다. 여기서, 염산과 질산으로 이루어진 ITO 에천트를 사용할 경우, 그 조성은 염산:질산:물이 20:1:10의 부피비를 갖으며, 3회에 걸쳐 각각 10∼15초 동안 식각 공정을 수행한다.In addition, in order to further reduce the etching time, an etching process may be performed on an amorphous ITO metal film using an ITO etchant composed of hydrochloric acid and nitric acid. In this case, the Al metal film, which is a material of the data line, is severely damaged by the above-described ITO etchant, but in the case of the present invention, due to the high etching rate of the amorphous ITO metal film, the damage of the Al metal film is reduced by that much. Therefore, it is applicable. Here, in the case of using an ITO etchant consisting of hydrochloric acid and nitric acid, the composition has a volume ratio of hydrochloric acid: nitric acid: water of 20: 1: 10, and the etching process is performed three times for 10 to 15 seconds each.
한편, 비정질의 ITO 금속막은 그 자체로 저항이 크고, 아울러, 전도성이 부족하기 때문에, 저항을 낮춤과 동시에 전도성을 부여하기 위하여, 어닐링 공정을 수행해야만 한다. 따라서, 본 발명의 실시예에서는 비정질의 ITO 금속막에 대한 식각 공정을 완료한 후에, 상기 비정질의 ITO 금속막의 전항을 낮추고, 그리고, 전도성을 부여하기 위하여 200∼350℃에서 0.6∼2시간 동안 어닐링을 해준다.On the other hand, since the amorphous ITO metal film has a large resistance in itself and lacks conductivity, in order to lower the resistance and impart conductivity, an annealing process must be performed. Therefore, in the embodiment of the present invention, after completing the etching process for the amorphous ITO metal film, to lower the previous term of the amorphous ITO metal film, and anneal for 0.6 to 2 hours at 200 ~ 350 ℃ to impart conductivity Do it.
그런데, 공지된 탑 ITO 구조의 TFT 어레이 기판의 제작시에는, 마지막 공정 단계로서, TFT의 특성 향상이 향상되도록 어닐링 공정이 수행되고 있으므로, 비정질의 ITO 금속막의 저항을 낮춤과 동시에 전도성을 부여하기 위한 어닐링 공정은 별도로 수행하지 않고, TFT의 특성 향상을 위한 어닐링시에 함께 수행되도록 한다.By the way, when fabricating a TFT array substrate having a known top ITO structure, as an final process step, an annealing process is performed to improve the characteristics of the TFTs, thereby lowering the resistance of the amorphous ITO metal film and providing conductivity. The annealing process is not performed separately, but is performed together in annealing for improving the characteristics of the TFT.
도 2는 본 발명의 실시예에 따라 제작된 탑 ITO 구조의 TFT 어레이 기판을 도시한 단면도이다. 여기서, 도 1과 마찬가지로, 도면부호 1은 유리기판, 2는 게이트 라인, 3은 게이트 절연막, 4는 반도체층, 5는 오믹층, 6a는 소오스 전극, 6b는 드레인 전극, 10은 TFT, 11은 보호막, 12는 콘택홀, 13은 화소전극이다.2 is a cross-sectional view illustrating a TFT array substrate having a top ITO structure manufactured according to an embodiment of the present invention. 1, reference numeral 1 denotes a glass substrate, 2 a gate line, 3 a gate insulating film, 4 a semiconductor layer, 5 an ohmic layer, 6a a source electrode, 6b a drain electrode, 10 a TFT, and 11 a The protective film 12 is a contact hole and 13 is a pixel electrode.
도시된 바와 같이, 그 구조는 도 1에 도시된 종래의 구조와 동일하지만, 화소전극(13)을 형성하기 위한 ITO 금속막의 식각시에, ITO 에천트에 의해 소오스/드레인 전극(6a, 6b)을 포함한 데이터 라인(6)의 손상은 발생되지 않는다.As shown, the structure is the same as the conventional structure shown in Fig. 1, but at the time of etching the ITO metal film for forming the pixel electrode 13, the source / drain electrodes 6a and 6b are formed by the ITO etchant. The damage of the data line 6 including the above does not occur.
따라서, 데이터 라인(6)의 신뢰성을 확보할 수 있으며, 아울러, ITO 금속막에 대한 식각 속도를 증가시킨 것에 기인하여, 전체적인 공정 시간을 감소시킬 수 있다.Therefore, the reliability of the data line 6 can be ensured, and at the same time, the overall process time can be reduced due to the increased etching rate for the ITO metal film.
이상에서와 같이, 본 발명은 결정질의 ITO 금속막에 비해 식각 속도가 빠른 비정질의 ITO 금속막을 성막함으로써, 염산과 질산으로 이루어진 ITO 에천트에 비해, 데이터 라인의 재질인 Al 금속막의 손상을 줄일 수 있는 염산과 초산으로 이루어진 ITO 에천트를 사용하면서도 그 식각 시간을 감소시킬 수 있다.As described above, the present invention can reduce the damage of the Al metal film, which is a material of the data line, by forming an amorphous ITO metal film having a faster etching rate than the crystalline ITO metal film, compared to an ITO etchant composed of hydrochloric acid and nitric acid. It is possible to reduce the etching time by using ITO etchant consisting of hydrochloric acid and acetic acid.
따라서, 데이터 라인의 손상을 감소시킬 수 있는 것에 기인하여, 상기 데이터 라인의 신뢰성 확보는 물론, 제조 수율을 향상시킬 수 있다.Therefore, due to being able to reduce the damage of the data line, it is possible to ensure the reliability of the data line, as well as improve the manufacturing yield.
게다가, 식각 시간을 감소시킬 수 있기 때문에, 장비 운영 능력의 증대 및 전체적인 공정 시간의 단축 효과를 얻을 수 있다.In addition, since the etching time can be reduced, the effect of increasing the equipment operating capability and the overall process time can be obtained.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR1019990024601A KR20010004016A (en) | 1999-06-28 | 1999-06-28 | Method of manufacturing TFT-LCD |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20020078582A (en) * | 2001-04-06 | 2002-10-19 | 테크노세미켐 주식회사 | Selective etchant formulation for ito film |
| KR100532080B1 (en) * | 2001-05-07 | 2005-11-30 | 엘지.필립스 엘시디 주식회사 | Echant for amorphous indium-tin-oxide and fabrication method using the same |
| KR100796483B1 (en) * | 2001-05-16 | 2008-01-21 | 엘지.필립스 엘시디 주식회사 | Method For Fabricating Liquid Crystal Display Device |
| KR100964615B1 (en) * | 2003-08-29 | 2010-06-21 | 삼성전자주식회사 | Process for Manufacturing LCD Assembly |
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| JPH05158071A (en) * | 1991-12-09 | 1993-06-25 | Oki Electric Ind Co Ltd | Production of lower substrate of active matrix liquid crystal display |
| JPH09293875A (en) * | 1996-04-26 | 1997-11-11 | Canon Inc | Semiconductor element substrate, manufacture thereof, and semiconductor device using its substrate |
| KR19990003013A (en) * | 1997-06-24 | 1999-01-15 | 구자홍 | LCD and its manufacturing method |
| JPH11153803A (en) * | 1997-11-21 | 1999-06-08 | Sony Corp | Liquid crystal display element |
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| JPH05158071A (en) * | 1991-12-09 | 1993-06-25 | Oki Electric Ind Co Ltd | Production of lower substrate of active matrix liquid crystal display |
| JPH09293875A (en) * | 1996-04-26 | 1997-11-11 | Canon Inc | Semiconductor element substrate, manufacture thereof, and semiconductor device using its substrate |
| KR19990003013A (en) * | 1997-06-24 | 1999-01-15 | 구자홍 | LCD and its manufacturing method |
| JPH11153803A (en) * | 1997-11-21 | 1999-06-08 | Sony Corp | Liquid crystal display element |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20020078582A (en) * | 2001-04-06 | 2002-10-19 | 테크노세미켐 주식회사 | Selective etchant formulation for ito film |
| KR100532080B1 (en) * | 2001-05-07 | 2005-11-30 | 엘지.필립스 엘시디 주식회사 | Echant for amorphous indium-tin-oxide and fabrication method using the same |
| KR100796483B1 (en) * | 2001-05-16 | 2008-01-21 | 엘지.필립스 엘시디 주식회사 | Method For Fabricating Liquid Crystal Display Device |
| KR100964615B1 (en) * | 2003-08-29 | 2010-06-21 | 삼성전자주식회사 | Process for Manufacturing LCD Assembly |
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