KR100341129B1 - method for manufacturing TFT- LCD - Google Patents

Abstract

The present invention discloses a method of manufacturing a thin film transistor-liquid crystal display device. The disclosed invention comprises the steps of depositing a metal film on an insulating substrate; Forming a first resist pattern for a gate electrode on the metal film, and then patterning the metal film in the form of a first resist pattern to form a gate electrode; Removing the first resist pattern; Sequentially stacking a gate insulating layer, a doped semiconductor layer, a source, and a drain metal layer on an insulating substrate on which the gate electrode is formed; Forming a second resist pattern for defining a source and a drain electrode on the source and drain metal film; Etching the source, the drain metal film, and the doped semiconductor layer using the second resist pattern as a mask to form a source, a drain electrode, and an ohmic contact layer; Removing the second resist pattern; Stacking an amorphous silicon layer and a protective film on the resultant; Forming a channel defining third resist pattern on the passivation layer; Forming a passivation layer covering the channel layer and the channel layer by partially patterning the passivation layer and the amorphous silicon layer using the third resist pattern as a mask; And removing the third resist pattern.

Description

Method of manufacturing thin film transistor-liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor-liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor-liquid crystal display device capable of manufacturing a thin film transistor with three masks.

In general, the active matrix liquid crystal display device among the liquid crystal display devices has high speed response and has a large number of pixels. As a result, the display screen has high characteristics such as high image quality, large size, and color screen, and is used in portable TVs, notebook PCs, automobile navigation systems, and the like.

In such an active matrix liquid crystal display device, a switching device such as a diode or a thin film transistor is disposed at the intersection of the gate bus line and the data bus line to selectively turn on / off the pixel electrode.

A conventional method of manufacturing a liquid crystal display device including the thin film transistor will be described with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a metal film for a gate bus line is deposited on a surface of an insulating substrate 1 to a predetermined thickness. Then, the metal film is patterned through the first photolithography process to form the gate electrode 2. Subsequently, the first gate insulating film 3, the second gate insulating film 4, the amorphous silicon layer 5, and the etch stopper layer 6 are sequentially deposited on the insulating substrate 1 including the gate electrode 2. do.

Thereafter, as shown in FIG. 1B, the etch stopper layer 6 is patterned to be present in the corresponding portion of the gate electrode 1 through the second photolithography process to form the etch stopper 6a. At this time, the etch stopper 6a, as is well known, prevents damage to the channel layer when forming the source and drain electrodes, thereby increasing the operating current of the thin film transistor and reducing the leakage current.

Next, as shown in FIG. 1C, the doped semiconductor layer 7 is deposited on the amorphous silicon layer 5 on which the etch stopper 6a is formed.

Next, referring to FIG. 1D, the doped semiconductor layer 7 and the amorphous silicon layer 5 are partially patterned by a third photolithography process to form the ohmic contact layers 7a and 7b and the channel layer 5 '. ). At this time, the ohmic contact layers 7a and 7b are patterned to exist on both sides of the etch stopper 6.

Subsequently, as shown in FIG. 1E, the first and second insulating layers 3 and 4 are etched by the fourth photolithography process so that the gate electrode pad portion outside the substrate may be exposed.

Then, as illustrated in FIG. 1F, a metal film for data bus lines is deposited on the lower substrate 1, and the metal film is etched through a fifth photolithography process to form an upper portion of the ohmic contact layers 7a and 7b. Source and drain electrodes 8a and 8b are formed.

However, in manufacturing the conventional thin film transistor, at least five photolithography processes, such as a gate electrode forming process, an etch stopper forming process, a channel layer forming process, a pad opening process, a source, and a drain forming process, must be performed.

At this time, the photolithography process is a photolithography process, as it is known, and includes a resist coating process, an exposure process, a developing process, an etching process, a resist removing process, and the like by itself, so that a single step takes a long time.

For this reason, in order to form the thin film transistor as described above, since a plurality of photolithography processes are required, a very long time is required, and manufacturing cost is increased, and yield is lowered.

Accordingly, a technique of reducing the one-time photolithography process has been proposed by omitting the etch stopper in another conventional method. However, if the etch stopper is omitted, part of the channel layer may be lost during the process of forming the source and drain electrodes, so that the operating current of the thin film transistor is reduced and leakage current is generated.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor-liquid crystal display device capable of reducing the number of photolithography processes without etching the channel layer.

1A to 1F are cross-sectional views of respective processes for explaining a method of manufacturing a conventional thin film transistor-liquid crystal display device.

2A to 2E are cross-sectional views of respective processes for explaining a method of manufacturing a thin film transistor-liquid crystal display device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

11-insulated substrate 12-gate electrode

13,14-gate insulating film 15-doped semiconductor layer

15a, 15b-ohmic contact layer 16-metal film for source and drain electrodes

16a, 16b-source, drain electrode 17-second resist pattern

18-Amorphous Silicon Layer 19-Protective Film

20-Third Resist Pattern

In order to achieve the above object of the present invention, according to an embodiment of the present invention, the step of depositing a metal film on the insulating substrate; Forming a first resist pattern for a gate electrode on the metal film, and then patterning the metal film in the form of a first resist pattern to form a gate electrode; Removing the first resist pattern; Sequentially stacking a gate insulating layer, a doped semiconductor layer, a source, and a drain metal layer on an insulating substrate on which the gate electrode is formed; Forming a second resist pattern for defining a source and a drain electrode on the source and drain metal film; Etching the source, the drain metal film, and the doped semiconductor layer using the second resist pattern as a mask to form a source, a drain electrode, and an ohmic contact layer; Removing the second resist pattern; Stacking an amorphous silicon layer and a protective film on the resultant; Forming a channel defining third resist pattern on the passivation layer; Forming a passivation layer covering the channel layer and the channel layer by partially patterning the passivation layer and the amorphous silicon layer using the third resist pattern as a mask; And removing the third resist pattern.

In the forming of the source, drain electrode, and ohmic contact layers, the source and drain electrode metal layers may be over-etched to expose the ohmic contact layer by a predetermined width.

In addition, the width of the ohmic contact layer exposed by the source and drain electrodes may be about 5 μm or less.

The method may further include etching the gate insulating layer between the forming of the channel layer and the passivation layer and removing the third resist pattern to expose the pad portion by the third resist pattern.

According to the present invention, a thin film transistor is formed by a first photolithography process for forming a gate electrode, a second photolithography process for forming an ohmic contact layer and a source drain electrode, and a third photolithography process for forming a channel layer and a passivation layer. To form.

As a result, the processing steps are greatly reduced compared to the conventional five photolithography processes, thereby reducing the manufacturing steps and the manufacturing process time.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views of respective manufacturing processes for explaining a method of manufacturing a thin film transistor liquid crystal display according to the present invention.

First, as shown in FIG. 2A, a metal film for a gate electrode is deposited to a predetermined thickness on an insulating substrate 11, for example, on a transparent glass substrate. Subsequently, a first photolithography process, that is, a photoresist film (not shown) is applied on the metal layer, and then exposed and developed using a mask for defining a gate electrode to form a first resist pattern (not shown). And a series of processes for etching the metal film in the form of the first resist pattern are performed to form the gate electrode 12. Subsequently, the first gate insulating layer 13 of silicon nitride oxide and the second gate insulating layer 13 of silicon nitride, the doped semiconductor layer 15, and the source are formed on the insulating substrate 11 on which the gate electrode 12 is formed. The drain metal film 16 is sequentially stacked. In this case, the first and second gate insulating layers 13 and 14 may serve to prevent current from the source drain electrode from flowing toward the gate electrode 12.

Then, as shown in FIG. 2B, a photoresist film is applied over the source and drain metal film 16, and the second resist is exposed and developed to define the source, drain electrode and data bus lines. The pattern 17 is formed. In this case, the second resist pattern 17 is formed by a second photolithography process. Thereafter, the exposed source and drain metal films 16 are excessively etched using the second resist pattern 17 as a mask to form the source and drain electrodes 16a and 16b. Subsequently, the ohmic contact layers 15a and 15b are formed by etching the exposed doped semiconductor layer 15 using the second resist pattern 17 as a mask. At this time, since the source and drain electrodes 16a and 16b are excessively etched, they are recessed inward from the second resist pattern 17. Preferably, the source and drain electrodes 16a and 16b are excessively etched so that the ohmic contact layers 15a and 15b are exposed to a width of about 5 μm or less.

Then, as shown in FIG. 2C, the second resist pattern 17 is removed by a known method, and then the amorphous silicon layer 18 for the channel 18 is formed to a thickness of about 300 to 500 kV over the resulting substrate 11. Deposit. Thereafter, a protective film 19 is deposited on the amorphous silicon layer 18 to a thickness of about 4000 to 5000 kPa.

Then, as shown in FIG. 2D, a photoresist film is applied over the passivation film 19, and predetermined partial exposure and development are performed to define the channel layer, thereby forming the third resist pattern 20. Next, the protective film 19 and the channel layer 18 are etched using the third resist pattern 20 as a mask. In this case, the passivation layer 19 and the channel layer 18 are excessively etched by a predetermined value, and thus have a smaller size than the third resist pattern 20. As a result, a thin film transistor is formed.

Next, as shown in FIG. 2E, the exposed first and second gate insulating layers 13 and 14 are etched using the third resist pattern 20 and the source and drain electrodes 16a and 16b as a mask to form a pad. Expose a portion (not shown).

Thereafter, the third resist pattern 20 is removed in a known manner.

As described in detail above, according to the present invention, the first photolithography process for forming the gate electrode, the second photolithography process for forming the ohmic contact layer and the source drain electrode, the channel layer and the protective film for forming The thin film transistor is formed by a third photolithography process.

As a result, the processing steps are greatly reduced compared to the conventional five photolithography processes, thereby reducing the manufacturing steps and the manufacturing process time.

In addition, since the channel layer is formed after the source and drain electrodes are formed, the channel layer is not etched.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

Depositing a metal film on the insulating substrate; Forming a first resist pattern for a gate electrode on the metal film, and then patterning the metal film in the form of a first resist pattern to form a gate electrode; Removing the first resist pattern; Sequentially stacking a gate insulating layer, a doped semiconductor layer, a source, and a drain metal layer on an insulating substrate on which the gate electrode is formed; Forming a second resist pattern for defining a source and a drain electrode on the source and drain metal film; Etching the source, the drain metal film, and the doped semiconductor layer using the second resist pattern as a mask to form a source, a drain electrode, and an ohmic contact layer; Removing the second resist pattern; Depositing an amorphous silicon layer and a passivation layer on the resultant substrate; Forming a channel defining third resist pattern on the passivation layer; Forming a passivation layer covering the channel layer and the channel layer by partially patterning the passivation layer and the amorphous silicon layer using the third resist pattern as a mask; And And removing the third resist pattern. The thin film transistor of claim 1, wherein the forming of the source, drain electrode, and ohmic contact layer comprises over-etching the metal film for the source and drain electrode so that a predetermined width of the ohmic contact layer is exposed. -Manufacturing method of liquid crystal display device. The method of claim 2, wherein the width of the ohmic contact layer exposed by the overetching of the source and drain electrode metal films is about 5 μm or less. The method of claim 1, wherein a portion of the gate insulating layer is etched so that a pad portion is exposed by the third resist pattern between forming the channel layer and the passivation layer and removing the third resist pattern. A method of manufacturing a thin film transistor-liquid crystal display device, further comprising the step.