JPH0289318A - Manufacture of multilayer interconnected semiconductor integrated circuit device - Google Patents

Manufacture of multilayer interconnected semiconductor integrated circuit device

Info

Publication number
JPH0289318A
JPH0289318A JP24275088A JP24275088A JPH0289318A JP H0289318 A JPH0289318 A JP H0289318A JP 24275088 A JP24275088 A JP 24275088A JP 24275088 A JP24275088 A JP 24275088A JP H0289318 A JPH0289318 A JP H0289318A
Authority
JP
Japan
Prior art keywords
insulating film
film
aluminum wiring
wiring layer
lower aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24275088A
Other languages
Japanese (ja)
Inventor
Shinichi Tonari
真一 隣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24275088A priority Critical patent/JPH0289318A/en
Publication of JPH0289318A publication Critical patent/JPH0289318A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent difference in thickness of an insulating film at the shoulder part of a lower aluminum wiring layer and at the flat part scarcely by depositing and forming the insulating film mainly consisting of polyimide over the whole surface of a semiconductor substrate including the lower wiring having an inorganic or organic insulating film left on the side surface thereof. CONSTITUTION:A silicon nitride film 3 is etched by about 1mum by reactive ion etching utilizing carbon tetrafluoride gas plasm until the surface of a lower aluminum wiring layer 2 is exposed. Because this etching is anisotropic etching, the silicon nitride film 3' is left on the side surface of the lower aluminum wiring layer 2. Lastly, polyamide precursor solution is applied by spin application process so that the film thickness at the part may be about 1mum, and baking up to about 400 deg.C is carried out stepwise to form a polyimide interlayer insulating film 4. In this case, since polyamide precursor solution is applied to the shoulder part of the lower aluminum wiring layer 2 on the basis of the surface of the silicon nitride film 3', the polyimide interlayer insulating film 4 formed on the shoulder part of the lower aluminum wiring layer 2 scarcely differs from that formed on the flat part.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線半導体集積回路装置の製造方法に関し
、特に多層金属配線の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a multilayer interconnect semiconductor integrated circuit device, and more particularly to a method for forming multilayer metal interconnects.

〔従来の技術〕[Conventional technology]

従来より多層配線構造を形成するための層間絶縁膜には
ポリイミド重合膜が用いられている。この理由は、絶縁
膜が最初溶液状態のものの基板上へのスピン塗布から始
まり、ついでこれを焼きしめることによって形成される
なめ、結果として配線段差を平滑化する作用があり、容
易に上層配線を形成することができるためである。
Conventionally, polyimide polymer films have been used as interlayer insulating films for forming multilayer wiring structures. The reason for this is that the insulating film is formed by spin-coating a solution onto the substrate and then baking it, which has the effect of smoothing out wiring steps and making it easier to remove upper layer wiring. This is because it can be formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上述したスピン塗布法によって形成され
た膜は、第3図に示す様に下層アルミ配線2の肩の部分
の膜厚6が他の平坦部分の膜厚に比較して薄く形成され
る。これは膜の断面形状が塗布時の溶液の表面張力に応
じて決定されるなめであり、原理的に避けられない問題
である。この対策として、従来は下層アルミ配!!2の
肩の部分の層間絶縁膜の絶縁耐圧を確保するために、第
4図に示す様に平坦部が配線段差の約1..5〜2倍程
度となるように膜厚を最初から大きく見積って塗布され
る。この影響として配線を上下に接続する箇所に於ける
層間絶縁膜の膜厚も大きくなり、接続不良が発生しやす
くなる欠点を生じる。この理由は、上層アルミ配線は、
眉間絶縁膜にスルーホールの開孔を行った後、通常スパ
ッタリング等のフィジカル・ペーパー・デポジション(
Physical Vapor Deposition
 )法、所謂。
However, in the film formed by the above-described spin coating method, the film thickness 6 at the shoulder portion of the lower aluminum wiring 2 is thinner than the film thickness at other flat portions, as shown in FIG. This is a problem that cannot be avoided in principle because the cross-sectional shape of the film is determined depending on the surface tension of the solution at the time of application. As a countermeasure for this, conventionally the lower layer was made of aluminum! ! In order to ensure the dielectric strength of the interlayer insulating film at the shoulder portion of 2, the flat part is approximately 1. .. The film thickness is estimated from the beginning so that it will be approximately 5 to 2 times as thick as the coating. As a result, the thickness of the interlayer insulating film at the locations where the wirings are connected vertically increases, resulting in a drawback that connection failures are more likely to occur. The reason for this is that the upper layer aluminum wiring
After making through holes in the glabellar insulating film, physical paper deposition such as sputtering is usually used (
Physical Vapor Deposition
) law, so-called.

PVD法を用いてつけられるが、PVD法は段部の被覆
性に乏しい為第2図に示す様にスルーホールが深い程上
層アルミ配線7には被覆不良部8が発生し易くなるため
である。
Although it is attached using the PVD method, since the PVD method has poor coverage of the stepped portion, as shown in FIG. 2, the deeper the through hole is, the more likely it is that poor coverage 8 will occur in the upper layer aluminum wiring 7. .

本発明の目的は、上記の状況に鑑み、平坦部に対し必要
以上の膜厚を形成することなく、また、下層アルミ配線
の肩部分と平坦部の膜厚に殆んど差異を生じることなき
眉間絶縁膜の形成工程を備えた多層配線半導体集積回路
装置の製造方法を提供することである。
In view of the above-mentioned circumstances, an object of the present invention is to avoid forming a film thicker than necessary on the flat part, and to create a film with almost no difference in film thickness between the shoulder part and the flat part of the lower layer aluminum wiring. It is an object of the present invention to provide a method for manufacturing a multilayer wiring semiconductor integrated circuit device, which includes a step of forming a glabellar insulating film.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば、多層配線半導体集積回路装置の製造方
法は、半導体基板上に下層配線を選択的に形成する工程
と、前記下層配線を含む半導体基板上に無機または有機
の絶縁膜を被覆形成する工程と、前記下層配線の側面に
無機または有機の絶縁膜を残す前記無機または有機の絶
縁膜の選択的除去工程と、前記無機または有機の絶縁膜
を側面に残す下層配線を含む半導体基板全面にポリイミ
ドを主体とする絶縁膜を被着形成する工程とからなる眉
間絶縁膜の形成工程を含んで構成される。
According to the present invention, a method for manufacturing a multilayer wiring semiconductor integrated circuit device includes the steps of selectively forming a lower layer wiring on a semiconductor substrate, and forming an inorganic or organic insulating film on the semiconductor substrate including the lower layer wiring. a step of selectively removing the inorganic or organic insulating film, leaving the inorganic or organic insulating film on the side surfaces of the lower wiring; and a step of selectively removing the inorganic or organic insulating film on the side surfaces of the lower wiring; The method includes a step of forming an insulating film between the eyebrows, and a step of depositing an insulating film mainly made of polyimide.

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図(a)〜(d)は本発明の一実施例を示す層間絶
縁膜の形成工程図である。本実施例によれば、第1図(
a)に示すように、半導体基板1上に下層アルミ配線2
がまず形成される。すなわち、基板1上に1μm程度の
厚さのアルミ膜がスパッタ法にてまず最初被着され、つ
いで、通常のフォトリソグラフィー法によって形成され
たフォトレジストをマスクとする塩素プラズマガスによ
るアルミのりアクティブ・イオン・エツチングが行われ
て下層アルミ配線2が形成される。つぎにシランおよび
アンモニアを原料としたプラズマCVD法により約1μ
mの厚さのシリコン窒化膜3が付けられ〔第1図(b)
参照〕、ついで、四弗化炭素(CF4 )ガス・プラズ
マを用いなりアクティブ・イオン・エツチングによって
このシリコン窒化膜3を下層アルミ配線2の表面が露出
するまで約1μmエツチングされる。このエツチングは
異方性エツチングであるので、下層アルミ配線2の側面
にはシリコン窒化pA3’が残される〔第1図(c)参
照〕。最後にポリアミド前駆体溶液を平坦部の膜厚が約
1μmの厚さになるようにスピン塗布法を用いて塗布し
、約400℃迄の焼きしめを段階的に行うことによって
、ポリイミド層間絶縁膜4が形成される〔第1図(d)
参照〕。この際、ポリアミド前駆体溶液はシリコン窒化
膜3′の面上を基準として下層アルミ配線2の肩部に塗
布されて行くので、下層アルミ配線2の肩部分には平坦
部とほとんど差異のないポリイミド層間絶縁膜4が形成
される。
FIGS. 1(a) to 1(d) are process diagrams for forming an interlayer insulating film showing one embodiment of the present invention. According to this embodiment, as shown in FIG.
As shown in a), a lower aluminum wiring 2 is formed on a semiconductor substrate 1.
is formed first. That is, an aluminum film with a thickness of about 1 μm is first deposited on the substrate 1 by sputtering, and then active aluminum film is applied using chlorine plasma gas using a photoresist formed by ordinary photolithography as a mask. Ion etching is performed to form lower layer aluminum wiring 2. Next, approximately 1 μm
A silicon nitride film 3 with a thickness of m is applied [Fig. 1(b)].
Then, this silicon nitride film 3 is etched by about 1 μm by active ion etching using carbon tetrafluoride (CF4) gas plasma until the surface of the lower layer aluminum wiring 2 is exposed. Since this etching is anisotropic etching, silicon nitride pA3' is left on the side surfaces of the lower aluminum wiring 2 [see FIG. 1(c)]. Finally, a polyamide precursor solution is applied using a spin coating method so that the film thickness on the flat part is approximately 1 μm, and baking is performed stepwise to approximately 400°C to form a polyimide interlayer insulating film. 4 is formed [Fig. 1(d)
reference〕. At this time, since the polyamide precursor solution is applied to the shoulder part of the lower aluminum wiring 2 with reference to the surface of the silicon nitride film 3', the polyimide precursor solution is applied to the shoulder part of the lower aluminum wiring 2, which has almost no difference from the flat part. An interlayer insulating film 4 is formed.

第2図(a)〜(d)は本発明の他の実施例を示す眉間
絶縁膜の形成工程図である。本実施例によれば、下層ア
ルミ配線2の側面には前実施例のシリコン窒化膜3′に
代えてポリイミド膜5′が形成される。すなち、下層ア
ルミ配線2の形成後〔第2図(a>参照〕。ポリアミド
前駆体溶液を平坦部の膜厚が約1μmの厚さになるよう
にスピン塗布し、約400°C迄の段階的な焼しめを行
いポリイミド膜5をつける〔第2図(b)参照〕。
FIGS. 2(a) to 2(d) are process diagrams for forming a glabellar insulating film showing another embodiment of the present invention. According to this embodiment, a polyimide film 5' is formed on the side surface of the lower aluminum wiring 2 in place of the silicon nitride film 3' of the previous embodiment. That is, after forming the lower aluminum wiring 2 [see Fig. 2 (a>)], a polyamide precursor solution was spin-coated to a film thickness of about 1 μm on the flat part, and heated to about 400°C. A polyimide film 5 is applied by stepwise baking (see FIG. 2(b)).

ついで、酸素ガス・プラズマを用いたプラズマ等方性エ
ツチングによってこのポリイミド膜5を下層アルミ配線
2の表面が露出するまで約1μmエツチングする。この
時配線段部には平坦部に比穀してポリイミド膜5が厚く
形成されているので、エツチング後配線側面に約0.5
μm程度の幅と高さのポリイミド膜5′が残される〔第
2図(c)参照〕。最後にスピン塗布法を用いてポリイ
ミド層間絶縁H4を形成すれば、前実施例と同様に下層
アルミ配線2の肩部分には平坦部とほとんど差異のない
第2図(d)に示す如きボリイミド眉間絶縁膜4が形成
される。
Next, this polyimide film 5 is etched by about 1 μm by plasma isotropic etching using oxygen gas plasma until the surface of the lower aluminum wiring 2 is exposed. At this time, since the polyimide film 5 is formed thicker than the flat part on the wiring step part, the thickness of the polyimide film 5 is about 0.5 on the side surface of the wiring after etching.
A polyimide film 5' having a width and height of approximately μm is left behind [see FIG. 2(c)]. Finally, if the polyimide interlayer insulation H4 is formed using the spin coating method, the shoulder part of the lower aluminum wiring 2 will have a polyimide glabella as shown in FIG. Insulating film 4 is formed.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、多層配線
構造を形成するに際し、従来と同じく層間絶縁膜として
ポリイミド重合膜を用いたとしても、下層配線の側面に
配線と同程度の高さ及び幅をもった絶縁膜が形成される
ので、下層配線の肩の部分においても、平坦部に比較し
てポリイミド重合膜が薄くなることが少ない。従って、
眉間絶縁膜を比較的薄く形成することが可能となりスル
ーホールの深さを小さくすることができるので、スルー
ホールにおいて上層配線が被覆不良をおこし、接続不良
を発生するなどの問題点が解決される。
As explained in detail above, according to the present invention, when forming a multilayer wiring structure, even if a polyimide polymer film is used as an interlayer insulating film as in the past, the side surface of the lower layer wiring has a height comparable to that of the wiring. Since an insulating film having a width and a width is formed, the polyimide polymer film is less likely to become thinner at the shoulder portions of the lower wiring than at the flat portions. Therefore,
It is possible to form a relatively thin insulating film between the eyebrows and reduce the depth of the through hole, which solves problems such as poor coverage of the upper layer wiring in the through hole and poor connection. .

の部分工程図、第5図は従来法による層間絶縁膜の構造
的欠陥を示す図である。
FIG. 5 is a diagram showing structural defects in the interlayer insulating film produced by the conventional method.

1・・・半導体基板、2・・・下層アルミ配線、3・・
・シリコン窒化膜、3′・・・下層アルミ配線の側面に
残されたシリコン窒化膜、4・・・ポリイミド層間絶縁
膜、5・・・ポリイミド膜、5′・・・下層アルミ配線
の側面に残されたポリイミド膜。
1... Semiconductor substrate, 2... Lower layer aluminum wiring, 3...
・Silicon nitride film, 3'...Silicon nitride film left on the side surface of the lower layer aluminum wiring, 4...Polyimide interlayer insulating film, 5...Polyimide film, 5'...On the side surface of the lower layer aluminum interconnection The remaining polyimide film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に下層配線を選択的に形成する工程と、前
記下層配線を含む半導体基板上に無機または有機の絶縁
膜を被覆形成する工程と、前記下層配線の側面に無機ま
たは有機の絶縁膜を残す前記無機または有機の絶縁膜の
選択的除去工程と、前記無機または有機の絶縁膜を側面
に残す下層配線を含む半導体基板全面にポリイミドを主
体とする絶縁膜を被着形成する工程とからなる層間絶縁
膜の形成工程を含むことを特徴とする多層配線半導体集
積回路装置の製造方法。
A step of selectively forming a lower layer wiring on a semiconductor substrate, a step of coating an inorganic or organic insulating film on the semiconductor substrate including the lower layer wiring, and a step of forming an inorganic or organic insulating film on a side surface of the lower layer wiring. It consists of a step of selectively removing the remaining inorganic or organic insulating film, and a step of depositing an insulating film mainly made of polyimide over the entire surface of the semiconductor substrate, including the lower layer wiring, leaving the inorganic or organic insulating film on the side surfaces. A method for manufacturing a multilayer wiring semiconductor integrated circuit device, comprising a step of forming an interlayer insulating film.
JP24275088A 1988-09-27 1988-09-27 Manufacture of multilayer interconnected semiconductor integrated circuit device Pending JPH0289318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24275088A JPH0289318A (en) 1988-09-27 1988-09-27 Manufacture of multilayer interconnected semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24275088A JPH0289318A (en) 1988-09-27 1988-09-27 Manufacture of multilayer interconnected semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0289318A true JPH0289318A (en) 1990-03-29

Family

ID=17093710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24275088A Pending JPH0289318A (en) 1988-09-27 1988-09-27 Manufacture of multilayer interconnected semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0289318A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11705061B2 (en) 2021-06-21 2023-07-18 Samsung Electronics Co., Ltd. Display device for low power driving and method of operating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53104186A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Multilayer wiring body
JPS60161637A (en) * 1984-02-01 1985-08-23 Hitachi Ltd Electronic device
JPS62108542A (en) * 1985-11-06 1987-05-19 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53104186A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Multilayer wiring body
JPS60161637A (en) * 1984-02-01 1985-08-23 Hitachi Ltd Electronic device
JPS62108542A (en) * 1985-11-06 1987-05-19 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11705061B2 (en) 2021-06-21 2023-07-18 Samsung Electronics Co., Ltd. Display device for low power driving and method of operating the same

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