JPS5882536A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten wiring layers by executing ion milling to an electrode wiring layer on a substrate having uneven surface from oblique direction to the substrate surface. CONSTITUTION:A window is opened to PSG1 on the Si substrate and the Al wiring 3 is formed. Then, while the substrate is rotated, the Ar ion 4 is irradiated at an angle of 60-70 degrees from the perpendicular of substrate surface. At this time, since ion does not easily enter the narrow dent region of window and therefore such region is less etched than the other areas, the step region is curtailed. When aluminium is vacuum-depositied by the suputtering on the wiring 3 and the Ar ion is irradiated again in the same angle, the step region is further curtailed. In case the sputtering evaporation of aluminium and ion milling are alternately repeated for several times as described above, the aluminium wiring layer 3 having the flat surface is obtained and when such wiring layers are formed into multi-layered structure, disconnection does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to semiconductor devices, and particularly relates to a method for forming electrode wiring layers of transistors, integrated circuits, etc.012) Prior Art and Problems Electrode wiring has conventionally It was formed by depositing a layer of an electrically conductive material such as aluminum (At) on a substrate using a sputter deposition method or the like. However, a substrate with a step provided with an electric window etc., for example, a MOS transistor,
In a substrate with a step on which a source/drain electrode window with a height of about Lpm is provided, the step is large compared to the ratio of the step s, and the conventional forming method has no effect on the unevenness of the substrate. Since it is difficult to form a thick wiring layer, there is a drawback that wire breakage is likely to occur at the corners of steps where the electrode wiring layer is thinner.On the other hand, in the conventional forming method, the electrode Even if a wiring layer is formed, the surface of the electrode wiring layer will not become flat; rather, the surface of the electrode wiring layer will not become flat; rather, the formation of a wiring layer will increase the level difference. There is a problem that K"#li is likely to occur when dovetails are stacked. (3) Purpose of the Invention In order to solve the above-mentioned conventional drawbacks, the present invention provides an electrode wiring that does not cause disconnection in single-layer and multi-layer wiring. The object of the present invention is to provide a method for forming a layer.

(4) Structure of the Invention According to the present invention, this object is a TSL process for forming an electrode wiring layer made of an electrode material on a substrate.

A 4m process of ion milling by irradiating ions from an oblique direction to the electrical wiring layer on the substrate, and a process of planarizing the electrode wiring layer by alternately performing the steps of 51g1 and igs. It is achieved from.

When ions are irradiated obliquely onto the surface of a substrate using the ion milling method, the ions enter the narrow recesses provided in the substrate. After forming the Ii1 layer, the electrode wiring layer is ion-milled from a diagonal direction with respect to the substrate. The electrode set @m provided in this manner is formed in the recessed part of the substrate, and the electrode wiring layer formed in the area other than the recessed part is milled more often than the electrode wiring layer formed in the recessed part of the substrate. ? 71F) The level difference after ion milling is smaller than the level difference caused by ion milling on the substrate. If this process is repeated many times, the level difference will gradually disappear each time this process is repeated, and the surface blood of the 11IL electrode wiring layer can be flattened. *
If g can be flattened, Of! at the corner of the step! This eliminates the problem of thinning of the wire layer, and it is possible to prevent disconnection of the electrode wiring layer. In addition, in multilayer wiring, the surface of the first electrode wiring layer is flat, so even if the wiring layers are sequentially formed,
M does not occur, and even if one layer is stacked, no wire breakage occurs.

忤) Embodiments of the Invention The following 1 Invention Practical II/IAIP I will be described in detail in terms of FjA plane.
A phosphosilicate glass (P2O) layer of Il Peng is formed and a window S of 13 m is provided by l < linear y (11) ji fj (11'Fig. 1m))
Fluminicum (Mut) was deposited on top of the P8G layer by sputter deposition so that the layer thickness on the P8G layer was 1lII11.
#j! , when the rock layer is formed, the layer thickness of the At wiring layer 8 in the gs also becomes lIIm (Hl fHJ lbJ
) o Next, while rotating the substrate, from the straight FILIiI to the plane of the ji mold, 60~7 GO,, III
”C7kfy (A'r) A:ty 4 f Hj@
@l.

Then, ion milling is performed on the 80-layer-thick thick wiring layer 80A formed on the P8G layer ◎ At this time, the At wiring layer 8 formed on the window 3 is about 1000A 1
, or not milled. Therefore, the layer thickness of layer 8 is P
SGml has a 500OA% window S with 9000 people6.
Figure CjlI1 (cJ) shows that the step difference has become smaller from the step filpm before Az sputter deposition to 600OA.
oThe ion irradiation angle was set to 60 to 70 degrees because
<0 because the ring efficiency at this angle is the best.Next, when AL is further sputter-evaporated by 50 GOA on the Aj wiring layer, the layer thickness of the At wiring layer 8 will be ll on the P19G layer l.
lm1 window S 1. (Fig. 1 m)
l). When the Ar ion number is irradiated again at the same angle as mentioned above and the At wiring layer 8 on the P8G layer 1 is milled by 500 OA, the Ar wiring layer 8 in the window 8 is milled by only about 100 OA, and therefore the At wiring layer 8 The R difference is about ioo
.

It becomes even smaller than A (m1 Fig. 1et)
.

By repeating this process, that is, the process of alternately performing the μ sputter II layer and the μ sputter II layer and on-milling, several times, the step roof of the μ sputter layer becomes gradually smaller, and the interconnect layer with a flat surface becomes smaller. l is obtained. At this time, the thickness of the wiring layer for the P8G layer 1 is set to l.

(2) Effects of the invention According to the f14 of the present invention, the surface of the electrode wiring layer can be flattened, thereby preventing the conventional problem, that is, the occurrence of disconnection at the corner part of the nine wave difference provided on the substrate. In multi-layer wiring, the surface of the first JI electrode wiring layer is flat, so 4hR11 will not occur when wiring layers are sequentially formed, and therefore, disconnection will not occur even if the layers are stacked. There is an effect of 0

[Brief explanation of drawings]

Figures 9 and 9 are cross-sectional views of a semiconductor device showing various steps of manufacturing an electrode wiring layer in this embodiment. l PilGfi! l Window A
t Wiring layer 6 Ar ion sprout Figure 1 ((1) (j) Figure 1 m e)

Claims (1)

[Claims] a first step of forming an electrode wiring layer made of an electrode material on a substrate; and a first step of forming an electrode wiring layer made of an electrode material on a substrate;
The eighth step is ion milling by irradiating ions to the polar layer.
A method for manufacturing a semiconductor device, comprising the following steps: and a step of planarizing the electrode wiring layer by alternately performing the first and second steps.