JPS60136335A - Multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To prevent a faulty short-circuit generating from the coexistence of unnecessary foreign substance as well as to improve the electrical reliability of the titled device by a method wherein an interlayer insulating layer is composed of a silicon nitride layer formed by performing a plasma CVD method and a silicon oxide layer formed by performing a bias sputtering technique. CONSTITUTION:The first layer of wirings 3A, 3B and 3C are formed. Then, when a silicon nitride layer which is formed by performing a plasma CVD technique is used for the first insulating layer 4 which is covered on the wiring 3, a foreign substance 4A is coexisted in the process wherein the first insulating layer 4 is formed. When silicon oxide layer is used for the second insulating layer 5 using a bias sputtering technique, the upper surface part of the layer 5 is flattened, and a foreign substance 5A is coexisted in the process of formation of the second insulating layer 5. After the above-mentioned process has been finished, the insulating layers 4 and 5 located on the upper part of the first layer wiring 3A are selectively removed, and a connecting hole 6 is formed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to multilayer wiring technology, and particularly to a technique that is effective when applied to multilayer wiring technology of semiconductor integrated circuit device 1. It is.

[Background Art] In a semiconductor integrated circuit device that employs a multilayer wiring structure, the upper surface of an interlayer insulating layer provided between each conductive layer is flattened in order to improve electrical reliability and fine processing of upper layer wiring. is considered to be one of the important technical issues.

Therefore, it is known that the interlayer insulating layer is formed by bias sputtering technology ("Fundamentals of Thin Film Work", Tatsuo Asamaki, Nikkan Kogyo Shimbun, p. 132).

However, as a result of electrical characteristic tests and studies on such technology, the present inventor has found that a single layer 1 interlayer insulating layer formed by bias sputtering of quartz t (SiO2 film) does not provide sufficient electrical connection between the lower layer wiring and the upper layer wiring. We discovered a problem that would make it impossible to separate the issues.

The present inventor considers that the above problem is caused by the causes described below.

That is, in the process of forming the interlayer insulating layer using the quartz bias sputtering technique, the glabellar insulating layer contains unnecessary foreign matter that may cause a short circuit between the lower layer wiring and the upper layer wiring. These foreign substances include stainless steel particles generated when the target, the jig that supports the semiconductor wafer, the inner wall of the quartz bias sputtering equipment, etc. are struck by argon ions, as well as silicon particles and silicon oxide particles caused by poor formation of the glabella insulating layer. Yes, sometimes the size is 1 to 4 [μm]
There are some things that reach a certain degree. Foreign matter such as stainless steel particles is conductive and therefore induces the short-circuit failure, while foreign matter such as silicon particles and silicon oxide particles forms pinholes in the insulating layer between the eyebrows and similarly induces short-circuit defects. .

Therefore, the present inventor believes that unless this problem is solved, electrical reliability of a semiconductor integrated circuit device employing a multilayer wiring structure cannot be achieved.

[Purpose of the invention]

An object of the present invention is to provide a technical means capable of preventing short-circuit defects between lower layer wiring and upper layer wiring due to unnecessary foreign matter mixed in interlayer insulation layers in a multilayer wiring structure (member). .

Another object of the present invention is to provide a multilayer wiring structure (member) with:
The object of the present invention is to provide technical means that can improve electrical reliability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a multilayer wiring structure (member), the interlayer insulating layer is subjected to plasma CV [) (+JHical Vapor
By forming a silicon nitride layer using the rDeposition technology and a silicon oxide layer using the bias sputtering technology, it is possible to reduce the probability that unnecessary foreign substances mixed in each layer will reach the lower layer wiring and the upper layer wiring. The purpose is to prevent short circuit defects and improve electrical reliability.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

This embodiment will be explained using a semiconductor integrated circuit device that employs a two-layer wiring structure.

〔Example〕

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device for explaining one embodiment of the present invention.

In all the figures, those having the same function are marked with the same - signal, and repeated explanations will be omitted.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate of a predetermined conductivity type made of monoactive silicon crystal, and is used to construct a semiconductor integrated circuit device. Although not shown, the semiconductor substrate 1 is provided with semiconductor elements such as insulated gate field effect transistors and bipolar transistors. Reference numeral 2 denotes an insulating layer provided between the semiconductor element and a first layer of wiring, which will be described later, for electrically isolating them. 3A, 3B, and 3G are first-layer wirings provided above the insulating layer 2, and are mainly used to electrically connect the semiconductor elements via the insulating layer 2. 4
are the first layer wirings 3A and 3B.

a first insulating layer provided to cover the upper part of the 3G;
is a second insulating layer provided on top of the first insulating layer 4, which electrically isolates the first layer wiring 3 and the second layer wiring to be described later, and 1 insulating layer 4 and the second
This is to prevent short-circuit failures due to unnecessary foreign matter that may be mixed in with the insulating layer 5. 4A
5A is an unnecessary foreign substance mixed in the first insulating layer 4 in the forming process, and 5A is an unnecessary foreign substance mixed in the second insulating layer 5 in the forming process. this is.

Between the first layer wiring 3 and the second layer wiring (described later), conductive materials such as stainless steel particles may cause short-circuit defects between them, and silicon particles, silicon oxide particles, etc. Even if the material is substantially insulating, pinholes and the like can be formed and short circuits can occur between them. However, in this embodiment, by configuring the glabella insulating layer with a plurality of layers including the first insulating layer 4 and the second insulating layer 5, unnecessary foreign substances 4A and 5A mixed in each layer are removed from the first insulating layer.
It is possible to reduce the probability of reaching the wiring 3 of the layer and the wiring of the second layer to be described later, and since the probability that unnecessary foreign substances 4A and 5A mixed in each layer overlap in the same part is extremely small, These short-circuit defects can be prevented. 6 are insulating layers 4 and 5 above the first layer wiring 3A;
This is a connection hole formed by selectively removing the contact hole, and is for electrical connection to a second layer of wiring, which will be described later.

Reference numeral 7 denotes a second layer wiring which is electrically connected to the first layer wiring 3A through the connection hole 6 and is provided so as to extend above the second insulating layer 5, and is connected to the semiconductor element - This is for electrically connecting between the first layer wiring 3 and the like.

Next, a specific manufacturing method of this example will be explained.

2 to 5 are sectional views of main parts of the semiconductor integrated circuit device in each manufacturing process for explaining the manufacturing method of the embodiment of the present invention.

First, after semiconductor elements and the like (not shown) are formed on a semiconductor substrate 1, an insulating layer 2 is formed to cover them. Then, the insulating layer above a predetermined semiconductor element is selectively removed to form a connection hole (not shown). Thereafter, as shown in FIG. 2, first layer wirings 3A, 3B, and 3C that are electrically connected to a predetermined semiconductor element through the connection hole and extend above the insulating layer 2 are formed. . For example, this may be done by forming an aluminum layer using sputtering technology to a thickness of about 0.8 to 1.0 [μm].

After the step shown in FIG. 2, a first insulating layer 4 is formed to cover the first layer wiring 3, as shown in FIG. For example, a silicon nitride layer formed by plasma CVD technology may be used to form the film to a thickness of about 2000 to 3000 Å. Further, a silicon oxide layer formed using a sputtering technique, a CVD technique, a phosphosilicate glass (PSG) layer formed using a CVD technique, or the like may be used. Note that the foreign matter 4A is mixed in during the formation process of the first insulating layer 4.

After the process shown in FIG. 3, the process shown in FIG. 1M54 is performed.

A second insulating layer 5 is formed by depositing on the first insulating layer 4 . For example, this can be done by using a silicon oxide layer formed by bias sputtering technique, which can flatten the upper surface, and with a thickness of 1°8 to 2.5° so that the upper surface can be flattened.
It may be formed with a film thickness of about [μm]. As mentioned above, the silicon oxide layer formed by bias sputtering technology has the characteristic that its upper surface can be flattened, but since argon ions hit the inner walls of the bias sputtering equipment, jigs, etc., unnecessary foreign matter is likely to be generated. There is a drawback that short-circuit defects are likely to occur. However, this drawback can be overcome by providing the first insulating layer 4. Note that the foreign matter 5A is mixed in during the formation process of the second insulating layer 5. In addition, the silicon oxide layer formed by bias sputtering technology is free from unnecessary foreign particles with a small size that is less than the thickness of the silicon oxide layer.
When A is present in the mixture, there is a feature that the upper surface portion of the foreign object 5A is flattened without being affected by the shape of the foreign object 5A.

After the step shown in FIG. 4, the insulating layers 4 and 5 above the first layer wiring 3A are selectively removed, and a connection hole 6 is formed as shown in FIG.

After the step shown in FIG. 5, as shown in FIG. 1, the second layer wiring 3A is formed so as to be electrically connected to the first layer wiring 3A through the connection hole 6. .

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that, after this, a treatment process such as a protective film may be performed.

〔effect〕

In the multilayer wiring member, the following effects can be obtained.

(1) By configuring the interlayer insulating layer with the first insulating layer and the second insulating layer, the probability that unnecessary foreign matter mixed in each layer will reach the lower layer wiring and the upper layer wiring can be reduced. , these short circuit defects can be prevented.

(2) According to the above (1), the electrical reliability of the multilayer wiring member can be improved due to the effect that it is possible to prevent a switching failure between the lower layer wiring and the upper layer wiring.

Above, the invention made by the present inventor has been specifically explained using Examples, but the present invention is not limited to the Examples, and within the scope of the gist thereof,
Of course, various changes are possible.

For example, although in the embodiment described above a silicon oxide layer is deposited on top of a sputtered silicon nitride layer using a bias sputtering technique, the reverse is also possible. Further, in the above embodiment, the interlayer insulating layer has a two-layer structure, but it may have a three-layer structure. Further, in the above embodiments, a semiconductor integrated circuit device having a two-layer wiring structure has been described, but a multi-layer wiring structure having three or more layers may also be used.

[Application field]

The invention described above is applied to the multilayer wiring technology of semiconductor integrated circuit devices, which is the background field of application of the invention, but the invention is not limited thereto. It may also be applied to multilayer wiring technology.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device for explaining an embodiment of the present invention, and FIGS. 2 to 5 are cross-sectional views for explaining a manufacturing method of an embodiment of the present invention. FIG. 2 is a cross-sectional view of a main part of a semiconductor integrated circuit device in a manufacturing process. In the figure, l: semiconductor substrate, 2, 4.5: insulating layer,
3A, 3B, 3C, 7=-wiring, 4A, 5A--foreign matter, 6--connection hole. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A multilayer wiring member having a plurality of layers in which conductive layers and insulating layers are alternately overlapped on the upper part of a substrate, wherein the ribbed edge layer is a first
A patented multilayer wiring structure consisting of an insulating layer and a negative 2 insulating layer deposited on top of the insulating layer. 2. The layer wiring structure according to claim 1, wherein the first insulating layer or the second insulating layer is a silicon oxide layer formed by noise sputtering technology. 3. The first insulating layer is formed using plasma CVD technology. 2. The multilayer wiring structure according to claim 1, wherein the second insulating layer is constructed using either a CVD technique or a sputtering technique, and the second insulating layer is constructed using a bias sputtering technique. 4. The multilayer wiring structure according to claim 1, wherein the first insulating layer and the second insulating layer are of the same or different film quality.