JPS6365646A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6365646A JPS6365646A JP21024486A JP21024486A JPS6365646A JP S6365646 A JPS6365646 A JP S6365646A JP 21024486 A JP21024486 A JP 21024486A JP 21024486 A JP21024486 A JP 21024486A JP S6365646 A JPS6365646 A JP S6365646A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- insulating film
- film
- silicon oxide
- plasma vapor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004544 sputter deposition Methods 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000007740 vapor deposition Methods 0.000 claims description 8
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 230000008034 disappearance Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 241001494479 Pecora Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に多層配線における層間
絶縁膜の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to the structure of an interlayer insulating film in a multilayer wiring.
高密度化および高速化を目指す最近の半導体装置、特に
集積回路装置では配線の多層化が必要不可欠である。配
線の多層化全実現する際に褒も重要なことは配線間全絶
縁分離する眉間絶縁膜の膜質と構造であシ、一般的には
まず下層配線の段差を充分に緩和°できること、すなわ
ち平坦性が良好であることが要求される。従来、この平
坦性を確保するためにはシリカ塗布膜が用いられ、例え
ば第１層アルミ配線上にプラズマ気相成長されたシリコ
ン窒化膜の凹所ｔこのシリカ塗布膜で埋め更に化学気相
成長法によるリン・ガラス膜金被覆した３層構造の層間
絶縁膜が広く用いられてきた。2. Description of the Related Art Multilayer wiring is essential in recent semiconductor devices, especially integrated circuit devices, which aim to achieve higher density and higher speed. What is important when realizing multi-layer wiring is the film quality and structure of the glabella insulating film that completely isolates the wiring. Good properties are required. Conventionally, a silica coating film has been used to ensure this flatness. For example, the recesses in a silicon nitride film grown on the first layer aluminum wiring by plasma vapor deposition are filled with this silica coating film and further deposited by chemical vapor deposition. A three-layer interlayer dielectric film coated with phosphorus glass film and gold has been widely used.
しかしながら、この従来の層間絶縁膜構造は、まず第１
に下層アルミ配線上にシリコン窒化膜をプラズマ気相成
長させる際、またはり／硅酸ガラス（ＰＳＧ）ｔ−化学
気相成長させる際アルミ配線に１ヒロツモ
７目−トまたはスルーホール不良を生じ、第２にる。ま
た、第３にはシリコン窒化膜は酸化膜に比し誘電率が高
いので配線の層間容量が大きくなシ動作速度に悪影響を
及はし更に第４には化学気相されたリン・ガラス膜はプ
ラズマ気相成長の窒化膜と比べると平坦性が良くないな
どの諸欠点を有する。とシ分け、第２番目に挙げた１ア
ルミ消失”は２〜３μｍ程度の大きさのものが１発生す
ることがあシ下層アルミ配線の断線事故または配線寿命
の大幅低下に直結するので今日の如きアルミ配線幅が／
３μｍ以下で製造される半導体デバイスにおいては致命
的障害となる。However, this conventional interlayer insulating film structure
When a silicon nitride film is grown in plasma vapor phase on the lower aluminum wiring, or when silicic acid glass (PSG) is grown in chemical vapor phase, defects in the aluminum wiring or through holes occur. Second one. Thirdly, the silicon nitride film has a higher dielectric constant than the oxide film, so the interlayer capacitance of the wiring is large, which has a negative effect on the operating speed.Fourthly, the phosphorus glass film is chemically vaporized. has various drawbacks such as poor flatness compared to plasma vapor grown nitride films. The second item, ``Aluminum loss'', is caused by the occurrence of particles with a size of about 2 to 3 μm, which directly leads to disconnection accidents in the lower layer aluminum wiring or a significant reduction in the life of the wiring, so today's The aluminum wiring width is /
This is a fatal problem for semiconductor devices manufactured with a thickness of 3 μm or less.
本発明の目的は、従って、アルミ配線に対しヒロである
。The object of the present invention is therefore to provide advantages over aluminum wiring.
本発明によれば、半導体装置は、シリコン基板と、前記
シリコン基板上のフィールド絶縁膜と、前記フィールド
絶縁膜上に形成された第１層のアルミ配線と、前記第１
層アルミ配線を含む基板全面に順次形成されるスパッタ
法によるシリコン酸化膜、プラズマ気相成長法による第
１のシリコン酸化膜、塗布法によるシリコン酸化膜およ
びプラズマ気相成長法による第２のシリコン酸化膜の４
層構造からなる第２層アルミ配線に対する層間絶縁膜と
を備えること金含む。According to the present invention, a semiconductor device includes a silicon substrate, a field insulating film on the silicon substrate, a first layer of aluminum wiring formed on the field insulating film, and a first layer of aluminum wiring formed on the field insulating film.
A silicon oxide film by sputtering, a first silicon oxide film by plasma vapor deposition, a silicon oxide film by coating, and a second silicon oxide film by plasma vapor deposition are sequentially formed on the entire surface of the substrate including layered aluminum wiring. membrane 4
It also includes an interlayer insulating film for the second layer aluminum wiring having a layered structure.
すなわち、本発明によれば、アルミ配線に直接接触する
絶縁膜には２００”Ｃ以下の温度で且つ化学反応を利用
せずに被着できるスパッタ法のシリコン酸化膜が形成さ
れるので、従来の層間絶縁膜のようにアルミ配線に°′
ヒロック”を生ぜしめたバ或いは゛′アルミ消失”事故
を発生せしめたシするなどの問題点は解決される。すな
わち、アルミ配線の゛ヒロック箋これに直接接触する絶
縁膜の形成温度によって大きく左右されるが２００”Ｃ
以下の場合は発生せず、また、′アルミ消失”現象は反
応ガスと直接接触しなければ生じることはないので、ア
ルミ配線に直接接触する絶縁膜がスパッタ法で形成され
ている場合はこれら力ゞ゛発生ている恐れは全くない。That is, according to the present invention, a silicon oxide film is formed on the insulating film that is in direct contact with the aluminum wiring using a sputtering method that can be deposited at a temperature of 200"C or lower and without using a chemical reaction. °′ for aluminum wiring like interlayer insulation film
Problems such as the crash that caused the "hillock" or the crash that caused the "aluminum disappearance" accident are solved. In other words, it depends largely on the formation temperature of the insulating film that is in direct contact with the aluminum wiring hillock, but the temperature is 20"C.
The following cases will not occur, and the phenomenon of 'aluminum disappearance' will not occur unless there is direct contact with the reaction gas, so if the insulating film that is in direct contact with the aluminum wiring is formed by sputtering, these There is no fear that this is happening.
更にプラズマ気相成長法によるシリコン酸化膜は同じく
プラズマ気相成長のシリコン窒化膜と同程度の段差被覆
性を有し且つその誘電率は後者の約１／２と小さいので
配線の層間容量を大幅に減少せしめ得る。Furthermore, a silicon oxide film produced by plasma vapor phase epitaxy has a step coverage comparable to that of a silicon nitride film produced by plasma vapor phase epitaxy, and its dielectric constant is about 1/2 that of the latter, so it can significantly increase the interlayer capacitance of wiring. can be reduced to
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す配線部分の断面構造図
である。本実施例によれば、本発明の半導体装置は、シ
リコン基板１と、この上面に形成されたフィールド絶縁
膜２と、フィールド絶縁膜３上に形成された第１層アル
ミ配線３と、このアルミ配線３を含む基板全面に順次形
成されたスパッタ法によるシリコン酸化膜４、プラズマ
気相成長法による第１のシリコン酸化膜５、塗布法によ
るシリコン酸化膜６およびプラズマ気相成長法による第
２のシリコン酸化膜７０４層構造からなる眉間絶縁膜と
を含む。すなわち、第１層アルミ配Ｍ３の露出面は化学
反応を利用せずに済み且つ２００″Ｃ程度の温度で被着
できるスパッタ法によるシリコン酸化膜４で被覆され６
アルミ・ヒロックおよび“アルミ消失”の発生がまず防
止される。ついで、第１のシリコン酸化膜５勿この上面
に形成した後段差全通常手段の塗布法によるシリコン酸
化膜６で埋めて平坦化し、更に第２のシリコン酸化膜７
ｔこの上面にプラズマ気相成長法で形成することによっ
て眉間絶縁膜は４層構造に形成される。この際、スルー
・プツトおよびトランジスタ素子の特性劣化等を考慮し
てスパッタ時間金成可く短時間に済ますと共に絶縁膜も
シリコン酸化膜４の形成だけに限ったの又゛みろ。FIG. 1 is a cross-sectional structural diagram of a wiring portion showing an embodiment of the present invention. According to this embodiment, the semiconductor device of the present invention includes a silicon substrate 1, a field insulating film 2 formed on the upper surface of the silicon substrate 1, a first layer aluminum wiring 3 formed on the field insulating film 3, and the aluminum A silicon oxide film 4 formed by sputtering on the entire surface of the substrate including wiring 3, a first silicon oxide film 5 formed by plasma vapor deposition, a silicon oxide film 6 formed by coating, and a second silicon oxide film 6 formed by plasma vapor deposition. It includes a glabella insulating film consisting of a silicon oxide film 704 layered structure. That is, the exposed surface of the first aluminum layer M3 is coated with a silicon oxide film 4 formed by sputtering, which does not require the use of chemical reactions and can be deposited at a temperature of about 200"C.
The occurrence of aluminum hillocks and "aluminum disappearance" is firstly prevented. Next, all the steps formed on the upper surface of the first silicon oxide film 5 are filled and planarized with a silicon oxide film 6 by a conventional coating method, and then a second silicon oxide film 7 is formed.
By forming the glabellar insulating film on this upper surface by plasma vapor deposition, a four-layer structure is formed. At this time, considering the throughput and deterioration of the characteristics of the transistor elements, etc., the sputtering time can be kept as short as possible, and the insulating film is also limited to the formation of the silicon oxide film 4.
この４層構造の層間絶縁膜はアルミ配線３にパヒロック
＃または“アルミ消失”を生せしめないはかシでなく、
全てが誘電率の小さいシリコン酸化膜で作られているの
で配線の層間容量が著しく小さい利点も併わせ有してい
る。This four-layer structure interlayer insulating film is not only reliable but also prevents the aluminum wiring 3 from causing block # or "aluminum disappearance".
Since everything is made of a silicon oxide film with a low dielectric constant, it also has the advantage of extremely low interlayer capacitance of wiring.
以上詳細に説明したように、本発明によれば、アルミ配
線に′°ヒロック”および１アルミ消失”を全く生せし
めない層間絶縁膜を備えた半導体装置を得ることができ
るので、多層アルミニウム配線構造半導体装置に実施す
れば、集積度および信頼性の向上に顕著なる効果金臭し
得る。As explained in detail above, according to the present invention, it is possible to obtain a semiconductor device equipped with an interlayer insulating film that does not cause any ``hillocks'' or 1-aluminum loss in aluminum interconnections, so that a multilayer aluminum interconnection structure can be obtained. When applied to semiconductor devices, significant effects can be achieved in improving the degree of integration and reliability.
第１図は本発明の一実施例を示す配線部分の断面構造図
である。
ｌ・・・シリコン基板、２・・・フィールド絶縁層、３
・・・アルミ配線、４・・・スパッタ法によるシリコン
酸化膜、５・・・プラズマ気相成長法による第１のシリ
コン酸化膜、６・・・塗布法によるシリコン酸化膜、７
・・・プラズマ気相成長法による第２のシリコン酸化膜
。
、／
代理人 弁理士 内 原 （晋
１： シリコン基板
２：フィールド羊色）表頃
３ニアルミ配線FIG. 1 is a cross-sectional structural diagram of a wiring portion showing an embodiment of the present invention. l...Silicon substrate, 2...Field insulating layer, 3
... Aluminum wiring, 4... Silicon oxide film by sputtering method, 5... First silicon oxide film by plasma vapor deposition method, 6... Silicon oxide film by coating method, 7
...Second silicon oxide film formed by plasma vapor phase epitaxy. , / Agent Patent Attorney Hara Uchi (Shin 1: Silicon substrate 2: Field sheep color) Front side 3 Ni-aluminum wiring
Claims (1)
膜と、前記フィールド絶縁膜上に形成される第１層のア
ルミ配線と、前記第１層アルミ配線を含む基板全面に順
次形成されるスパッタ法によるシリコン酸化膜、プラズ
マ気相成長法による第１のシリコン酸化膜、塗布法によ
るシリコン酸化膜およびプラズマ気相成長法による第２
のシリコン酸化膜の４層構造からなる第２層アルミ配線
に対する層間絶縁膜とを備えることを特徴とする半導体
装置。A silicon substrate, a field insulating film on the silicon substrate, a first layer of aluminum wiring formed on the field insulating film, and silicon formed by sputtering on the entire surface of the substrate including the first layer aluminum wiring in order. Oxide film, first silicon oxide film formed by plasma vapor deposition method, silicon oxide film formed by coating method, and second silicon oxide film formed by plasma vapor phase growth method.
1. A semiconductor device comprising: an interlayer insulating film for a second layer aluminum wiring having a four-layer structure of silicon oxide films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61210244A JPH0611079B2 (en) | 1986-09-05 | 1986-09-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61210244A JPH0611079B2 (en) | 1986-09-05 | 1986-09-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6365646A true JPS6365646A (en) | 1988-03-24 |
| JPH0611079B2 JPH0611079B2 (en) | 1994-02-09 |
Family
ID=16586171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61210244A Expired - Lifetime JPH0611079B2 (en) | 1986-09-05 | 1986-09-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611079B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03283450A (en) * | 1990-03-30 | 1991-12-13 | Toshiba Corp | Semiconductor device |
| JPH04167429A (en) * | 1990-10-30 | 1992-06-15 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5957456A (en) * | 1982-09-27 | 1984-04-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5998534A (en) * | 1982-11-26 | 1984-06-06 | Nec Corp | Semiconductor device |
| JPS6035535A (en) * | 1983-08-08 | 1985-02-23 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6042847A (en) * | 1983-08-18 | 1985-03-07 | Nec Corp | Semiconductor device |
| JPS60136335A (en) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | Multilayer interconnection structure |
| JPS60262443A (en) * | 1984-06-08 | 1985-12-25 | Nec Corp | Forming method of multilayer interconnection |
-
1986
- 1986-09-05 JP JP61210244A patent/JPH0611079B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5957456A (en) * | 1982-09-27 | 1984-04-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5998534A (en) * | 1982-11-26 | 1984-06-06 | Nec Corp | Semiconductor device |
| JPS6035535A (en) * | 1983-08-08 | 1985-02-23 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6042847A (en) * | 1983-08-18 | 1985-03-07 | Nec Corp | Semiconductor device |
| JPS60136335A (en) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | Multilayer interconnection structure |
| JPS60262443A (en) * | 1984-06-08 | 1985-12-25 | Nec Corp | Forming method of multilayer interconnection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03283450A (en) * | 1990-03-30 | 1991-12-13 | Toshiba Corp | Semiconductor device |
| JPH04167429A (en) * | 1990-10-30 | 1992-06-15 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0611079B2 (en) | 1994-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0514417B2 (en) | ||
| JPS62219923A (en) | Manufacture of semiconductor device | |
| JPS6365646A (en) | Semiconductor device | |
| JPH06302704A (en) | Semiconductor device | |
| JPS60119755A (en) | Semiconductor integrated circuit device with multilayered wiring | |
| JPH07147281A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2884100B2 (en) | Semiconductor device | |
| JPH02183536A (en) | Semiconductor device | |
| JP3099381B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6325952A (en) | Semiconductor device | |
| JPS6151848A (en) | Manufacture of semiconductor device | |
| JPH1187496A (en) | Manufacture of semiconductor device | |
| JPS60113444A (en) | Multilayer interconnection structure | |
| JPH0794583A (en) | Fabrication of semiconductor integrated circuit device | |
| JPH0529481A (en) | Semiconductor device | |
| JPH056939A (en) | Manufacture of semiconductor device | |
| JPH04255249A (en) | Manufacture of semiconductor device | |
| JPH06120166A (en) | Manufacture of semiconductor device | |
| JPH0122984B2 (en) | ||
| JPS5950517A (en) | Semiconductor device | |
| JPS62245641A (en) | Structure of pad part of semiconductor device | |
| JPH05152444A (en) | Manufacture of semiconductor device | |
| JPH0291968A (en) | Manufacture of memory device | |
| JPS63164241A (en) | Manufacture of semiconductor device | |
| JPH03126246A (en) | Semiconductor device |