JPS6325952A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6325952A JPS6325952A JP16911486A JP16911486A JPS6325952A JP S6325952 A JPS6325952 A JP S6325952A JP 16911486 A JP16911486 A JP 16911486A JP 16911486 A JP16911486 A JP 16911486A JP S6325952 A JPS6325952 A JP S6325952A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- interlayer insulating
- organic
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 125000005375 organosiloxane group Chemical group 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 238000000576 coating method Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、有機系絶縁膜を層間
絶縁膜に用いた多層配線構造を有する半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a multilayer wiring structure using an organic insulating film as an interlayer insulating film.
多層配線構造を有する半導体装置においては、特に上層
配線の断線防止のため層間絶縁膜の平坦化が必要となっ
てきている。In a semiconductor device having a multilayer wiring structure, it has become necessary to planarize an interlayer insulating film, especially to prevent disconnection of upper layer wiring.
平坦化法としては突出部を除去するエツチング法、下層
配線上に平坦な絶縁膜を形成するバイアススパッタ法、
絶縁物溶液を塗布する塗布法等があるが、塗布法は比較
的プロセスが簡単である。Planarization methods include etching to remove protrusions, bias sputtering to form a flat insulating film on the underlying wiring,
There are coating methods that apply an insulating solution, but the coating method is a relatively simple process.
しかし無機系の塗布液を用いた場合、クラックが入るた
め厚く塗布することが出来ないため、十分な平坦性が得
られない。そのため有機系の塗布膜の使用が考えられる
が、単独で層間絶縁膜として使用する場合信頼性上問題
がある。However, when an inorganic coating liquid is used, it is not possible to apply a thick coating due to cracks, and therefore sufficient flatness cannot be obtained. Therefore, it is possible to use an organic coating film, but if it is used alone as an interlayer insulating film, there is a problem in terms of reliability.
すなわち、吸水性による下層配線への影響、不純物によ
るデバイス特性への影響等である。That is, the influence of water absorption on lower layer wiring, the influence of impurities on device characteristics, etc.
これらの問題点を解決するために、信頼性のある無機絶
縁膜、例えばＣＤＶ法による酸化シリコン膜や窒化シリ
コン膜等を下層配線形成後の基板全面に形成し、次に有
機絶縁膜を形成し、再び前記と同様の無機絶縁膜を形成
して３層構造の層間絶縁膜を設けることにより、上述し
た代願性上の問題点を解決することが提案され実施され
ている。In order to solve these problems, a reliable inorganic insulating film, such as a silicon oxide film or a silicon nitride film, is formed using the CDV method over the entire surface of the substrate after forming the lower layer wiring, and then an organic insulating film is formed. It has been proposed and implemented to solve the above-mentioned problems regarding application by forming an inorganic insulating film similar to that described above again to provide an interlayer insulating film having a three-layer structure.
しかしながら、上述した３層構造の層間絶縁膜を用いる
場合、層間絶縁膜を形成した後下層配線と上層配線の接
続をとるためのスルーホールを設け、しかる後上層配線
金属を例えばスパッタ蒸着するわけであるが、その後、
熱によって有機絶縁膜中にガスが発生する場合がある。However, when using the above-mentioned three-layer interlayer insulating film, after forming the interlayer insulating film, a through hole is provided for connecting the lower layer wiring and the upper layer wiring, and then the upper layer wiring metal is deposited by sputtering, for example. Yes, but then,
Gas may be generated in the organic insulating film due to heat.
有機絶縁膜はその上部を無機絶縁膜により覆われている
ため発生したガスは有機絶縁膜中を移動し、スルーホー
ルから噴出して上層配線金属の蒸着を妨げ、スルーホー
ルにおける上層配線の信頼性を低下させ、半導体装置の
歩留りを低下させるという問題点がある。Since the organic insulating film is covered with an inorganic insulating film, the generated gas moves through the organic insulating film and ejects from the through-hole, interfering with the vapor deposition of the upper-layer wiring metal, thereby reducing the reliability of the upper-layer wiring in the through-hole. There is a problem in that the yield rate of semiconductor devices is lowered.
本発明の目的は、信頼性の向上した多層配線構造の半導
体装置を提供することにある。An object of the present invention is to provide a semiconductor device having a multilayer interconnection structure with improved reliability.
本発明の半導体装置は、第１の無機絶縁膜と有機絶縁膜
と第２の無機絶縁膜とが順次形成されてなる３層構造の
層間絶縁膜を有する多層配線構造の半導体装置であって
、前記３層構造の層間絶縁膜には配線に接続せず、かつ
少くとも前記有機絶縁膜に達する開孔部が設けられてい
るものである。The semiconductor device of the present invention is a multilayer wiring structure semiconductor device having an interlayer insulating film having a three-layer structure in which a first inorganic insulating film, an organic insulating film, and a second inorganic insulating film are sequentially formed, The interlayer insulating film of the three-layer structure is provided with an opening that is not connected to the wiring and reaches at least the organic insulating film.
し実施例〕 次に本発明の実施例を図面を参照して説明する。Example] Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）（ｂ）は本発明の一実施例の平面図及びＡ
−Ａ′線断面図である。FIGS. 1(a) and 1(b) are plan views of one embodiment of the present invention and A
-A' line sectional view.
第１図（ａ）、（ｂ）において、半導体基板１上に形成
された５ｉ０２等からなる絶縁膜２上に、例えば厚さ約
１．０μｍの下層のアルミニウム配線３を形成する。次
に半導体基板１全面に、例えばプラズマＣＶＤ法を用い
て第１の窒化シリコン膜４を約０．２μｍの厚さに成長
させる。In FIGS. 1A and 1B, on an insulating film 2 made of 5i02 or the like formed on a semiconductor substrate 1, a lower aluminum wiring 3 having a thickness of, for example, about 1.0 μm is formed. Next, a first silicon nitride film 4 is grown to a thickness of about 0.2 μm over the entire surface of the semiconductor substrate 1 using, for example, plasma CVD.
次にオルガノシロキサン樹脂溶液を塗布し焼成して有機
絶縁膜５を形成したのち、その表面に再びプラズマＣＶ
Ｄ法を用いて第２の窒化シリコン膜６を約０．５μｍの
厚さに成長させて３層構造の層間絶縁膜２０を設ける。Next, an organosiloxane resin solution is applied and fired to form an organic insulating film 5, and then the surface is again coated with plasma CV.
A second silicon nitride film 6 is grown to a thickness of about 0.5 μm using the D method to provide an interlayer insulating film 20 having a three-layer structure.
しかる後に通常のフォトリソグラフィー 法およびエツ
チング法によりスルーホール１０を開孔するがここで、
下層のアルミニウム配線３．上層のアルミニウム配線７
のいずれかにも接続しない開孔部９を同時に設ける。こ
の開孔部９の深さは少くとも有機絶縁膜５に達するよう
に形成し、第１の窒化シリコン膜４を貫通しないことが
望ましい。Thereafter, the through hole 10 is opened using the usual photolithography method and etching method.
Lower layer aluminum wiring 3. Upper layer aluminum wiring 7
At the same time, an opening 9 is provided which is not connected to any of the above. It is desirable that the depth of the opening 9 is so formed that it reaches at least the organic insulating film 5 and does not penetrate the first silicon nitride film 4.
次に全面にパッシベーション膜８としてＣＶＤ法により
窒化シリコン膜を約１．５μｍの厚さに成長させ開孔部
９からの水分の侵入を防ぐ。Next, a silicon nitride film is grown as a passivation film 8 on the entire surface by CVD to a thickness of about 1.5 μm to prevent moisture from entering through the openings 9.
このように構成された本実施例においては、３層構造を
有する層間絶縁膜２０に少くとも有機絶縁膜５に達する
開孔部９が設けられているため、後工程で有機絶縁膜中
に発生するガスはこの開孔部９からも噴出する。従って
スルーホールからのガスの噴出は低減されるなめ、スル
ーホール１０における上層のアルミニウム配線の形成は
容易となる。In this embodiment configured in this way, the interlayer insulating film 20 having a three-layer structure is provided with the openings 9 that reach at least the organic insulating film 5. The gas is also ejected from this opening 9. Therefore, gas ejection from the through hole is reduced, and the formation of the upper layer aluminum wiring in the through hole 10 is facilitated.
尚、上記実施例におけては有機絶縁膜としてオルガノシ
ロキサン樹脂を用いた場合について説明したが、ポリイ
ミド樹脂等の有機樹脂を用いてもよい。In the above embodiments, the case where organosiloxane resin was used as the organic insulating film was described, but organic resin such as polyimide resin may also be used.
以上説明したように本発明は、第１の無機絶縁膜と有機
絶縁膜と第２の無機絶縁膜とからなる３層構造の層間絶
縁膜に、配線に接続せずかつ少くとも有機絶縁膜に達す
る開孔部を設けることにより、有機絶縁膜中に発生する
ガスをこの開孔部から除去することができるため、下層
配線上の層間絶縁膜に設けたスルーホールからのガスの
噴出は低減され、このスルーホールに形成される上層配
線は信頼性の高いものとなる。従って信頼性及び歩留り
の向上した多層配線構造を有する半導体装置が得られる
。As explained above, the present invention provides an interlayer insulating film having a three-layer structure consisting of a first inorganic insulating film, an organic insulating film, and a second inorganic insulating film, without being connected to wiring, and at least in the organic insulating film. By providing an opening that extends through the organic insulating film, gas generated in the organic insulating film can be removed from the opening, thereby reducing gas ejection from the through hole provided in the interlayer insulating film on the lower wiring. , the upper layer wiring formed in this through hole becomes highly reliable. Therefore, a semiconductor device having a multilayer wiring structure with improved reliability and yield can be obtained.
【図面の簡単な説明】
第１図（ａ）、（ｂ）は本発明の一実施例の平面図、及
びＡ−Ａ′線断面図である。
１・・・半導体基板、２・・・絶縁膜、３・・・下層の
アルミニウム配線、４・・・第１の窒化シリコン膜、５
・・・有機絶縁膜、６・・・第２の窒化シリコン膜、７
・・・上層のアルミニウム配線、８・・・パッシベーシ
ョン膜、９・・・開孔部、１０・・・スルーホール、２
０・・・層間絶縁膜。
竿 ｌ 図BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Lower layer aluminum wiring, 4... First silicon nitride film, 5
...Organic insulating film, 6...Second silicon nitride film, 7
... Upper layer aluminum wiring, 8... Passivation film, 9... Opening part, 10... Through hole, 2
0...Interlayer insulating film. rod l diagram
Claims (1)
が順次形成されてなる３層構造の層間絶縁膜を有する多
層配線構造の半導体装置において、前記３層構造の層間
絶縁膜には配線に接続せず、かつ少くとも前記有機絶縁
膜に達する開孔部が設けられていることを特徴とする半
導体装置。In a semiconductor device having a multilayer wiring structure having an interlayer insulating film having a three-layer structure in which a first inorganic insulating film, an organic insulating film, and a second inorganic insulating film are sequentially formed, the interlayer insulating film having the three-layer structure 1. A semiconductor device, wherein the semiconductor device is provided with an opening that is not connected to wiring and that reaches at least the organic insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16911486A JPS6325952A (en) | 1986-07-17 | 1986-07-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16911486A JPS6325952A (en) | 1986-07-17 | 1986-07-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6325952A true JPS6325952A (en) | 1988-02-03 |
Family
ID=15880558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16911486A Pending JPS6325952A (en) | 1986-07-17 | 1986-07-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6325952A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121570A (en) * | 1991-10-25 | 1993-05-18 | Nec Corp | Semiconductor device |
| US6650002B1 (en) | 1997-04-24 | 2003-11-18 | Sharp Kabushiki Kaishi | Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film |
| US7667332B2 (en) | 2004-11-05 | 2010-02-23 | Kabushiki Kaisha Toshiba | Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product |
-
1986
- 1986-07-17 JP JP16911486A patent/JPS6325952A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121570A (en) * | 1991-10-25 | 1993-05-18 | Nec Corp | Semiconductor device |
| US6650002B1 (en) | 1997-04-24 | 2003-11-18 | Sharp Kabushiki Kaishi | Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film |
| US7667332B2 (en) | 2004-11-05 | 2010-02-23 | Kabushiki Kaisha Toshiba | Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product |
| US7996813B2 (en) | 2004-11-05 | 2011-08-09 | Kabushiki Kaisha Toshiba | Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program |
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