JPS62274641A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS62274641A
JPS62274641A JP11950186A JP11950186A JPS62274641A JP S62274641 A JPS62274641 A JP S62274641A JP 11950186 A JP11950186 A JP 11950186A JP 11950186 A JP11950186 A JP 11950186A JP S62274641 A JPS62274641 A JP S62274641A
Authority
JP
Japan
Prior art keywords
film
bpsg
insulating film
semiconductor device
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11950186A
Other languages
Japanese (ja)
Other versions
JP2512900B2 (en
Inventor
Hajime Arai
新井 肇
Katsuhiro Hirata
勝弘 平田
Junichi Arima
純一 有馬
Masaaki Ikegami
雅明 池上
Hiroshi Mochizuki
望月 弘
Reiji Tamaki
礼二 玉城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61119501A priority Critical patent/JP2512900B2/en
Publication of JPS62274641A publication Critical patent/JPS62274641A/en
Application granted granted Critical
Publication of JP2512900B2 publication Critical patent/JP2512900B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent direct contact of a BPSG film with a substrate and an interconnection layer including a contact part, by covering the lower layer of the BPSG film as a smooth coating film with an underlay film, and covering the upper layer by an insulating film other than said BPSG film. CONSTITUTION:On a silicon semiconductor substrate 1, a first underlay oxide film 2, a PSG film 3 as a second underlay insulating film and a BPSG film 4 as a smooth coating film are sequentially formed. An opening 7a, which has a slightly larger size, is provided by an anisotropic etching in the parts of the surface of the BPSG film 4 and the PSG film 3. Then, by the reflow treatment of the BPSG film 4, the surface side facing the opening 7a is made to be the gentle curved surface. After an SOG film 5 is applied and formed thereon, an opening is provided at specified dimensions in the SOG film 5, the BPSG film 4, the PSG film 3 and the underlay oxide film 2 by anisotropic etching. Thus a contact hole 7 is formed. In this way, the BPSG film 4 as the smooth coating film is completely covered with the lower PSG film 3 and the upper SOG film 5.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 この発明は、半導体装置およびその製造方法に関し、さ
らに詳しくは、半導体装置におけるコンタクトホール構
造の形成手段の改良に係るものである。
[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly relates to an improvement in a means for forming a contact hole structure in a semiconductor device. It is something.

〔従来の技術〕[Conventional technology]

従来から、半導体装置に形成されるところの。 Conventionally, it has been formed in semiconductor devices.

いわゆるスムースコート膜としては、一般にPSG(P
hospho−si Iicate−glass)によ
る絶縁膜が用いられている。このPSG膜は、アルカリ
金属のゲッタリングおよびブロッキングの作用をもち、
しかもシリコン基板とか配線材料に悪影響を与える惧れ
もないなど、スムースコート膜としての優れた特性を有
しており、また一方では、現在、半導体装置での高速化
、微細化への要求が一層高まるにつれて、接合のシャロ
ー化が必要となり、リフロ一工程での低温化を意図して
、BPJG(Boro−phaspho−s i l 
icate−g 1ass)膜の導入が進みつ−ある。
The so-called smooth coat film is generally made of PSG (P
An insulating film made of phospho-silicate-glass is used. This PSG film has alkali metal gettering and blocking functions,
Furthermore, it has excellent properties as a smooth coat film, such as having no adverse effects on silicon substrates or wiring materials.On the other hand, there is currently a growing demand for higher speeds and smaller sizes in semiconductor devices. As the temperature increases, it becomes necessary to make the bond shallower, and BPJG (Boro-phaspho-sil) is used to reduce the temperature in the reflow process.
The introduction of icate-g 1ass) membranes is progressing.

ご覧で、従来例でのこの種のBPSGHによるスムース
コート膜をもつ半導体装置でのコンタクト部の概要断面
構造を第6図に示す。
For your reference, FIG. 6 shows a schematic cross-sectional structure of a contact portion in a conventional semiconductor device having a smooth coat film made of this type of BPSGH.

すなわち、この第6図従来例によるコンタクトホール構
造においては、よく知られている通り、まず、CVD(
C:hemical−Vapour−Depositi
on、化学気相成長法)装置を用い、シリコン半導体基
板1の下敷き酸化膜2上に、前記したスムースコート膜
としてのBPSG膜4を形成させ、ついで、異方性エツ
チングなどによって、コンタクトホール7を開口させ、
さらにその後、リフロー処理を行なうことで、コンタク
トホール7の開口形状を良好に処理してから、図示省略
したがスパッタリングなどにより、 A文−Siなどの
配線層を形成するのである。
That is, in the contact hole structure according to the conventional example shown in FIG. 6, first, as is well known, CVD (
C: Chemical-Vapour-Deposit
The BPSG film 4 as the smooth coat film described above is formed on the underlying oxide film 2 of the silicon semiconductor substrate 1 using a chemical vapor deposition method (on, chemical vapor deposition method), and then the contact hole 7 is formed by anisotropic etching or the like. Open the
Further, after that, a reflow process is performed to properly shape the opening of the contact hole 7, and then a wiring layer such as A-Si is formed by sputtering or the like (not shown).

すなわち、この場合、前記スムースコート膜としてPS
G膜よりもBPSG膜のほうが、装置構成の高速化、微
細化に適しているのは、前記リフロ一工程での温度が低
くてすみ、従って接合深さを浅く保ち得るからである。
That is, in this case, PS is used as the smooth coat film.
The reason why the BPSG film is more suitable for speeding up and miniaturizing the device configuration than the G film is that the temperature in the reflow process can be lowered, and therefore the junction depth can be kept shallow.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、一方、前記BPSGI]I4を用いたス
ムースコート膜によるコンタクトホール7の構造では、
そのリフロー処理に際して、第6図に符号6で示した部
分に見られるように、BPSG膜4のブレのために、こ
れがシリコン基板lに直接々触する部分を生じて、この
部分6からBPS(i膜4中のボロン、リンなどが、基
板l中に、またコンタクトに析出されたシリコン中にそ
れぞれ拡散されてゆき、結果的に一方では、コンタクト
部にオーミック不良を発生すると云う不都合があり、ま
た他方では、 Au−5iなどの配線層に対してBPS
G膜4が接触されるために、配線層中にもボロン、リン
However, on the other hand, in the structure of the contact hole 7 made of the smooth coat film using BPSGI]I4,
During the reflow process, as seen in the part 6 shown in FIG. Boron, phosphorus, etc. in the i-film 4 are diffused into the substrate l and into the silicon deposited on the contact, and as a result, on the one hand, there is an inconvenience that an ohmic failure occurs in the contact part. On the other hand, BPS is used for wiring layers such as Au-5i.
Since the G film 4 is in contact, boron and phosphorus are also present in the wiring layer.

シリコンなどが拡散されて、コンタクト部に析出するな
どの好ましくない問題点があった。
There were undesirable problems such as silicon and the like being diffused and precipitated in the contact area.

この発明は従来のこのような問題点を解消するためにな
されたものであって、その目的とするところは、 BP
SGによるスムースコート膜を用いた半導体装置におい
て、同BPSGIljJが、シリコン基板。
This invention was made to solve these conventional problems, and its purpose is to
In a semiconductor device using a smooth coat film made of SG, BPSGIljJ is a silicon substrate.

およびコンタクト部を含む配線層に直接々触することの
ないようにした。この種の半導体装置およびその製造方
法を得ることである。
Also, the wiring layer including the contact portion was prevented from being directly touched. An object of the present invention is to obtain a semiconductor device of this type and a method for manufacturing the same.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するために、この発明に係る半導体装置
およびその製造方法は、スムースコート膜としてのBP
SG膜の下層を下敷き膜、上層をこのBPSG膜以外の
絶縁膜により、それぞれに被覆させるようにしたもので
ある。
In order to achieve the above object, a semiconductor device and a method for manufacturing the same according to the present invention are provided using BP as a smooth coat film.
The lower layer of the SG film is covered with an underlay film, and the upper layer is covered with an insulating film other than the BPSG film.

〔作   用〕[For production]

すなわち、この発明においては、BPSG膜によるスム
ースコート膜の下層に下敷き膜、上層にBPSG膜以外
の絶縁膜をそれぞれに被覆させて、 BPSG膜からの
シリコン基板中、およびコンタクト部を含む配線層中へ
の、ボロン、リン、シリコンなどの拡散と析出を避ける
ようにしたから、コンタクト部での接続不良を改善でき
、低温リフローが可能であると云う、 BPSGII@
によるスムースコート膜での特長を充分に活用し得るの
である。
That is, in the present invention, the lower layer of the smooth coat film made of the BPSG film is coated with an underlayer film, and the upper layer is coated with an insulating film other than the BPSG film, and the inside of the silicon substrate from the BPSG film and the wiring layer including the contact portion are coated. By avoiding the diffusion and precipitation of boron, phosphorus, silicon, etc. in the BPSG II, poor connection at the contact area can be improved and low-temperature reflow is possible.
This makes it possible to fully utilize the features of the smooth coat film.

〔実 施 例〕〔Example〕

以下、この発明に係る半導体装置およびその製造方法の
実施例につき、第1図ないし第5図を参照して詳細に説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to FIGS. 1 to 5.

第1図はこの発明の一実施例を適用したBPSG膜によ
るスムースコート膜をもつ半導体装置のコンタクト部を
示す概要断面図であり、この第1図実施例装置において
、前記第6図従来例装置と同一符号は同一または相当部
分を示している。
FIG. 1 is a schematic sectional view showing a contact portion of a semiconductor device having a smooth coat film made of a BPSG film to which an embodiment of the present invention is applied. The same reference numerals indicate the same or equivalent parts.

この第1図実施例装置では、前記BPSG膜4の形成に
先立って、前記下敷き酸化膜2上に第2の下敷き絶縁膜
31例えば前記したPSG膜を形成させ、またこの下敷
き絶縁膜3を下層としてBPSG膜4の形成後、コンタ
クトホール7に接する部分を含めた上層に絶縁膜59例
えば5OG(Spin−on−Glass)膜を被覆さ
せたものである。
In the apparatus of the embodiment shown in FIG. 1, prior to the formation of the BPSG film 4, a second underlay insulating film 31, for example, the above-mentioned PSG film, is formed on the underlay oxide film 2, and this underlay insulating film 3 is After forming the BPSG film 4, the upper layer including the portion in contact with the contact hole 7 is covered with an insulating film 59, for example, a 5OG (Spin-on-Glass) film.

こ−で、前記SOG膜とは、二酸化硅素(Si02)を
有機溶剤に溶融させた溶液を基板上に滴下させ、かつ同
基板をスピンさせる手法、いわゆるスピンコート法によ
って形成したシリコン酸化膜を指している。
Here, the SOG film refers to a silicon oxide film formed by a so-called spin coating method, in which a solution of silicon dioxide (Si02) dissolved in an organic solvent is dropped onto a substrate and the substrate is spun. ing.

しかして、第2図(a)ないしくd)には、前記第1図
実施例構成での製造プロセスフローの概要を示しである
FIGS. 2(a) to 2d) outline the manufacturing process flow in the configuration of the embodiment shown in FIG. 1.

すなわち、まず、前記シリコン半導体基板1上にあって
、第1の下敷き酸化膜2.第2の下敷き絶縁膜、ご覧で
はPSGSaO2たスムースコート膜としてのBPSG
膜4を順次に形成させた上で、異方性エツチングにより
、このBPSGljJ4.それにPSGSaO2面一部
を、選択的にや−太き目の寸法で開ロアaさせる(同図
(a))、続いて、前記BPSG膜4のリフロー処理に
より、開ロアaに面した表面側をなだらかな曲面としく
同図(b))、かつその上にSOG膜5を塗布形成した
後(同図(C))、さらに異方性エツチングにより、こ
れらのSOG膜5.BPSG膜4. PSGSaO2れ
に下敷き酸化膜2を、それぞれ選択的に所期寸法通りに
開口させてコンタクトホール7を形成させるのである(
同図(d))。
That is, first, on the silicon semiconductor substrate 1, a first underlying oxide film 2. The second underlying insulating film, shown here is BPSG as a smooth coat film with PSGSaO2.
After sequentially forming the films 4, this BPSGljJ4. Then, a part of the PSGSaO2 surface is selectively opened lower a with a slightly thicker dimension ((a) in the same figure), and then the surface side facing the open lower a is subjected to reflow treatment of the BPSG film 4. After forming the SOG film 5 into a gently curved surface (FIG. 5(b)) and coating the SOG film 5 thereon (FIG. 2(C)), the SOG film 5 is further etched by anisotropic etching. BPSG film 4. PSGSaO2 is then selectively opened in the underlying oxide film 2 to the desired dimensions to form contact holes 7 (
Figure (d)).

従って、このようにして得た第1図実施例装置では、ス
ムースコート膜としてのBPSGIIQ4 カ、下層の
PSGSaO2層のSOG膜5とによって完全に被覆さ
れることになり、その結果として、こ!では、従来と同
様の低温処理で良好な形状のコンタクト構造を得ること
ができる。
Therefore, in the device of the embodiment shown in FIG. 1 obtained in this way, the smooth coat film BPSGIIQ4 is completely covered with the SOG film 5 of the underlying PSGSaO2 layer, and as a result, this! In this case, a contact structure with a good shape can be obtained by low-temperature processing similar to the conventional method.

また、第3図(a)ないしくe)には、他の実施例によ
る製造プロセスフローの概要を示してあり、この第3図
実施例構成においては、前記第1図実施例構成と同様に
スムースコート膜としてのBPSG膜4を完全に被覆す
るが、下層に下敷き酸化膜2のみを用いた場合である。
In addition, FIGS. 3(a) to 3(e) show an outline of the manufacturing process flow according to another embodiment, and the configuration of this embodiment in FIG. 3 is similar to the configuration of the embodiment in FIG. This is a case where the BPSG film 4 as a smooth coat film is completely covered, but only the underlying oxide film 2 is used as the lower layer.

すなわち、まず、シリコン基板lの下敷き酸化膜2上に
あって、スムースコート膜としてのBPSG膜4を形成
させ、かつその表面の一部を異方性エツチングにより、
選択的にや〜大き目の寸法で開ロアaさせるが、このと
き下敷き酸化膜2の該当部分も同時に失なわれる(同図
(a))。そしてこのま−リフローをかけると、前記B
PSG膜4のダレによって、これが基板1に接触する可
能性があるために、下敷き酸化膜2の開口?a、つまり
コンタクト該当部分に再度、酸化膜を形成しく同図(b
))だ上で、リフロー処理により、開ロアaに面した表
面側をなだらかな曲面としく同図(C))、かつその上
にSOG膜5を塗布形成した後(同図(d))、さらに
異方性エツチングによって、これらの5OGIIQ 5
 、BPSG■々4.それに下敷き酸化膜2を、それぞ
れ選択的に所期寸法通りに開口させてコンタクトホール
7を形成させるのである(同図(e))。
That is, first, a BPSG film 4 as a smooth coat film is formed on the underlying oxide film 2 of the silicon substrate l, and a part of its surface is anisotropically etched.
The lower opening a is selectively opened to a slightly larger dimension, but at this time, the corresponding portion of the underlying oxide film 2 is also lost (FIG. 4(a)). Then, when reflow is applied, the above B
Since there is a possibility that the PSG film 4 may come into contact with the substrate 1 due to sagging, the opening in the underlying oxide film 2 may be removed. In the same figure (b), an oxide film is again formed on the contact area.
)), the surface facing the open lower a is made into a gently curved surface by reflow treatment (Figure (C)), and the SOG film 5 is coated thereon (Figure (D)). , further by anisotropic etching, these 5OGIIQ 5
, BPSG■4. Then, contact holes 7 are formed by selectively opening the underlying oxide film 2 according to the desired dimensions (FIG. 4(e)).

のって、この第3図実施例装置の場合にも、スムースコ
ート膜としてのBPSG膜4が、下層の下敷き酸化膜2
と上層のSOG膜5とによって完全に被覆されることに
なり、こ−でも、従来と同様の低温処理で良好な形状の
コンタクト構造を得ることができるのである。
Therefore, also in the case of the device according to the embodiment shown in FIG.
The contact structure is completely covered with the upper layer SOG film 5, and a contact structure with a good shape can be obtained by low-temperature processing similar to the conventional method.

なお、前記BPSGI莫4の下層膜には、 PSG膜に
代えて窒化膜、プラズマ窒化膜、その他酸化膜などのC
vD絶縁膜を、また上層膜には、 SOG膜に代えて窒
化膜、プラズマ窒化膜、その他酸化膜などのCvD絶縁
膜を利用してもよく、同様な作用、効果を奏し得るもの
で、この上層膜にCvD絶縁膜を使用した場合の概要断
面構造による実施例、変形例装置をそれぞれ第4図、第
5図に示してあり、さらに、装置のバリア性能に対する
要求次第によっては、これらの下層膜、上層膜を多層化
することも可能である。
Note that the lower layer film of the BPSGI Mo4 is a C nitride film, plasma nitride film, or other oxide film instead of the PSG film.
In place of the SOG film, a CvD insulating film such as a nitride film, plasma nitride film, or other oxide film may be used as the upper layer film, and the same action and effect can be achieved. 4 and 5 show schematic cross-sectional structures of an embodiment and a modified device in which a CvD insulating film is used as the upper layer film, respectively. It is also possible to form a multilayer film and an upper film.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、この発明によるときは、スムース
コート膜としてボロンを含むリンガラスlfi (BP
SG膜)を用いた半導体装置のコンタクトホール構造に
おいて、 BPSG膜を下層絶縁膜および上層絶縁膜に
より完全に被覆させた状態でコンタクトホールを開口さ
せ、このBPSG膜が半導体基板。
As detailed above, according to the present invention, phosphorus glass lfi (BP) containing boron is used as the smooth coat film.
In a contact hole structure for a semiconductor device using a BPSG film (SG film), a contact hole is opened while the BPSG film is completely covered with a lower insulating film and an upper insulating film, and this BPSG film is used as a semiconductor substrate.

およびコンタクトホールを通した配線接続部、ならびに
配線層に直接々触することのないようにしたから、この
種の装置構成での、 BPSG膜から基板部、配線部へ
のボロン、リン、シリコンなどノ析出による影響を排除
、もしくは抑制した状態で、装置構成にとって好ましい
低温処理により、良好なコンタクト構造を得ることがで
き、しかも構造的にも比較的簡単で容易に実施できるな
どの優れた特長を有するものである。
In this type of device configuration, boron, phosphorus, silicon, etc. can be transferred from the BPSG film to the substrate part and the wiring part, since it is prevented from directly touching the wiring connection part through the contact hole and the wiring layer. It has excellent features such as being able to obtain a good contact structure through low-temperature treatment that is favorable for the device configuration while eliminating or suppressing the effects of precipitation, and also being relatively simple in structure and easy to implement. It is something that you have.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を適用したBPSG膜によ
るスムースコート膜をもつ半導体装置のコンタクトホー
ル部を示す概要断面図、第2図(a)ないしくd)は同
上第1図実施例装置の製造プロセスフローの概要を示す
それぞれ概要断面図、また第3図(a)ないしくe)は
同上他の実施例による装置製造プロセスフローの概要を
示すそれぞれ概要断面図、第4図および第5図はさらに
他の実施例および変形例による半導体装置のコンタクト
ホール部を示す概要断面図であり、また第6図は従来例
による同上半導体装置のコンタクトホール部を示す概要
断面図である。 1・・・・シリコン半導体基板、2・・・・下敷き酸化
膜、3・・・・BPSGII5Iの下層膜(下敷き膜)
、4・・・・スムースコート膜としてのBPSG膜(ボ
ロンを含むリンガラス膜)、5・・・・BPSG膜の上
層膜、7・・・・コンタクトホール開口。 第1図 1:シリコンも譚欄鞠寒久( (爪゛ロア2合仁ソ/〃パう入賎p 5:BPSG月炎−」ニノを飛跳、 7:コ〉/クトネーlし開口 第2図 (a) a (b) (C) (d) 第3図 7a 第4図 °第5 図 第6図
FIG. 1 is a schematic sectional view showing a contact hole portion of a semiconductor device having a smooth coat film made of a BPSG film to which an embodiment of the present invention is applied, and FIGS. 2(a) to d) are the embodiments shown in FIG. FIGS. 3(a) to 3(e) are schematic sectional views showing an overview of the manufacturing process flow of the device, and FIGS. FIG. 5 is a schematic cross-sectional view showing a contact hole portion of a semiconductor device according to still another embodiment and a modified example, and FIG. 6 is a schematic cross-sectional view showing a contact hole portion of the same semiconductor device according to a conventional example. 1... Silicon semiconductor substrate, 2... Underlay oxide film, 3... BPSGII5I lower layer film (underlay film)
, 4... BPSG film (phosphorus glass film containing boron) as a smooth coat film, 5... Upper layer film of the BPSG film, 7... Contact hole opening. Figure 1 1: Silicon is also tanran Mari Kankyu ((Tsume Roa 2 Gojinso/〃Pauiri p. 5: BPSG Moon Flame-'' Jumping over Nino, 7: Ko〉/Kutonel and Opening Diagram 2 (a) a (b) (C) (d) Fig. 3 7a Fig. 4 ° Fig. 5 Fig. 6

Claims (6)

【特許請求の範囲】[Claims] (1)スムースコート膜としてボロンを含むリンガラス
膜(BPSG膜)を用いた半導体装置のコンタクトホー
ル構造において、前記BPSG膜を下層絶縁膜および上
層絶縁膜により被覆させ、このBPSG膜が半導体基板
、コンタクトホールを通した配線接続部、ならびに配線
層に直接々触しないようにしたことを特徴とする半導体
装置。
(1) In a contact hole structure of a semiconductor device using a phosphorus glass film (BPSG film) containing boron as a smooth coat film, the BPSG film is covered with a lower layer insulating film and an upper layer insulating film, and this BPSG film is used as a semiconductor substrate, A semiconductor device characterized in that a wiring connection portion through a contact hole and a wiring layer are not directly touched.
(2)下層絶縁膜が、リンガラス膜(PSG膜)、また
は窒化膜、プラズマ窒化膜、酸化膜などの絶縁膜である
特許請求の範囲第1項に記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the lower layer insulating film is an insulating film such as a phosphorus glass film (PSG film), a nitride film, a plasma nitride film, or an oxide film.
(3)上層絶縁膜が、スピンコート法によるシリコン酸
化膜、または化学気相成長法による窒化膜、プラズマ窒
化膜、酸化膜などの絶縁膜である特許請求の範囲第1項
または第2項に記載の半導体装置。
(3) According to claim 1 or 2, the upper insulating film is an insulating film such as a silicon oxide film formed by spin coating, a nitride film, a plasma nitride film, or an oxide film formed by chemical vapor deposition. The semiconductor device described.
(4)スムースコート膜としてボロンを含むリンガラス
膜(BPSG膜)を用いた半導体装置のコンタクトホー
ル構造において、半導体基板の下敷き酸化膜を下層絶縁
膜として、その上に直接、または必要に応じ第2の下層
絶縁膜を介してBPSG膜を形成させ、かつこのBPS
G膜、ないしは第2の下層絶縁膜の表面一部を、選択的
にやゝ大き目の寸法で開口させる工程と、前記BPSG
膜をリフロー処理する工程と、これらの上に上層絶縁膜
を形成する工程と、これらの各上層絶縁膜、BPSG膜
、ないしは第2の下層絶縁膜、および下層絶縁膜の前記
開口対応部分を、それぞれ選択的に所期寸法通りに開口
させてコンタクトホールを形成させる工程とを含み、前
記BPSG膜を前記半導体基板、コンタクトホールを通
した配線接続部、ならびに配線層に直接々触しないよう
にしたことを特徴とする半導体装置の製造方法。
(4) In the contact hole structure of a semiconductor device using a phosphorous glass film (BPSG film) containing boron as a smooth coat film, the underlying oxide film of the semiconductor substrate is used as the lower insulating film, and the oxide film is used as a lower layer insulating film directly on the underlying oxide film or as a layer as required. A BPSG film is formed through the lower insulating film of No. 2, and this BPS
A step of selectively opening a part of the surface of the G film or the second lower layer insulating film to a slightly larger size;
a step of reflowing the film, a step of forming an upper insulating film thereon, each of the upper insulating films, the BPSG film or the second lower insulating film, and the portion of the lower insulating film corresponding to the opening, A step of forming a contact hole by selectively opening the contact hole according to the desired dimensions, and preventing the BPSG film from directly touching the semiconductor substrate, the wiring connection portion through the contact hole, and the wiring layer. A method for manufacturing a semiconductor device, characterized in that:
(5)第2の下層絶縁膜が、リンガラス膜(PSG膜)
、または窒化膜、プラズマ窒化膜、酸化膜などの絶縁膜
である特許請求の範囲第4項に記載の半導体装置の製造
方法。
(5) The second lower layer insulating film is a phosphorus glass film (PSG film)
, or an insulating film such as a nitride film, a plasma nitride film, or an oxide film.
(6)上層絶縁膜が、スピンコート法によるシリコン酸
化膜、または化学気相成長法による窒化膜、プラズマ窒
化膜、酸化膜などの絶縁膜である特許請求の範囲第4項
または第5項に記載の半導体装置の製造方法。
(6) Claim 4 or 5, wherein the upper insulating film is an insulating film such as a silicon oxide film formed by a spin coating method, a nitride film formed by a chemical vapor deposition method, a plasma nitride film, or an oxide film. A method of manufacturing the semiconductor device described above.
JP61119501A 1986-05-22 1986-05-22 Method for manufacturing semiconductor device Expired - Lifetime JP2512900B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61119501A JP2512900B2 (en) 1986-05-22 1986-05-22 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61119501A JP2512900B2 (en) 1986-05-22 1986-05-22 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS62274641A true JPS62274641A (en) 1987-11-28
JP2512900B2 JP2512900B2 (en) 1996-07-03

Family

ID=14762825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61119501A Expired - Lifetime JP2512900B2 (en) 1986-05-22 1986-05-22 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2512900B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02203551A (en) * 1989-02-02 1990-08-13 Sony Corp Forming method for multilayer wiring
JPH0461327A (en) * 1990-06-29 1992-02-27 Sharp Corp Manufacturing of semiconductor device
US5286677A (en) * 1993-05-07 1994-02-15 Industrial Technology Research Institute Method for etching improved contact openings to peripheral circuit regions of a dram integrated circuit
US6319848B1 (en) * 1993-10-12 2001-11-20 Texas Instruments Incorporated Inhomogenous composite doped film for low temperature reflow

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638842A (en) * 1979-09-07 1981-04-14 Nec Corp Manufacture of semiconductor device
JPS56131948A (en) * 1980-03-19 1981-10-15 Toshiba Corp Manufacture of semiconductor element
JPS5832434A (en) * 1981-08-20 1983-02-25 Toshiba Corp Manufacture of semiconductor device
JPS5873135A (en) * 1981-10-28 1983-05-02 Nec Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638842A (en) * 1979-09-07 1981-04-14 Nec Corp Manufacture of semiconductor device
JPS56131948A (en) * 1980-03-19 1981-10-15 Toshiba Corp Manufacture of semiconductor element
JPS5832434A (en) * 1981-08-20 1983-02-25 Toshiba Corp Manufacture of semiconductor device
JPS5873135A (en) * 1981-10-28 1983-05-02 Nec Corp Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02203551A (en) * 1989-02-02 1990-08-13 Sony Corp Forming method for multilayer wiring
JPH0461327A (en) * 1990-06-29 1992-02-27 Sharp Corp Manufacturing of semiconductor device
US5286677A (en) * 1993-05-07 1994-02-15 Industrial Technology Research Institute Method for etching improved contact openings to peripheral circuit regions of a dram integrated circuit
US6319848B1 (en) * 1993-10-12 2001-11-20 Texas Instruments Incorporated Inhomogenous composite doped film for low temperature reflow

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