JPS5816536A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the electric contact with a P-Si layer and semiconductor region by way of Al wiring layer, by a method wherein such protective film is grown up by CVD method as SiO2 film containing boron and then SiO2 film containing boron and phosphor. CONSTITUTION:After SiO2 layer (10) is formed on the surface of Si substrate (9), and then the growth of P-Si layer is made up, patterning is performed to form P-Si layer (11) for gates. After SiO2 film is formed around the layer (11), BSG (SiO2 containing B) film is grown up by CVD method, and patterning is performed to open the contact hole (14, 14') into BSG film (13) and SiO2 film (10). SiO2 film (12) is mounted thereupon in order to prevent the diffusion of B from BSG film (13) into P-Si layer (11) in the following process. Then, after BSG (SiO2 containing B and P) film (13) is grown up, contacts (16, 16') are opened into said film (15). After impurities are diffused on the substrate (9) to form the drain (18) and source (18'), Al is vaporized to form Al wiring layers (19, 19').

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular, BPS is applied to the surface of an element having a wiring layer such as polysilicon by a CVD method.
The present invention relates to a method of manufacturing an MO8 type semiconductor device in which a protective film such as a G film is formed.

Generally, in the manufacture of semiconductor devices such as integrated circuits, the CVD method (CVD method), which allows for a certain degree of leeway in the manufacturing conditions, is used instead of the thermal oxidation method.
Mical Vapor Deposition
Formation of various oxide films by a vapor phase growth method using chemical reactions has begun to be frequently used. By the way, when forming an oxide film by the CVD method, protrusions called hillocks may grow in the oxide film.

In particular, polysilicon (hereinafter P
In MO8 type semiconductor devices having a layer (referred to as -8i), BPSG for melting is used to make the element surface smooth.
It is necessary to grow the film (SiOzm containing boron and phosphorus) relatively thickly, and hillocks are likely to occur. As a result, the applied resist became thinner at the hillocks9, and mask defects occurred due to damage to the mask, resulting in unnecessary openings.Moreover, etching solution easily penetrates the interface between the hillocks and the BPSG film, so the openings extends deep into the lower layer of the 5PSG film.

For example, Figure 1 shows an MO8 type transistor.
p-s to be the gate; 5102 with tJm on 5.1
Film 2.5PSG film 3 is formed by CVD method,
Defect holes 4 caused by hillocks generated during the growth of 5P8Gl1%3 are opened by etching. Therefore, the diffusion layer 6 can be
and P-8i layer 1 are connected, and the device function is impaired. Note that 6' is a diffusion layer that becomes a source (or drain);
Reference numeral 7' is an Al interconnection layer that contacts the diffusion layer 6', and 8 is a 5I02 film that insulates the P2S1 layer 1 from the substrate 5.

In this way, in MO8 type semiconductor devices, a BPSG film is formed by the CVD method in order to eliminate the surface step structure caused by the P-8i layer. Short circuits occurred and manufacturing yields decreased.

The present invention was made in view of such conventional difficulties, and its feature is that S
In, a B8'G film is formed instead of the BSG film, and by taking advantage of the slow etching rate of the BSG film, even if there are hillocks in the BPSG film, unnecessary defect holes can reach the underlying P-8i layer. This is to prevent electrical contact between the P-8i layer and the semiconductor region due to the Al wiring layer.

The present invention will be described in detail below with reference to the drawings.

In the present invention, a BSG film (5i containing poron
n2 film) and then a BPSG film. This is BPSG for smoothing the element surface structure.
This is because even if hillocks occur during film growth, the etching rate of the BSG film is slow, so that it is possible to reduce penetration of the etching solution from the hillock portions when forming holes in the BPSG film for contact with the semiconductor region. Typically, prior to drilling contact holes in the BP8G membrane, approximately 10
Melting is performed by heat treatment at 00℃ for about 10 minutes.
Regarding the etching rate after this heat treatment, the volume ratio HF:NH,F:H20=6:40:54
BPSG film, 5in.
BSGj
At a good etching rate (Poron concentration of about 5 x 10''/c++!), the etching rate is about 1 oooX/min.

First, a SiO2 layer 10 is formed on the surface of a Si substrate 90, and then a P-8i layer is grown thereon, followed by patterning to form a P-8i layer 11 for a gate (FIG. 2).

Next, a SiO2 film 12 of approximately several tens of OA is applied to the P-8i layer 11.
After forming around the B8G film 13 and the Sin
,, a first contact hole 14, 14' is drilled in the membrane 10 (FIG. 3). This 5102 film 12 is provided to prevent poron from diffusing from the BSGS electrical film into the P-8i layer 11 during heat treatment in subsequent steps.

Next, the BPSG film 15 is grown by the CVD method, and then heat treated at 1000°C in dry N2 for about 10 degrees to melt the BPSG film and smooth the surface. A second contact 16.16' is drilled (Fig. 4). At this time B
Hillocks may occur as the PSG film 15 grows, and unnecessary defective holes 17 may be formed from the hillocks by the etching solution used to open the contact holes 16 and 16'. Since the etching speed is slow, defect holes 17 can be easily prevented from reaching the P-8i layer 11. Subsequently, impurities are diffused into the substrate 9 to form the drain 18,
After forming the source 18', Al is deposited to form the drain 1.
8. By forming Al wiring layers 19 and 19' in contact with the source 18', an MO8 type transistor is formed (Fig. 5), and the drain 18 and P-
No electrical contact occurs with the 8i layer 11.

In the above explanation, an MO8 type semiconductor device in which a P-8i wiring layer is formed on a Si substrate has been described, but the present invention is not limited to this. It can also be applied when using a metal such as molybdenum as a material, and in this case, a 5 inch
2 membranes 12 can be omitted.

As explained above, according to the present invention, a BSG film and a BP film are sequentially formed on the surface of an element including a wiring layer such as P-8i by the CVD method.
Since the SG film is formed, even if hillocks occur during the growth of the BPSG film, unnecessary defect holes can be prevented from being drilled deeply.
It is possible to prevent electrical connection from occurring between wiring layers such as '>, etc., and improve the manufacturing yield of the device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional MO8 type transistor, and FIGS. 2 to 5 are y-plane views for explaining the manufacture of the MO8 type transistor by the method of the present invention. 9...Si substrate 10...SiO2 film 11...P-8i wiring layer 13...BSG gland 15...BPSG, film (7 '317) Agent Patent Attorney Rule Yu1e Lieutenant?
f5 (1 other person) Figure l Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which a wiring layer such as polysilicon is formed on a Si substrate via an 8i02 film, and then a protective film is formed on the wiring layer, the protective film is formed by a CVD method using an SiO film containing boron. , SN containing boron and phosphorus
A method for manufacturing a semiconductor device, characterized in that an O2 film is sequentially grown.