JPH0578193B2 - - Google Patents

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Publication number
JPH0578193B2
JPH0578193B2 JP57052770A JP5277082A JPH0578193B2 JP H0578193 B2 JPH0578193 B2 JP H0578193B2 JP 57052770 A JP57052770 A JP 57052770A JP 5277082 A JP5277082 A JP 5277082A JP H0578193 B2 JPH0578193 B2 JP H0578193B2
Authority
JP
Japan
Prior art keywords
film
substrate
sio
silicon
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57052770A
Other languages
Japanese (ja)
Other versions
JPS58169976A (en
Inventor
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5277082A priority Critical patent/JPS58169976A/en
Publication of JPS58169976A publication Critical patent/JPS58169976A/en
Publication of JPH0578193B2 publication Critical patent/JPH0578193B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置の製造方法の改良に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in a method for manufacturing a semiconductor device.

(b) 技術の背景 MOSトランジシタを含むMOS型IC、MOS型
LSI等の半導体装置は、構造が比較的単純であり
製造工程も比較的短いので大容量メモリや大規模
ロジツク回路として用いられている。
(b) Technical background MOS type ICs including MOS transistors, MOS type
Semiconductor devices such as LSI have a relatively simple structure and a relatively short manufacturing process, so they are used as large-capacity memories and large-scale logic circuits.

(c) 従来技術と問題点 第1図〜第3図及び第5図により従来の半導体
装置の製造方法を工程順に説明する。
(c) Prior Art and Problems A conventional method for manufacturing a semiconductor device will be explained step by step with reference to FIGS. 1 to 3 and FIG. 5.

まずP型シリコン基板(以下、Si基板と略称す
る)1に所定パターンの素子間分離用二酸化シリ
コン膜(以下、素子間分離用SiO2膜と略称する)
2を形成する。
First, a predetermined pattern of silicon dioxide film for element isolation (hereinafter referred to as SiO 2 film for element isolation) is deposited on a P-type silicon substrate (hereinafter referred to as Si substrate) 1.
form 2.

この方法としては第5図に示すように、Si基板
11に薄い二酸化シリコン膜(以下、SiO2膜と
略称する)12を熱酸化法で、窒化シリコン膜
(以下、Si3N4膜と略称する)13をCVD法によ
り順次積層して形成後、ホトリソグラフイ技術を
用いて素子間分離用SiO2膜14の形成予定領域
の薄いSiO2膜12とSi3N4膜13とをエツチング
により除去し、この薄いSiO2膜12とSi3N4膜1
3との積層された二層構造をマスクとしてシリコ
ン基板11の熱酸化により、素子間分離用SiO2
膜14を形成する。
As shown in FIG. 5, this method involves depositing a thin silicon dioxide film (hereinafter abbreviated as SiO 2 film) 12 on a Si substrate 11 by thermal oxidation, and then depositing a silicon nitride film (hereinafter abbreviated as Si 3 N 4 film) on a Si substrate 11. ) 13 are sequentially stacked by the CVD method, and then the thin SiO 2 film 12 and the Si 3 N 4 film 13 in the area where the SiO 2 film 14 for isolation between elements is to be formed are etched using photolithography technology. Remove this thin SiO 2 film 12 and Si 3 N 4 film 1
By thermally oxidizing the silicon substrate 11 using the laminated two-layer structure with 3 as a mask, SiO 2 for element isolation is removed.
A film 14 is formed.

その後二層構造のSiO2膜12及びSi3N4膜13
をエツチングして除去してから、第1図のように
基板上にゲート用のSiO2膜3を基板の熱酸化に
より形成する。更にSiO2膜3上にポリシリコン
膜を形成後、ホトリソグラフイ法及びプラズマエ
ツチング法を用いて所定のパターンのゲート電極
を形成する。第1図の4はこのようにして形成さ
れたゲート電極である。
After that, a two-layer structure SiO 2 film 12 and Si 3 N 4 film 13
After removing it by etching, a SiO 2 film 3 for a gate is formed on the substrate by thermal oxidation of the substrate as shown in FIG. Furthermore, after forming a polysilicon film on the SiO 2 film 3, a gate electrode in a predetermined pattern is formed using photolithography and plasma etching. 4 in FIG. 1 is the gate electrode formed in this manner.

その後第2図に示すようにゲート電極4の表面
を酸化した後、ゲート電極をマスクとしてAS原
子等を矢印のようにイオン注入してソース領域5
及びドレイン領域6を形成する。
Thereafter, as shown in FIG. 2, after oxidizing the surface of the gate electrode 4, ions such as AS atoms are implanted in the direction shown by the arrow using the gate electrode as a mask to form the source region 5.
and a drain region 6 is formed.

更に第3図に示すように基板上にりん硅酸ガラ
ス(PSG)膜7を形成後、ホトリソグラフイ法
及びプラズマエツチング法を用いて所定パターン
に窓開きする。
Further, as shown in FIG. 3, a phosphosilicate glass (PSG) film 7 is formed on the substrate, and then windows are opened in a predetermined pattern using photolithography and plasma etching.

図で8及び9はこの様にして形成したソース領
域5とドレイン領域6との接続用孔である。その
後ソース領域及びドレイ領域と接続を取るための
アルミニウム(Al)による配線膜10を蒸着に
より形成して半導体装置を形成していた。
In the figure, 8 and 9 are connection holes between the source region 5 and the drain region 6 formed in this manner. Thereafter, a wiring film 10 made of aluminum (Al) for connecting to the source region and the drain region is formed by vapor deposition to form a semiconductor device.

しかしかかる方法では、このような素子間分離
用SiO2膜2を、薄いSiO2とSi3N4膜との二層構造
をマスクとしてSi基板の上に形成する場合、第4
図に示すようにそのSiO2膜2が基板下に形成さ
れる厚さとほぼ同程度の寸法だけSiO2膜2の端
部Aより基板の横方向へ広がる傾向がある。この
現象は一般にバーズビークと称され、このバーズ
ビークの形成されるとSiO2膜2で画定された素
子形成領域の寸法が狭くなり、従つてこの領域に
形成される素子の数も限定され、形成される半導
体装置の集積度が低下する欠点がある。
However, in this method, when the SiO 2 film 2 for element isolation is formed on the Si substrate using a two-layer structure of thin SiO 2 and Si 3 N 4 film as a mask, the fourth
As shown in the figure, the SiO 2 film 2 tends to spread in the lateral direction of the substrate from the end A of the SiO 2 film 2 by a dimension approximately equal to the thickness formed under the substrate. This phenomenon is generally referred to as a bird's beak, and when this bird's beak is formed, the dimensions of the element formation area defined by the SiO 2 film 2 become narrower, and the number of elements formed in this area is also limited. This has the disadvantage that the degree of integration of semiconductor devices decreases.

そこでこのような欠点を防ぐためSi基板に
SiO2膜を介さず直接Si3N4膜を形成して、この
Si3N4膜をマスクとして基板を熱酸化して素子間
分離用SiO2膜を形成する方法がとられている。
このように形成されたSi3N4膜は基板Siと窒素原
子との反応でSi基板と窒素原子とは化学結合で結
合された結果であるので、密着力は強固であり、
従つて横方向に素子間分離用SiO2膜が広がるこ
とは少なくなる。
Therefore, in order to prevent such defects, Si substrate
By directly forming a Si 3 N 4 film without using a SiO 2 film, this
A method has been adopted in which a substrate is thermally oxidized using a Si 3 N 4 film as a mask to form an SiO 2 film for isolation between elements.
The Si 3 N 4 film formed in this way is the result of a reaction between the Si substrate and nitrogen atoms, and the Si substrate and nitrogen atoms are bonded by chemical bonds, so the adhesion is strong.
Therefore, the SiO 2 film for element isolation is less likely to spread in the lateral direction.

しかしこのようにして結合したSi3N4膜は除去
の際、例えば熱りん酸(H3PO4)により除去す
るとSi基板表面が荒れたり、またH3PO4中の不
純物が基板上に残留する欠点がある。また四弗化
炭素を反応ガスとして用い、リアクテイブイオン
スパツタエツチによりエツチングしてもエツチン
グされた基板に凹凸が生じたりする欠点を生じ、
これによつてSi基板上のSi3N4膜には上記の如き
利点と欠点がある。
However, when removing the Si 3 N 4 film bonded in this way, for example with hot phosphoric acid (H 3 PO 4 ), the Si substrate surface becomes rough, and impurities in H 3 PO 4 remain on the substrate. There are drawbacks to doing so. Furthermore, even if carbon tetrafluoride is used as a reactive gas and etching is performed by reactive ion sputter etching, there is a drawback that unevenness occurs on the etched substrate.
As a result, the Si 3 N 4 film on the Si substrate has the advantages and disadvantages described above.

しかしてMOSFETの特にゲート用絶縁膜につ
いて検討すると、第1図に示すように従来の方法
ではゲート用SiO2膜3はSi基板の熱酸化法で形
成され、Si基板と酸素の直接反応によつて得られ
ているので、その界面における欠陥は少なく電気
的に活性なトラツプやイオン汚染の少ない安定の
薄膜である。しかしその後の工程において、ゲー
ト電極を所定のパターンに形成したり、プラズマ
エツチングやリアクテイブイオンエツチング等の
プロセスを経ると、SiO2膜は劣化したり絶縁性
が低下したりする問題点が生じる。
However, when considering the insulating film for the gate of MOSFETs in particular, as shown in Figure 1, in the conventional method, the SiO 2 film 3 for the gate is formed by thermal oxidation of the Si substrate, and it is formed by a direct reaction between the Si substrate and oxygen. Since the film is obtained as a composite material, it is a stable thin film with few defects at the interface and no electrically active traps or ion contamination. However, in subsequent steps, when the gate electrode is formed into a predetermined pattern or through processes such as plasma etching and reactive ion etching, problems arise in that the SiO 2 film deteriorates and its insulation properties decrease.

一方大規模集積回路の性能及び集積度を向上さ
せるためにパターン形状の微細化、微少化の努力
が払われ、特にMOSLSIでは構造が比較的単純
であり、製造工程も比較的短いため大容量メモリ
や大規模ロジツク回路として発展し、従つてその
中で用いられる基本素子であるMOSFETではチ
ヤンネル長及び幅を短くし、ソース及びドレイン
の接合深さを浅くし、薄いゲート絶縁膜を用いる
必要がある。そこでゲート用SiO2膜の代わりに
化学的に安定で物理的にも構造緻密なゲート用
Si3N4を用いれば、特性の向上が期待できる。そ
して良質のSi3N4の薄膜を生成するためには、例
えばSi基板を純化したNH3中で加熱すればよい。
またSi基板を反応管中に導入し、反応管に純化し
たアンモニア(NH3)ガスを導入し、反応管の
外部の高周波誘導コイルに高周波電圧を印加して
NH3ガスをプラズマ化して形成してもよい。
On the other hand, in order to improve the performance and degree of integration of large-scale integrated circuits, efforts are being made to miniaturize and miniaturize pattern shapes.In particular, MOSLSI has a relatively simple structure and a relatively short manufacturing process, so large-capacity memory MOSFETs, which are the basic elements used in these circuits, need to have shorter channel lengths and widths, shallow source and drain junction depths, and thin gate insulating films. . Therefore, instead of SiO 2 film for gates, we used chemically stable and physically dense structure for gates.
If Si 3 N 4 is used, improved characteristics can be expected. In order to produce a high-quality Si 3 N 4 thin film, for example, a Si substrate may be heated in purified NH 3 .
In addition, a Si substrate was introduced into the reaction tube, purified ammonia (NH 3 ) gas was introduced into the reaction tube, and a high-frequency voltage was applied to a high-frequency induction coil outside the reaction tube.
It may also be formed by turning NH 3 gas into plasma.

かかる方法は反応の低温化及び混入不純物の低
減化に効果がある。しかし、かかる直接窒化反応
で生成したSi3N4膜は、生成できる膜厚が100Å
程度の厚さ以上に分厚く形成するのは困難で、電
界の集中する特にゲート電極の周囲の領域の膜厚
を大きくとることが困難で、印加する電圧の大き
さが制限される等不都合を生じていた。
Such a method is effective in lowering the reaction temperature and reducing mixed impurities. However, the Si 3 N 4 film produced by such a direct nitriding reaction has a thickness of only 100 Å.
It is difficult to form a film thicker than a certain thickness, and it is difficult to increase the film thickness especially in the area around the gate electrode where the electric field is concentrated, resulting in inconveniences such as limiting the magnitude of the applied voltage. was.

(d) 発明の目的 本発明はゲート絶縁膜としてプラズマエツチン
グとか、リアクテイブイオンエツチング等のプロ
セスを経てもSiO2の如く劣化せず、絶縁性も十
分に保持され化学的に安定で構造緻密な薄い
Si3N4膜を使用し、しかもゲート電極の周辺での
膜厚を大として大きな電圧にも耐えうるようにな
し、かつ電極窓の窓明けのエツチングでもSi基板
表面を平滑に保ちうるようにすることを目的とす
る。
(d) Purpose of the Invention The present invention provides a gate insulating film that does not deteriorate like SiO 2 even after undergoing processes such as plasma etching or reactive ion etching, maintains sufficient insulation properties, is chemically stable, and has a dense structure. thin
A Si 3 N 4 film is used, and the film thickness around the gate electrode is increased to withstand large voltages, and the Si substrate surface can be kept smooth even during etching to open the electrode window. The purpose is to

(e) 発明の構成 かかる目的は本発明によつて、シリコン基板1
1に所定パターンの素子間分離用二酸化シリコン
膜14を形成後、素子間分離用二酸化シリコン膜
14で画定されたシリコン基板11上に直接窒化
反応により窒化シリコン膜15を形成する工程
と、シリコン基板11上の窒化シリコン膜15の
表面にポリシリコン膜を形成後、ポリシリコン膜
をパターニングして窒化シリコン膜15の表面に
ゲート電極16を形成し、かかるシリコン基板1
1を酸素プラズマ中に曝してゲート電極以外の窒
化シリコン膜15を酸化する工程と、ゲート電極
16をマスクとして酸化膜に変換された膜を通し
てシリコン基板11に不純物を導入してソース1
9及びドレイン20領域を形成する工程とを含む
ことを特徴とする半導体装置の製造方法によつて
達成される。
(e) Structure of the invention This object is achieved by the present invention, in which silicon substrate 1
Step 1: Forming a silicon dioxide film 14 for element isolation in a predetermined pattern, and then forming a silicon nitride film 15 by direct nitriding reaction on the silicon substrate 11 defined by the silicon dioxide film 14 for element isolation; After forming a polysilicon film on the surface of the silicon nitride film 15 on the silicon substrate 11, the polysilicon film is patterned to form a gate electrode 16 on the surface of the silicon nitride film 15.
The source 1 is exposed to oxygen plasma to oxidize the silicon nitride film 15 other than the gate electrode, and the gate electrode 16 is used as a mask to introduce impurities into the silicon substrate 11 through the film converted into an oxide film.
9 and a step of forming a drain 20 region.

また本発明によれば、上記においてゲート電極
16を形成した後、このゲート電極をマスクとし
窒化シリコン膜を通してシリコン基板に不純物を
導入してソース19及びドレイン20領域を形成
し、続いてかかるシリコン基板を酸素プラズマ中
に曝してソース、ドレイン領域上の窒化シリコン
膜を酸化するようにしてもよい。
Further, according to the present invention, after forming the gate electrode 16 in the above, impurities are introduced into the silicon substrate through the silicon nitride film using the gate electrode as a mask to form the source 19 and drain 20 regions, and then the silicon substrate The silicon nitride film on the source and drain regions may be oxidized by exposing it to oxygen plasma.

(f) 発明の実施例 本発明はSi3N4が酸素プラズマ雰囲気中で、Si
基板と同程度の速度で酸化されるという知見にも
とずいている。
(f) Embodiments of the Invention The present invention provides a method for forming Si 3 N 4 in an oxygen plasma atmosphere.
This is based on the knowledge that it is oxidized at a rate similar to that of the substrate.

以下図面を用いて本発明の一実施例につき詳細
に説明する。
An embodiment of the present invention will be described in detail below with reference to the drawings.

第5図までは従来通りであり、第6図より第1
0図までが本発明の半導体装置の製造方法の工程
の手順を示す断面図で、第11図は本発明の半導
体装置の製造方法に用いる装置の概略図である。
Up to Figure 5, it is the same as before, and from Figure 6,
0 to 1 are cross-sectional views showing the steps of the method of manufacturing a semiconductor device of the present invention, and FIG. 11 is a schematic diagram of an apparatus used in the method of manufacturing a semiconductor device of the present invention.

まず従来通り第5図に示すようにP型のSi基板
11上に所定パターンのSiO2膜12及びSi3N4
13の二層構造のパターニングされた保護膜を形
成する。
First, as shown in FIG. 5, a patterned protective film having a two-layer structure of a SiO 2 film 12 and a Si 3 N 4 film 13 having a predetermined pattern is formed on a P-type Si substrate 11 as in the conventional method.

次に二層構造の保護膜をマスクとして基板を熱
酸化して素子間分離用のSiO2膜14を厚さ1μm
に形成する。その後二層構造のSiO2膜12及び
Si3N4膜13をエツチングして除去してから、基
板を第11図に示す石英の反応管101中の炭化
珪素(SiC)をコーテイングしたカーボン台10
2上に設置し、反応管内を約100Torrの真空
度に排気してから、基板の周囲の高周波誘導加熱
コイル103に200KHzの周波数で出力7KWの高
周波電力を印加して基板を約1100℃の温度に加熱
し、ガス導入管104よりアンモニア(NH3
ガスを導入して管内にNH3ガスの分解した窒素
ガスプラズマを形成する。そしてこの窒素ガスプ
ラズマとSi基板との反応で素子間分離領域の
SiO2膜14で画定された領域内に、第6図に示
すように膜厚100ÅのSi3N4膜15を形成する。
このとき素子間分離用SiO2膜14の一部もSi3N4
膜にて覆われるようになる。
Next, using the two-layer protective film as a mask, the substrate is thermally oxidized to form a SiO 2 film 14 with a thickness of 1 μm for isolation between elements.
to form. After that, the two-layer structure SiO 2 film 12 and
After removing the Si 3 N 4 film 13 by etching, the substrate is placed on a carbon stand 10 coated with silicon carbide (SiC) in a quartz reaction tube 101 as shown in FIG.
After evacuating the inside of the reaction tube to a vacuum level of approximately 100 Torr, high-frequency power with a frequency of 200 KHz and an output of 7 KW is applied to the high-frequency induction heating coil 103 around the substrate to heat the substrate to approximately 1100°C. ammonia (NH 3 ) from the gas introduction pipe 104.
Gas is introduced to form nitrogen gas plasma, which is the decomposition of NH 3 gas, inside the tube. The reaction between this nitrogen gas plasma and the Si substrate creates isolation regions between elements.
In the region defined by the SiO 2 film 14, a Si 3 N 4 film 15 with a thickness of 100 Å is formed as shown in FIG.
At this time, a part of the SiO 2 film 14 for element isolation is also Si 3 N 4
It becomes covered with a membrane.

その後基板上にモノシラン(SiN4)ガスの熱
分解によつてポリSi膜を約4000Åの厚さに形成し
て、これをホトリソグラフイ法及びプラズマエツ
チング法により所定のパターンのゲート電極とす
る。第6図の16はこのようにして形成したゲー
ト電極である。
Thereafter, a poly-Si film with a thickness of about 4000 Å is formed on the substrate by thermal decomposition of monosilane (SiN 4 ) gas, and this is formed into a gate electrode in a predetermined pattern by photolithography and plasma etching. Reference numeral 16 in FIG. 6 is the gate electrode formed in this manner.

この状態において、基板を再び前述した第11
図の反応管101の中の炭化珪素よりなる支持台
102上に設置してから、反応管内を100Torrの
真空度になるまで排気したのち、ガス導入管10
4より酸素ガスを導入し、反応管内を高周波誘導
加熱コイル103を用いて該コイルに周波数
200KHz出力7KWの高周波電力を印加し加熱し、
酸素ガスプラズマを発生させ、かかる酸素プラズ
マ中で約800℃に加熱する。
In this state, the substrate is again
After installing the reaction tube 101 in the figure on a support base 102 made of silicon carbide and evacuating the inside of the reaction tube to a degree of vacuum of 100 Torr, the gas introduction tube 10
4, oxygen gas is introduced into the reaction tube using a high frequency induction heating coil 103, and a frequency is applied to the coil.
Heat by applying high frequency power of 200KHz output 7KW,
An oxygen gas plasma is generated and heated to about 800° C. in the oxygen plasma.

かかる工程において、第7図に示すように素子
間分離用SiO2膜14で画定された領域のSi3N4
15が酸化され、ソース、ドレイン領域上の
Si3N4膜が全部SiO2膜17に変換されたら酸化を
停止する。またゲート電極16の表面にもわずか
にSiO2膜18が形成される。
In this step, as shown in FIG. 7, the Si 3 N 4 film 15 in the area defined by the element isolation SiO 2 film 14 is oxidized, and the Si 3 N 4 film 15 on the source and drain regions is oxidized.
When the Si 3 N 4 film is completely converted to the SiO 2 film 17, the oxidation is stopped. Further, a slight SiO 2 film 18 is also formed on the surface of the gate electrode 16.

ここで上記Si3N4膜のSiO2膜への変換速度は約
50Å/分である。ここで2分間、酸素プラズマ処
理すると、Si3N4膜はSi基板と同程度の速度で酸
化されるので、SiO2膜に変換されると膜厚が略
2倍以上になる。
Here, the conversion rate of the above Si 3 N 4 film to SiO 2 film is approximately
50 Å/min. When oxygen plasma treatment is performed for 2 minutes, the Si 3 N 4 film is oxidized at a rate comparable to that of the Si substrate, so that when converted to an SiO 2 film, the film thickness becomes approximately twice or more.

その後ソース形成予定領域及びドレイン形成予
定領域にゲート電極16をマスクとして砒素
(AS)原子を矢印のようにイオン注入してソース
領域19及びドレイン領域20を形成する。
Thereafter, a source region 19 and a drain region 20 are formed by ion-implanting arsenic (AS) atoms into the region where the source is to be formed and the region where the drain is to be formed as shown by the arrows using the gate electrode 16 as a mask.

その後第8図に示すように表面保護用として
PSG膜21を形成した後、PSG膜21と下部の
Si3N4膜が酸化されたSiO2膜17をプラズマエツ
チング法により選択的にエツチングして、第9図
のようにソース領域との接続用孔22及びドレイ
ン領域との接続用孔23を窓開きする。
Afterwards, as shown in Figure 8, it was used for surface protection.
After forming the PSG film 21, the PSG film 21 and the bottom
The SiO 2 film 17, in which the Si 3 N 4 film has been oxidized, is selectively etched by plasma etching to form a connection hole 22 with the source region and a connection hole 23 with the drain region as shown in FIG. Open.

このようにすればSi基板上の素子形成領域上の
Si3N4膜は酸化されているので、容易にプラズマ
エツチング出来るのでエツチングに要する時間が
少なく、またエツチングされたSi基板の表面も平
滑になり、SiO2膜によつてPSG膜中の燐Pが工
程の途中でソース、ドレイン領域に拡散するのも
防止される。
In this way, the device formation area on the Si substrate can be
Since the Si 3 N 4 film is oxidized, it can be easily plasma etched, so the time required for etching is shortened, and the surface of the etched Si substrate becomes smooth, and the SiO 2 film removes the phosphorus in the PSG film. It is also prevented from diffusing into the source and drain regions during the process.

また素子間分離用SiO2膜で画定された素子形
成領域はゲート電極の周囲を含め、その端部にお
いてSi3N4膜が厚さの大なるSiO2膜となつている
ので、その部分に電界が集中しても容易に素子が
劣化しない。
In addition, in the device formation region defined by the SiO 2 film for device isolation, the Si 3 N 4 film becomes a thick SiO 2 film at the edges, including around the gate electrode, so that The device does not deteriorate easily even if the electric field is concentrated.

その後第10図に示すように、アルミニウム
(Al)よりなる金属膜を蒸着によつて形成した
後、所定のパターンにエツチングしてAlの配線
膜として素子間を結合する。第10図の24はこ
のようにして形成したAlの配線である。
Thereafter, as shown in FIG. 10, a metal film made of aluminum (Al) is formed by vapor deposition and then etched into a predetermined pattern to form a wiring film of Al to connect the elements. Reference numeral 24 in FIG. 10 indicates the Al wiring formed in this manner.

また上記実施例では、Si3N4膜15を酸化した
後、ゲート電極をマスクとしてソース、ドレイン
領域を形成しているが、Si3N4膜を酸化する前
に、即ち第6図の状態でソース、ドレイン領域を
形成し、その後にSi3N4膜を酸化するようにして
もよい。
In the above embodiment, after the Si 3 N 4 film 15 is oxidized, the source and drain regions are formed using the gate electrode as a mask, but before the Si 3 N 4 film 15 is oxidized, the state shown in FIG. Alternatively, the source and drain regions may be formed using the same method, and then the Si 3 N 4 film may be oxidized.

(g) 発明の効果 以上述べた如く本発明の半導体装置の製造方法
では、素子間分離用二酸化シリコン膜で画定され
たシリコン基板上には化学的に安定で、構造緻密
なSi3N4膜が直接窒化反応により形成されている
ので、ゲート電極形成の際のエツチング工程でも
このSi3N4膜は劣化することがなく、またこれら
のSi3N4膜はゲート電極形成後酸化されてSiO2
なり、膜厚は倍となるのでゲート電極の周囲での
耐圧も大で、しかもソース、ドレイン電極形成の
際の窓明けでもSi基板表面は平滑に保たれる。
(g) Effects of the Invention As described above, in the method for manufacturing a semiconductor device of the present invention, a chemically stable Si 3 N 4 film with a dense structure is formed on a silicon substrate defined by a silicon dioxide film for element isolation. is formed by a direct nitridation reaction, so this Si 3 N 4 film does not deteriorate even during the etching process when forming the gate electrode, and these Si 3 N 4 films are oxidized after forming the gate electrode and become SiO. 2 , the film thickness is doubled, so the withstand voltage around the gate electrode is also high, and the Si substrate surface can be kept smooth even when the window is opened when forming the source and drain electrodes.

一方ゲート電極の下部のゲート絶縁膜は薄い構
造緻密なSi3N4膜となつているので、微細化の要
件を満足し、従つて半導体装置の特性が向上し、
高信頼度の半導体装置が得られることになる。
On the other hand, since the gate insulating film below the gate electrode is a thin Si 3 N 4 film with a dense structure, it satisfies the requirements for miniaturization and therefore improves the characteristics of the semiconductor device.
A highly reliable semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図より第3図まで及び第5図は従来の半導
体装置の製造方法の工程を示す断面図、第4図は
従来の半導体装置の不具合を示す図、第6図より
第10図までは本発明の半導体装置の製造方法の
工程を示す断面図、第11図は本発明の半導体装
置の製造方法に用いる装置の概略図である。 図において、1,11はSi基板、2,14は素
子間分離用SiO2膜、3はゲート酸化膜、4,1
6はポリシリコンゲート電極、5,19はソース
領域、6,20はドレイン領域、7,21は
PSG膜、8,9,22,23は接続用孔、12,
18はSiO2膜、13,15は窒化Si膜、17は
窒化Si膜を酸化したSiO2膜、10,24はAl配
線膜、101は反応管、102は基板設置台、1
03は高周波誘導コイル、104はガス導入管、
Aは端部を示す。
Figures 1 to 3 and 5 are cross-sectional views showing the steps of a conventional semiconductor device manufacturing method, Figure 4 is a diagram showing defects in the conventional semiconductor device, and Figures 6 to 10 are cross-sectional views showing the steps of a conventional semiconductor device manufacturing method. FIG. 11, which is a sectional view showing the steps of the method for manufacturing a semiconductor device of the present invention, is a schematic diagram of an apparatus used in the method for manufacturing a semiconductor device of the present invention. In the figure, 1 and 11 are Si substrates, 2 and 14 are SiO 2 films for isolation between elements, 3 is a gate oxide film, and 4 and 1
6 is a polysilicon gate electrode, 5 and 19 are source regions, 6 and 20 are drain regions, and 7 and 21 are
PSG membrane, 8, 9, 22, 23 are connection holes, 12,
18 is a SiO 2 film, 13 and 15 are Si nitride films, 17 is an SiO 2 film obtained by oxidizing the Si nitride film, 10 and 24 are Al wiring films, 101 is a reaction tube, 102 is a substrate installation stand, 1
03 is a high frequency induction coil, 104 is a gas introduction pipe,
A indicates the end.

Claims (1)

【特許請求の範囲】 1 シリコン基板11に所定パターンの素子間分
離用二酸化シリコン膜14を形成後、素子間分離
用二酸化シリコン膜14で画定されたシリコン基
板11上に直接窒化反応により窒化シリコン膜1
5を形成する工程と、シリコン基板11上の窒化
シリコン膜15の表面にポリシリコン膜を形成
後、ポリシリコン膜をパターニングして窒化シリ
コン膜15の表面にゲート電極16を形成し、か
かるシリコン基板11を酸素プラズマ中に曝して
ゲート電極以外の窒化シリコン膜15を酸化する
工程と、ゲート電極16をマスクとし酸化膜に変
換された膜を通してシリコン基板11に不純物を
導入してソース19及びドレイン20領域を形成
する工程とを含むことを特徴とする半導体装置の
製造方法。 2 シリコン基板11に所定パターンの素子間分
離用二酸化シリコン膜14を形成後、素子間分離
用二酸化シリコン膜14で画定されたシリコン基
板11上に直接窒化反応により窒化シリコン膜1
5を形成する工程と、シリコン基板11上の窒化
シリコン膜15の表面にポリシリコン膜を形成
後、ポリシリコン膜をパターニングして窒化シリ
コン膜15の表面にゲート電極16を形成し、ゲ
ート電極16をマスクとし窒化シリコン膜を通し
てシリコン基板11に不純物を導入してソース1
9及びドレイン20領域を形成した後、シリコン
基板11を酸素プラズマ中に曝してソース・ドレ
イン領域上の窒化シリコン膜15を酸化する工程
とを含むことを特徴とする半導体装置の製造方
法。
[Claims] 1. After forming a silicon dioxide film 14 for element isolation in a predetermined pattern on a silicon substrate 11, a silicon nitride film is formed by a direct nitriding reaction on the silicon substrate 11 defined by the silicon dioxide film 14 for element isolation. 1
5, and after forming a polysilicon film on the surface of the silicon nitride film 15 on the silicon substrate 11, patterning the polysilicon film to form a gate electrode 16 on the surface of the silicon nitride film 15, 11 in oxygen plasma to oxidize the silicon nitride film 15 other than the gate electrode, and using the gate electrode 16 as a mask, impurities are introduced into the silicon substrate 11 through the film converted into an oxide film to form the source 19 and drain 20. 1. A method of manufacturing a semiconductor device, comprising the step of forming a region. 2 After forming the silicon dioxide film 14 for device isolation in a predetermined pattern on the silicon substrate 11, a silicon nitride film 1 is formed by a direct nitriding reaction on the silicon substrate 11 defined by the silicon dioxide film 14 for device isolation.
After forming a polysilicon film on the surface of the silicon nitride film 15 on the silicon substrate 11, the polysilicon film is patterned to form a gate electrode 16 on the surface of the silicon nitride film 15. Using as a mask, impurities are introduced into the silicon substrate 11 through the silicon nitride film to form the source 1.
9 and drain 20 regions, the silicon substrate 11 is exposed to oxygen plasma to oxidize the silicon nitride film 15 on the source/drain regions.
JP5277082A 1982-03-30 1982-03-30 Manufacture of semiconductor device Granted JPS58169976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5277082A JPS58169976A (en) 1982-03-30 1982-03-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5277082A JPS58169976A (en) 1982-03-30 1982-03-30 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58169976A JPS58169976A (en) 1983-10-06
JPH0578193B2 true JPH0578193B2 (en) 1993-10-28

Family

ID=12924094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5277082A Granted JPS58169976A (en) 1982-03-30 1982-03-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58169976A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625641A (en) * 1985-04-09 1987-01-12 フエアチヤイルド セミコンダクタ コ−ポレ−シヨン Low temperature plasma nitriding and application of nitride film formed therein
CN102487050B (en) * 2010-12-03 2015-11-25 比亚迪股份有限公司 Power semiconductor and manufacture method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676536A (en) * 1979-11-27 1981-06-24 Chiyou Lsi Gijutsu Kenkyu Kumiai Anodization of silicon nitride film
JPS56135937A (en) * 1980-03-28 1981-10-23 Nec Corp Manufacture of semiconductor device
JPS56135936A (en) * 1980-03-28 1981-10-23 Nec Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676536A (en) * 1979-11-27 1981-06-24 Chiyou Lsi Gijutsu Kenkyu Kumiai Anodization of silicon nitride film
JPS56135937A (en) * 1980-03-28 1981-10-23 Nec Corp Manufacture of semiconductor device
JPS56135936A (en) * 1980-03-28 1981-10-23 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS58169976A (en) 1983-10-06

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