JPS5832434A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5832434A
JPS5832434A JP13052181A JP13052181A JPS5832434A JP S5832434 A JPS5832434 A JP S5832434A JP 13052181 A JP13052181 A JP 13052181A JP 13052181 A JP13052181 A JP 13052181A JP S5832434 A JPS5832434 A JP S5832434A
Authority
JP
Japan
Prior art keywords
film
insulating film
semiconductor device
silicon oxide
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13052181A
Other languages
Japanese (ja)
Other versions
JPS6320383B2 (en
Inventor
Shigeru Morita
茂 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13052181A priority Critical patent/JPS5832434A/en
Publication of JPS5832434A publication Critical patent/JPS5832434A/en
Publication of JPS6320383B2 publication Critical patent/JPS6320383B2/ja
Granted legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent metal wiring from being broken by minimizing surface unevenness through the use of an insulating film of the stacked layer type when covering the entire surface of a substrate after the formation of source and drain regions and providing these regions with openings. CONSTITUTION:Thick field oxide films 112 are formed on the peripheral parts of a P type Si substrate 110. A gate electrode 118 of a polycrystalline Si is formed via a thin gate oxide film 122 at the center surface of the substrate 110 surrounded by the films 112, and on the film 112 a wiring pattern 120 is formed. Then the electrode 118 and the pattern 120 are subjected to heat treatment in an atmosphere of POCl3 to provide them with conductivity, N<+> type source and drain regions 124,126 are formed on the substrate 110, and the entire surface is covered with a stacked layer of an SiO2 film 130 and an SiO2 film 132 with impurities added. Contact holes 134 are formed to the regions 124,126, and by the reactive ion etching the film 132 is left as a film 132b only on the film 130 in the vicinity of the hole 134. The entire surface is then covered with an SiO2 film 136, openings are provided to this film and Al wiring 138 is bonded to each region.

Description

【発明の詳細な説明】 本発明は半導体装置とその製造方法に関する。[Detailed description of the invention] The present invention relates to a semiconductor device and a method for manufacturing the same.

従来、半導体装置の製造に於いては、アルミ配線の断切
れを防ぐ目的で基板w爾を平滑化している。即ち、=ン
タクト開孔前に半導体基板全面に燐もしくは硼素を添加
した高温熱処理によシ溶融可能なシリコン酸化物からな
る絶縁膜を形成し、続いてコンタクFを開孔し、その後
高温熱処理によシ前記絶縁膜を溶融させている。
Conventionally, in the manufacture of semiconductor devices, substrates have been smoothed to prevent aluminum wiring from breaking. In other words, an insulating film made of meltable silicon oxide is formed on the entire surface of the semiconductor substrate by high-temperature heat treatment with addition of phosphorus or boron before opening the contact hole, then contact F is opened, and then high-temperature heat treatment is performed. Otherwise, the insulating film is melted.

凸 第1(a)図メ至1(・)図を参照して、例えば1チャ
ネルシリコンr−)MOg)ツンジスタの製造方法を説
明する。まず第1(a)図に示すようにP型シリコン基
板1−上に厚さ1μのシリコン酸化膜を形成し、写真蝕
刻法によ)ソース、ドレインとr−)形成予定領域0S
Iv:!ン酸化膜を除去してフィールド絶縁膜12を形
成する0次に露出し九シリコン基fI7L1−上に厚さ
100OXのシリコン酸化膜14を形成し、そめ上に厚
さ40001 O多結晶シリブン層1.#を気相成長法
によ多形成する。その後第1(b)図に示すように写真
蝕刻法によりダート電極18と配1m/す−720を形
成し、更にダート電極18をマスクとしてソース、ドレ
イン形成予定領域のシリコン酸化膜14を除去しr−)
絶縁膜21を形成する0次にオキシ塩化燐(Pock、
 )雰囲気中で1000℃、1#分の高温熱処理を実施
することによってr−)電極18と配線Δターン20に
燐を拡散させて低抵抗化させる。また同時に露出したシ
リコン基板10にも燐を拡散させてN+型のソース領域
24とドレイン領域2Cを形成する0次に第1 (e)
図に示すよう妃高温酸化によルf−)電極18と配線パ
ターン20及び露出したシリコン基板上に約1ooo1
の酸化膜2#を形にシリコン基板全面に燐もしくは燐と
硼素が添加された厚さ5000裏のシリコン酸化膜(ド
ープドシリコン酸化膜)32を形成する。その後写真蝕
刻法によシコンタクト34を開孔し、全面に厚さJSO
OXの7ンドーグドシリコン酸化換1#化燐雰囲気中で
1000℃、5分の高温熱処理を行い、ドープドシリコ
ン酸化膜81を濱融して、基板表面の凹凸を平滑化させ
る。更に再び写真蝕刻法によシコンタクト部34の厚さ
5ooX。
A method of manufacturing, for example, a 1-channel silicon MOg) Tunster will be described with reference to FIGS. First, as shown in FIG. 1(a), a silicon oxide film with a thickness of 1 μm is formed on a P-type silicon substrate 1-, and a region 0S in which sources and drains (a) and r-) are to be formed is formed by photolithography.
IV:! A silicon oxide film 14 with a thickness of 100OX is formed on the exposed nine silicon groups fI7L1- to form a field insulating film 12 by removing the silicon oxide film, and a polycrystalline silicon layer 1 with a thickness of 40001O is formed on the bottom. .. # is formed by a vapor phase growth method. Thereafter, as shown in FIG. 1(b), a dirt electrode 18 and a 1 m/s-720 layer are formed by photolithography, and the silicon oxide film 14 in the regions where the source and drain are to be formed is removed using the dirt electrode 18 as a mask. r-)
Zero-order phosphorus oxychloride (Pock,
) By performing high temperature heat treatment at 1000 DEG C. for 1 minute in an atmosphere, phosphorus is diffused into the r-) electrode 18 and the wiring Δ turn 20 to lower the resistance. At the same time, phosphorus is also diffused into the exposed silicon substrate 10 to form an N+ type source region 24 and drain region 2C.
As shown in the figure, by high temperature oxidation, the electrode 18, the wiring pattern 20 and the exposed silicon substrate are coated with approximately 1001
A silicon oxide film (doped silicon oxide film) 32 with a thickness of 5,000 mm and doped with phosphorus or phosphorus and boron is formed on the entire surface of the silicon substrate in the shape of the oxide film 2#. After that, a contact hole 34 was formed by photolithography, and a thickness of JSO was formed on the entire surface.
A high-temperature heat treatment is performed at 1000° C. for 5 minutes in an OX 7-doped silicon oxide conversion 1# phosphorus atmosphere to melt the doped silicon oxide film 81 and smooth the unevenness on the substrate surface. Furthermore, the thickness of the contact portion 34 is 50× by photolithography.

アンド−fPシリコン酸酸化膜−を除去する。AND-fP silicon acid oxide film- is removed.

次に第1(・)図に示すようにアル電を蒸着して厚さ1
μのアル電層をy#□成し、写真蝕刻法によシアル電酸
線j#を設ゆ、1チャネルシリフンr−) MOg )
 ?ンジスタを完成させる。
Next, as shown in Fig.
Form an alkaline layer of μ y#□, set a sialic acid wire j# by photolithography, and form a 1-channel silicone layer (r-)MOg).
? Complete the injista.

とζろで従来の方法では、平滑化用0ドーグドシリプン
酸化@aXを気相成長によ)形成する際に1異常成長に
よ)ドーf P V 9 :lン酸化膜J1!!面に突
起物40がある割合で発生しく第1(−)図参照)、こ
の突起物401ICよ)アル2配線31の断切れが発生
した)、写真蝕刻不良の原因となるととがある。を九一
方燐と硼素が添加されたシリコン酸化膜を平滑化用薄・
膜に使用した場合には、平滑化1禅に於けるオキシ塩化
燐雰囲気中での高温熱処理の際に、最上部に形成された
アンドープドシリコン酸化II x #にある割合で発
生している微小孔を通してオキシ塩化燐とドープドシリ
コン酸化膜J2が反応してドープドシリコン酸化IEJ
jの沸騰現象が生じ、ドープドシリコン酸化膜632表
面に突起物42が形成される場合がある(第1(−蔵参
照)。
In the conventional method, when the smoothing doped silicon oxide @aX is formed by vapor phase growth, the doped silicon oxide film J1! is formed by abnormal growth. ! It is said that the protrusions 40 are generated on the surface (see FIG. 1 (-)), and that the protrusions 401IC) cause the disconnection of the Al2 wiring 31), causing defective photo-etching. A thin and smooth silicon oxide film doped with phosphorus and boron.
When used in a film, during the high-temperature heat treatment in a phosphorous oxychloride atmosphere during smoothing, a certain proportion of microscopic particles are generated in the undoped silicon oxide II x # formed on the top. Through the holes, phosphorus oxychloride and doped silicon oxide film J2 react to form doped silicon oxide IEJ.
A boiling phenomenon may occur, and protrusions 42 may be formed on the surface of the doped silicon oxide film 632 (see No. 1 (-)).

この突起物42もアル建配*xtto断切れを発生させ
たシ、写真蝕刻不良の原因と慶る。上記不都合を防止す
るためには、ドープドシリコン酸化換12上にアンド−
lドシリーン酸化膜J6を厚く形成すればよいが、仁の
、場合には高温熱処理によるドープドシリコン酸化I[
12の平滑化が困難となるので自づからアンドーグドシ
リコン酸化膜sea膜厚は制限され、充分に微小孔の発
生を防止できない。
This protrusion 42 also caused the discontinuity in the alignment and was the cause of defective photo engraving. In order to prevent the above-mentioned disadvantages, an and-
It is sufficient to form the doped silicon oxide film J6 thickly.
Since it becomes difficult to smooth the surface of the undoped silicon oxide film 12, the thickness of the undoped silicon oxide film sea is naturally limited, and the generation of micropores cannot be sufficiently prevented.

本発明は上記点に鑑み表されたもので、平坦な領域上に
存在する高温熱処理によシ溶融可能な絶縁膜の厚みを、
凹凸部の側面に存在する前記絶縁膜の厚みよシ薄くする
かもしくは完全に除去する仁とによって、基板表面の凹
凸の高低の差を小さくするかもしくは、同効果に加えて
前記絶縁膜表面の突起物の発生面積を最少と表らしめ、
以って写真蝕刻工程の精度の向上と金属配線の断切れ及
び写真蝕刻不良を減少させ死生導体装置を援兵するもの
である。
The present invention was developed in view of the above points, and the thickness of an insulating film that exists on a flat area and can be melted by high-temperature heat treatment is
By reducing the thickness of the insulating film existing on the side surface of the uneven portion or completely removing the thickness, the height difference between the unevenness on the substrate surface can be reduced, or in addition to the same effect, the thickness of the insulating film surface can be reduced. Expressing the area where protrusions occur as the minimum,
This improves the accuracy of the photolithography process, reduces metal wiring breaks and photoetching defects, and supports the life and death conductor device.

また上記半導体装置の製造方法は、凹凸部を有する半導
体領域上に高温熱処理によシ溶融可能な絶縁膜を形成す
る工程と、反応性イオン工、チングによ〉前記絶縁膜を
半導体領域に対して略垂直に工、チンダして平坦な領域
上に存在する前記絶縁膜の厚みを凹凸部の側面に存在す
る前記絶縁膜の厚みよシ薄く形成するかもしくは完全に
除去する工程と、高温熱処理によシ絶縁展を溶融する工
程とからなる。
The manufacturing method of the semiconductor device described above also includes a step of forming an insulating film that can be melted by high-temperature heat treatment on a semiconductor region having uneven portions, and applying the insulating film to the semiconductor region by reactive ion processing or etching. a step of machining and cindering the insulating film approximately vertically to make the thickness of the insulating film on the flat area thinner than the thickness of the insulating film existing on the side surface of the uneven portion, or completely removing the insulating film, and high-temperature heat treatment. The process consists of a step of melting the insulation layer.

更に本発明に係る半導体装置は前記絶縁膜を被覆する別
の絶縁性薄膜を有してもよい。
Furthermore, the semiconductor device according to the present invention may include another insulating thin film covering the insulating film.

以下、図面を参照して本発明の実施例を詳細に説明する
。第2−)乃至2伽)―は本発明に係るlチャネルシリ
;ンr−)MOE!)ツンゾスタの製造工程図であゐ、
tず第2(a)図に示すように、P型シリ;ン基板11
e上に厚さ1μのシリコン酸化膜を形成し、写真蝕刻法
によルソース、ドレインとダート形成予定領域のシリコ
ン酸化膜を除去してフィールド絶縁膜112を形成する
0次に露出したシリプン基板9110上に厚さ長法によ
シ形成する。そO彼第2(b)図に示すように写真蝕刻
法によJ)r−)電極118と配線/4ターン120を
形成し、更にr−)電極ixaをマスクとしてソース、
ドレ゛イン形成予定領域のシリコン酸化膜114を除去
してr−)絶縁膜122を形成する0次にオキシ塩化燐
(Pock、)写囲気中で1000℃、10分の高温熱
処理を実施することによりてr−)電極118と配線パ
ターン120に燐を拡散させて低抵抗化させる。
Embodiments of the present invention will be described in detail below with reference to the drawings. 2-) to 2-)-- are the l-channel series according to the present invention; r-) MOE! ) Manufacturing process diagram of Tunzosta.
As shown in FIG. 2(a), a P-type silicon substrate 11
A silicon oxide film with a thickness of 1 μm is formed on the silicon oxide film 9110 exposed to the 0th order on which a field insulating film 112 is formed by removing the silicon oxide film in the regions where the source, drain and dirt are to be formed by photolithography. Form on top by thickness length method. Then, as shown in FIG. 2(b), the r-) electrode 118 and the wiring/four turns 120 are formed by photolithography, and the source, r-) electrode ixa is used as a mask.
A high temperature heat treatment is performed at 1000° C. for 10 minutes in a zero-order phosphorus oxychloride (Pock) atmosphere to remove the silicon oxide film 114 in the region where the drain is to be formed and form the r-) insulating film 122. Accordingly, phosphorus is diffused into the r-) electrode 118 and the wiring pattern 120 to lower the resistance.

また同時に露出したシリコン基板110にも燐を拡散さ
せてN+型□のソース領域124とドレイン領域126
を形成する0次に第2(C)図に示すように高温酸化に
よυr−)電極111と配線パターン110及び露出し
氏シリコン基板110上に約1000Xの酸化膜ixa
を形成して絶縁被覆し、素子保護用の厚さ5ooo又の
アンド−lドシリコン酸化膜110を形成する1次にシ
リコン基板全面に燐もしくは燐と硼素が添加された厚さ
5oool oシリコン酸化膜(ドープド134を開孔
する0次に第2(・)図に示すように例、tハフ L/
# ン(CF4) j OgCCM、水#c(H2)J
 # 1100M雰囲気でΔツー350W0反応性イオ
ンエツチングを11分間行う、この場合のドーグドシリ
コン酸化族112の工、チンダレイトは40017分で
あるので、基板に対して**方向にP−f)”/リコン
酸化j1 s !I J h 5zooX @14方的
に工、チンダされる。従りて平坦な領域に形成されたド
ープドシリコン酸化M J J x aは完全に除去さ
れるが、凹凸部の側面に形成され九ドーlドシリーン駿
化膜1sxbo厚みは略5ooo1以上と表る。なおシ
リコン基板110は一部露出されているが、との反応性
イオン工。
At the same time, phosphorus is also diffused into the exposed silicon substrate 110 to form an N+ type □ source region 124 and drain region 124.
Next, as shown in FIG. 2(C), an oxide film of about 1000X is formed on the electrode 111, the wiring pattern 110, and the exposed silicon substrate 110 by high-temperature oxidation.
1. Next, a 500 mm thick undo silicon oxide film 110 with a thickness of 5 mm for protecting the device is formed. 1. Next, a 5 mm thick silicon oxide film doped with phosphorus or phosphorus and boron is formed on the entire surface of the silicon substrate. (Doped 134 hole opening 0th order 2nd (・) example, t Huff L/
# N (CF4) j OgCCM, water #c (H2) J
# Perform Δ2 350W0 reactive ion etching for 11 minutes in a 1100M atmosphere. In this case, the doped silicon oxide group 112 etching time is 40017 minutes, so P-f) in the ** direction with respect to the substrate. Silicon oxide j1 s !I J h 5zoo The thickness of the silicone film 1sxbo formed on the side surface is approximately 5 mm or more.Although a portion of the silicon substrate 110 is exposed, it is etched by reactive ion processing.

チングではシリコンは工、チングされ表い。In the process, silicon is processed and processed.

次に第2(禮囚に示すようにドープドシリコン酸化膜1
31bを被覆もしくは保饅するため全面に厚さ500X
のアンド−ブトシリコン酸化膜IJ−を形成する。その
後第2(−図に示すようにオキシ塩化燐雰囲気中で10
00℃、5分の高温熱処理を行い、ドープドシリコン酸
化属111bを溶融して基板表面の凹凸を平滑化させる
。更に再び写真蝕刻法によルコンタタトIIJJ4の厚
さ56σlのアンドーグドシリコン酸化属1111を除
去する0次に第2(締図に示すようにアル建を蒸着して
厚さ1μのアル蜜層を形成し、写真蝕刻法によプアル建
配鱒sagを設け、nチャネルシリコンp−)MOS)
ツ/ゾスタを完成させる。
Next, the second (doped silicon oxide film 1 as shown in the figure)
Thickness 500X on the entire surface to cover or protect 31b
An unbuttoned silicon oxide film IJ- is formed. Then the second (-10
A high-temperature heat treatment is performed at 00° C. for 5 minutes to melt the doped silicon oxide metal 111b and smooth the unevenness on the substrate surface. Furthermore, the undoped silicon oxide metal 1111 with a thickness of 56σl of Lecontatato IIJJ4 was removed again by photolithography. In the second step (as shown in the final drawing), an aluminum layer was evaporated to form a 1μ thick layer of aluminum. A p-channel silicon MOS (n-channel silicon p-MOS)
Complete Tsu/Zosta.

上記のように形成し九牛導体素子は、ドープドシリコン
酸化膜を形成する工程あるいは、高温熱処理によ〉溶融
する工程で発生するドープドシリーン酸化展表面の突起
物の発生面積を小さくできるので、以後の工程に訃ける
アル省配線の断切れ中写真蝕刻不東を減少させることが
でき、アル省配線の信頼性を向上させることができる。
The conductor element formed as described above can reduce the area of protrusions on the doped silicon oxide surface that are generated during the process of forming the doped silicon oxide film or the process of melting it by high-temperature heat treatment. Therefore, it is possible to reduce photo-etching failure during disconnection of the aluminum-saving wiring, which may occur in subsequent processes, and improve the reliability of the aluminum-saving wiring.

また従来の半導体装置に比べてその厚さを薄くできるの
で基板表面の凹凸の高低を小さくでき、写真蝕刻工程に
おける精度も向上できる利点がある。
Furthermore, since the thickness of the semiconductor device can be made thinner than that of conventional semiconductor devices, the height of irregularities on the substrate surface can be reduced, and the accuracy in the photolithography process can be improved.

なお上記実施例で祉平坦な領域上のドー!ドシリ;ン酸
化gll1mを完全に除去したが、このドーlドシリコ
ン酸化膜IJ11を反応性イオンエツチングによル完全
に除去するのではなく、平坦な領域上に存在するドーグ
ド、シリコン酸化膜の厚みを凹凸部の@1ilK存在す
るドープドシリコン酸化属の厚みよル薄く形成するだけ
でも写真蝕刻工1i0精度向上の点で好結果が得られる
ことは言うまでもな1゜ また上記実施例では鳳チャネルシリーンr −) MO
JI )ツンジスタについて説明したがPチャネルMO
8)ツンジスタにもあるいはMO8キャノシタ等O他の
半導体素子にも適用できる。
In addition, in the above example, the do! on a flat area! Although the doped silicon oxide film IJ11 was completely removed by reactive ion etching, the thickness of the doped silicon oxide film existing on the flat area was reduced. It goes without saying that good results can be obtained in terms of improving the accuracy of photolithography even if the thickness of the doped silicon oxide metal present in the uneven parts is made thinner. ) M.O.
JI) I explained about Tunjistar, but P channel MO
8) It can be applied to a tungister or other semiconductor devices such as an MO8 capacitor.

更に高温熱処理により溶融可能な絶縁膜としてはドーグ
ドシリコン酸化膜に限らず他O絶縁膜を使用してもよい
し、配線としてはアル建に限らず他の金属であってもよ
−。
Further, the insulating film that can be melted by high-temperature heat treatment is not limited to the doped silicon oxide film, and other O insulating films may be used, and the wiring is not limited to Aluminum, but may be made of other metals.

以上詳述し九如く、本発明によれば必要な凹凸の側面に
のみ平滑用絶縁膜を厚く形成し溶融することによって、
金属配線の平滑化用絶縁膜に発生する突起物による金属
配線の断切れと写真蝕刻不要を減少した高信頼性の半導
体装置とその製造方法を提供できる。
As described in detail above, according to the present invention, by forming and melting a thick smoothing insulating film only on the side surfaces of necessary unevenness,
It is possible to provide a highly reliable semiconductor device and a method for manufacturing the same in which cut-off of metal wiring due to protrusions occurring in an insulating film for smoothing metal wiring and the need for photoetching are reduced.

【図面の簡単な説明】 第1(荀乃至1(e)図は従来の平滑化方法によるnチ
ャネルシリコy+’−)MOS)ツンジスタの製造工程
を示す断面図、第2(→乃至2伽)図は本発明による墓
チャネルシリコンr−)MOS)ツンジスタの製造工程
を示す断面図である。 Lし→ 10.110−シリコン基板、12.11:t、・・フ
ィールド酸化膜、14,114−・シリコン酸化膜、1
i*11g−・多結晶シリコン層、1a、11#−9”
−)電極、10.110−配線/f / −ン、xz、
xxx−r−ド絶縁膜、24゜J J 4−・ソース領
域、xi、xxi−ドレイン領域、2g、121−・徽
化膜、J#、JJ#−アンド−lドシリ;ン酸化膜1.
sx、xxz。 131*、111b−ドープドシリーン酸化膜、34.
134・・・コンタクト、1g、11g−アンドーグド
シリコン酸化膜、M a 、 11 # ””アル省配
線、4o、41−突起物。
[BRIEF DESCRIPTION OF THE DRAWINGS] The first (Xu to 1(e) is a sectional view showing the manufacturing process of a Thungister (n-channel silicon y+'-) MOS by the conventional smoothing method), the second (→ to 2) The figures are cross-sectional views illustrating the manufacturing process of a grave channel silicon (r-) MOS) tunnel transistor according to the present invention. L → 10.110-silicon substrate, 12.11:t,...field oxide film, 14,114--silicon oxide film, 1
i*11g-・Polycrystalline silicon layer, 1a, 11#-9”
-) electrode, 10.110-wiring/f/-on, xz,
xxx-r-dosilicon film, 24°J J 4-source region, xi, xxi-drain region, 2g, 121-dosilicon film, J#, JJ#-and-l dosilicon oxide film 1.
sx, xxz. 131*, 111b-doped silicon oxide film, 34.
134...Contact, 1g, 11g - Undoped silicon oxide film, M a , 11 # "" Al-saving wiring, 4o, 41 - Projection.

Claims (7)

【特許請求の範囲】[Claims] (1)  高温熱処理によシ溶融可能な絶縁膜を有する
半導体装置に於いて、平担な領域上に存在する前記絶縁
膜O厚みが、凹凸部の側面に存在する前記絶縁膜O厚み
よル薄いかもしくは平担な領域上に社前記絶縁膜は存在
しないことを特徴とする半導体装置。
(1) In a semiconductor device having an insulating film that can be melted by high-temperature heat treatment, the thickness of the insulating film O existing on a flat area is greater than the thickness of the insulating film O existing on the side surface of an uneven portion. A semiconductor device characterized in that the insulating film does not exist on a thin or flat region.
(2)前記絶縁膜を覆う別の絶縁性薄膜を有することを
特徴とする特許請求の範囲第(1)項記載O半導体装置
(2) The semiconductor device according to claim (1), further comprising another insulating thin film covering the insulating film.
(3)前記絶縁膜紘鱗添加シリ;ン酸化展もしくは硼素
と燐が添加されたシリブン酸化展であことを特徴とする
特許請求の範囲第0)よまたは第(2)項記載O半導体
装置。
(3) The semiconductor device according to claim 0) or claim 2, characterized in that the insulating film is made of oxidized silicon or silicon oxidized to which boron and phosphorus are added. .
(4)凹凸部を有する半導体領域上に高温熱処理によ)
II融可能1klsl縁−を形成する工1と、反応性イ
オン工、チンダによ〉前記絶縁膜を半導体領域に対して
略垂直にエツチングして平坦な領域上に存在する前記絶
縁属の厚みを凹凸部の側面に存在する前記絶縁膜の厚み
よシ薄く形成するかもしくは完全に除去する工程と、高
温熱処理によ〕絶縁膜を溶融する工程とをAIthlシ
たことを特徴とする半導体装置の製造方法。
(4) High-temperature heat treatment on semiconductor regions with uneven parts)
Step 1 of forming a fusible 1klsl edge and reactive ion etching, etching the insulating film approximately perpendicularly to the semiconductor region to reduce the thickness of the insulating metal present on the flat region. A semiconductor device characterized in that the step of forming the insulating film on the side surface of the uneven portion to be thinner than the thickness or completely removing it, and the step of melting the insulating film by high temperature heat treatment are performed. Production method.
(5)前記絶縁膜を溶融する前に前記絶縁膜を覆うよう
に別の絶縁性薄膜を形成することを特徴とする特許請求
の範囲第(4)項記載の半導体装置の製°造方法。
(5) The method for manufacturing a semiconductor device according to claim (4), characterized in that, before melting the insulating film, another insulating thin film is formed to cover the insulating film.
(6)前記反応性イオンエツチングによシ凹凸部の少な
くとも側面に前記絶縁膜を残すことを特徴とする特許請
求の範囲第(4)項または第(5)項記載の半導体装置
の製造方法。
(6) The method of manufacturing a semiconductor device according to claim 4 or 5, wherein the insulating film is left on at least the side surfaces of the uneven portion by the reactive ion etching.
(7)  前記絶縁膜は燐添加シIJ jン酸化膜もし
くは硼素と燐が添加され九シリコン酸化膜であることを
特徴とする特許請求の範囲第(4)項攻いし第(6)項
のいずれかに記載の半導体装置の製造方法。
(7) The insulating film is a phosphorous-doped silicon oxide film or a boron and phosphorus-doped silicon oxide film, A method for manufacturing a semiconductor device according to any one of the above.
JP13052181A 1981-08-20 1981-08-20 Manufacture of semiconductor device Granted JPS5832434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13052181A JPS5832434A (en) 1981-08-20 1981-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13052181A JPS5832434A (en) 1981-08-20 1981-08-20 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5832434A true JPS5832434A (en) 1983-02-25
JPS6320383B2 JPS6320383B2 (en) 1988-04-27

Family

ID=15036281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13052181A Granted JPS5832434A (en) 1981-08-20 1981-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5832434A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111470A (en) * 1983-11-22 1985-06-17 Fujitsu Ltd Manufacture of semiconductor device
JPS62274641A (en) * 1986-05-22 1987-11-28 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5420077A (en) * 1990-06-29 1995-05-30 Sharp Kabushiki Kaisha Method for forming a wiring layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221785A (en) * 1975-08-13 1977-02-18 Toshiba Corp Unit and production system for semiconductor
JPS52102691A (en) * 1976-02-25 1977-08-29 Hitachi Ltd Formation of wiring on insulating layer having steps
JPS5324277A (en) * 1976-08-18 1978-03-06 Nec Corp Semiconductor devic e and its production

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5221785A (en) * 1975-08-13 1977-02-18 Toshiba Corp Unit and production system for semiconductor
JPS52102691A (en) * 1976-02-25 1977-08-29 Hitachi Ltd Formation of wiring on insulating layer having steps
JPS5324277A (en) * 1976-08-18 1978-03-06 Nec Corp Semiconductor devic e and its production

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111470A (en) * 1983-11-22 1985-06-17 Fujitsu Ltd Manufacture of semiconductor device
JPS62274641A (en) * 1986-05-22 1987-11-28 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5420077A (en) * 1990-06-29 1995-05-30 Sharp Kabushiki Kaisha Method for forming a wiring layer

Also Published As

Publication number Publication date
JPS6320383B2 (en) 1988-04-27

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