JPS5856261B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for stably manufacturing high-density semiconductor integrated circuits.

FIG. 1 shows an example of a silicon-Ga-1-MO8 type semiconductor integrated circuit memory using conventional phosphosilicate glass (hereinafter abbreviated as PSG).

Part A is a region having a thick oxide film that separates active regions, and part B is an active region.

FIG. 1a shows a state in which the formation of a thick oxide film, the etching of the active region, and the formation of the gate region are omitted, and a PSB film is deposited on the entire surface.

Here, 1 is a substrate, 2 is a thick oxide film in the non-active region, and 3 is a PSG film.

By performing heat treatment under certain conditions as shown in FIG.

The state is shown in Figure 1.

At this time, by appropriately selecting the concentration of phosphorus in the PSG film and the heat treatment conditions, the depth and sheet resistance of the N+ diffusion layer can be determined, and the stepped portion 8 is smoothed due to the FLOW effect of the PSG film.

Next, a contact hole 5 for metal wiring of the N1 diffusion layer 4 is etched (FIG. 1C).

At this time, the thickness of the PSG film 3 must be such that it can cover the stepped portion well.

Further, in order to reduce the capacitance between the metal wiring and the conductive gate polycrystalline silicon, it is desirable that the thickness be thicker.

After etching the contact hole 5, a marking layer metal such as aluminum 6 is deposited by sputter deposition or electron beam deposition.

At this time, if the PSG film 3 is thick and the metal wiring layer 6 is thin, metal wire breakage is likely to occur at the stepped portion 7 of the contact hole 5.

As described above, the conventional method has the disadvantage that if the PSG film 3 is made thicker in order to ensure stoop coverage and reduce stray capacitance, the metal wiring may be disconnected within the contact hole.

An object of the present invention is to reduce the level difference in the contact hole in order to eliminate these drawbacks, and will be described in detail below.

FIG. 2 shows an embodiment of the present invention, taking an MO8 type semiconductor integrated circuit memory as an example.

1 is a substrate, 2 is a thick oxide film in the non-active region, 3 is a PSG film, 4 is an N+ layer, 5 is a contact hole, 6 is a wiring metal, 7 is a stepped portion, and 14 is a diffusion region within the contact hole.

The steps up to the step of depositing the PSG film on the entire surface are the same as the conventional method shown in FIG.

In the conventional method, heat treatment is then performed to perform FLOW and N+ diffusion of the PSG film, but in this method, the contact hole 5 is first
(Fig. 2b).

After that, heat treatment is performed.

If the atmosphere during this heat treatment does not contain diffusion impurities, the inside of the contact hole will have the same conductivity type as the substrate, and the diffusion layer 4 will be PN.
A bond cannot be formed and a good electrode cannot be formed.

Therefore, in this method, during the heat treatment for FLOW of the PSG film and diffusion from the PSG film, the inside of the contact hole that has already been opened is also converted to N type, so for example, phosphorus oxychloride (POCl2
) is used as an impurity source and a gas atmosphere containing N-type impurities is used.

By doing this, it also diffuses into the contact hole (area 1
4) It is possible to make good electrodes.

Further, since the contact hole 5 is heat treated after etching, the stepped portion 7 can be made smooth.

(Fig. 2C) However, in this case, POC is present on the surface of the contact hole.
A thin oxide film containing l2 is formed, and the existing PSG
Since the membrane flows into the contact hole, the electrode cannot be removed as it is.

Therefore, appropriate treatment is performed to expose the surface of the contact hole.

Appropriate processing involves gradually etching the entire surface using the difference in oxide film thickness, and may be completed when the surface of the contact hole is exposed, or a new mask process may be performed to form the contact hole. You can.

In this case, the same mask as used in FIG. 2 can be used.

After that, electrode wiring is applied.

(Fig. 2 d) As explained above, in this embodiment, after etching the contact hole, heat treatment is performed in an atmosphere containing N-type impurities, so the step in the contact hole becomes smooth and disconnection of the metal wiring can be prevented. It also has the advantage that good electrodes can be extracted.

In addition, in the conventional method, the surface concentration of the contact hole was determined by the concentration of the PSG film, but in this method, the surface concentration of the contact hole can be determined independently of the concentration of the PSG film, so it is possible to obtain a surface with a high concentration of metal. It also has the advantage of reducing contact resistance with wiring.

Also, the contact hole was for single crystal silicon,
In the MO8 type silicon semiconductor integrated circuit, polycrystalline silicon located in part A is also used, and the same effect is produced for the contact hole therefor.

The present invention has the advantage of forming a high-density MO8 type semiconductor integrated circuit memory stably and with a high yield, and can be applied to all kinds of semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing a conventional integrated circuit manufacturing method, and FIG. 2 is a process sectional view showing an example of an integrated circuit manufacturing method according to the present invention. 1...Silicon substrate, 2...Thick oxide film in non-active region, 3...PSG film, 4...
... N+ layer, 5 ... Contact hole, 6 ... Metal wiring, 7 ... Shoulder part of step of contact hole, 8
・・・・・・Shoulder part of the thick oxide film step in the non-active area, 14・・・N+ layer (by vapor phase diffusion), A part・
...Inactive area, part B...Active area.

Claims (1)

[Claims] 1. A step of selectively forming an insulating film on the main surface of a semiconductor substrate, a step of depositing a phosphosilicate glass layer over the entire main surface of the substrate including the insulating film, and selectively removing the phosphosilicate glass layer. a step of exposing the surface portion before applying the glass layer; and a heat treatment in an atmosphere containing N-type impurities to smooth the surface of the glass layer and remove and expose the phosphosilicate glass layer. a step of diffusing an N-type impurity into the surface portion where the N-type impurity has been diffused; a step of removing an oxide film formed on the surface portion into which the N-type impurity has been diffused by the heat treatment to expose this surface portion again; 1. A method of manufacturing a semiconductor integrated circuit, comprising the step of forming an electrode wiring layer including the re-exposed surface portion.