JPS60245159A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high insulating withstand strength between the first and the second gate electrodes by forming the first gate electrode, then accumulating an insulator, and removing the insulating film only at the portion for forming the second gate oxide film, and forming the second gate oxide film. CONSTITUTION:The second gate electrode 9 is accumulated on an Si substrate 8 formed with a field oxide film 7 and the first gate oxide film 6, and desired pattern is formed. Then, an insulator film 20 is accumulated. Thereafter, only the film 20 is removed only on the portion to be formed with the second gate oxide film to expose the substrate 8. Then, the second gate oxide film 11 is formed. Subsequently, the second gate electrode 12 is accumulated to form a desired pattern. According to this method, the electrodes 9 and 12 are insulated by the film 20, and even if the thickness of the film 20 is formed in the thickness necessary to obtain required insulating withstand voltage between the electrodes 9 and 12, the thickness of the film 11 may be formed in the thickness necessary to obtain desired transistor characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing semiconductor integrated circuits, particularly high-density dynamic memories (hereinafter referred to as DRAMs).

2. Description of the Related Art Conventional Structures and Problems Semiconductor devices have recently become more and more densely packed and have higher performance, and this trend is particularly noticeable in semiconductor memories such as DRAMs. In order to increase the density of semiconductor devices, microfabrication techniques are being used to miniaturize semiconductor devices.

In order to miniaturize MO8 type transistors constituting a DRAM, it is necessary to reduce the gate oxide film thickness in addition to shortening the gate length, increasing the impurity concentration and reducing the diffusion depth. Now, in the DRAM manufacturing process, due to the thinning of this gate oxide film, there is a problem in that the dielectric breakdown voltage of the first gate electrode and the second gate electrode is reduced. The above problem will be explained below using figures.

FIG. 1 is a plan view of a DRAM memory cell according to a conventional method, in which a first gate electrode 3 is formed on the surface of a diffusion region 1, and a second gate electrode 4 is provided with an interlayer insulating film interposed therebetween. ing. Note that it is assumed here that the first gate electrode 3 and the second gate electrode 4 are made of polycrystalline silicon.

The manufacturing process of the structure shown in FIG. 1 is shown in FIG. 2 (al to (0)). First, as shown in FIG. and a first gate oxide film 6 is formed.Next, after depositing a first gate electrode 9, a desired pattern is formed by photolithography and etching techniques.The first gate electrode 9 is used as an etching mask. By removing the first gate oxide film 6, the surface of the semiconductor substrate 8 is exposed.

This is shown in FIG. 2(b).

Next, when oxidation is performed, a desired second gate oxide film 11 is formed on the surface of the semiconductor substrate 8 due to the difference in oxidation rate between the semiconductor substrate 8 and the first gate electrode 9, and a desired second gate oxide film 11 is formed on the surface of the first gate electrode 9. In this case, the oxide film 1o of the first gate electrode 9 is formed as an interlayer insulating film. In this case, FIG. 3 shows the relationship between oxidation time and oxide film thickness when silicon is used as the semiconductor substrate 8 and N-type polycrystalline silicon is used as the first gate electrode 9.

16 is the thickness of the oxide film grown on the semiconductor substrate 8, 14 is the first
It shows the relationship between the thickness of the oxide film grown on the gate electrode 9.

In this way, if a thick second gate oxide film 11 is required, a thick first gate electrode oxide film 11 is required.
However, if a thin second gate oxide film 11 is required, it becomes difficult to obtain an oxide film 1o of the first gate electrode with sufficient dielectric strength. Also,
Even when a high melting point metal or its silicide is used as the first gate electrode 9, it becomes difficult to employ the method described above.

In view of the above-mentioned problems, the inventors of the present invention have found that it is possible to solve the above-mentioned problems by forming the interlayer insulating films of the first gate electrode 9 and the second gate electrode 12 independently. I discovered that.

OBJECTS OF THE INVENTION In view of these conventional problems, the present invention provides a method for manufacturing a high-density semiconductor device.

Structure of the Invention The present invention involves depositing an insulating film after forming a first gate electrode, removing the insulating film only in the portion where the second gate electrode is to be formed, exposing the surface of the semiconductor substrate, and then depositing the second gate electrode. By forming a gate insulating film, the dielectric breakdown voltage of the first gate electrode and the second gate electrode is increased, thereby making it possible to manufacture a stable semiconductor device.

Embodiment 5 FIG. 4 is a plan view of a main part of a DRAM memory cell according to an embodiment of the present invention. Note that many of the numbers in the figure are the same as those of the conventional example so that there is no risk of confusion. In FIG. 4, an opening region 13 in the insulating film between the first gate electrode 3 and the second gate electrode 4 is formed. A more detailed explanation will be given with reference to FIGS. 6(a) to 6(f), which are cross-sectional views of the manufacturing process of a memory cell portion of a DRAM according to an embodiment of the present invention.

As shown in FIG. 6 (1!L), a field oxide film 7 and a first gate oxide film 6 are formed on the surface of a silicon substrate 8 by a well-known method. Next, as shown in FIG. 6(b), a second gate electrode 9 is deposited to form a desired pattern. Next, as shown in FIG. 6(0), an insulating film 2o is deposited. Next, as shown in Figure 6(d), the second
The insulating film 2 is applied only to the portion where the gate oxide film is to be formed.
o is removed to expose the surface of the silicon substrate 8. Next, as shown in FIG. 6 (θ), second gate oxidation is performed,
A second gate oxide film 11 is formed. Thereafter, the second gate electrode 12 is deposited to form a desired pattern (FIG. 6 (shown in crocodile)).

In this embodiment, the first gate electrode 9 and the second gate electrode 12 are insulated by an insulating film 20, and the thickness of the insulating film 2o is set between the first gate electrode 9 and the second gate electrode 12. Even if the second gate oxide film 11 is formed to a thickness necessary to obtain the dielectric strength voltage required between the two, the second gate oxide film 11 can be formed to a thickness necessary to obtain the desired transistor characteristics. .

In the above embodiments, the case where the first gate electrode is made of polycrystalline silicon has been considered, but the present invention also applies when the first gate electrode is made of a high melting point metal or the like, where it is difficult to obtain a thick insulating oxide film. It goes without saying that it is effective to put the invention into practice.

Effects of the Invention As described above, in the present invention, after forming the first gate electrode,
When a thin second gate oxide film is formed by depositing an insulating film and removing the insulating film only in the portion where the second gate oxide film is to be formed, thereby forming the second gate oxide film. However, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which make it possible to obtain a high dielectric breakdown voltage between a first gate electrode and a second gate electrode.

[Brief explanation of the drawing]

Figure 1 is a plan view of a conventional DRAM memory cell.
a+ to (C) are cross-sectional views of the manufacturing process of the memory cell portion of a conventional DRAM, FIG. 3 is a diagram showing the relationship between oxidation time and oxide film thickness, and FIG. 4 is a diagram of a DRAM memory according to an embodiment of the present invention. A plan view of the cell, and FIGS. 6(a) to 6(a) are cross-sectional views of the manufacturing process of a memory cell portion of a DRAM which is an embodiment of the present invention. 8...Silicon substrate, 9... ...First gate electrode, 1o... Oxide film of first gate electrode, 11.
...Second gate oxide film, 12...Second gate electrode, 13...Opening region of insulator film, 20
...Insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4 of Tuyanhua Xuan

Claims (1)

[Claims] After forming the first gate electrode, depositing an insulating film;
A method for manufacturing a semiconductor device, comprising removing only a portion of the insulating film where a second gate insulating film is to be formed, and then forming the second gate insulating film.