JPS6342146A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS6342146A
JPS6342146A JP18631586A JP18631586A JPS6342146A JP S6342146 A JPS6342146 A JP S6342146A JP 18631586 A JP18631586 A JP 18631586A JP 18631586 A JP18631586 A JP 18631586A JP S6342146 A JPS6342146 A JP S6342146A
Authority
JP
Japan
Prior art keywords
film
oxide film
polycrystalline silicon
gate oxide
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18631586A
Other languages
Japanese (ja)
Inventor
Shuichi Enomoto
秀一 榎本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18631586A priority Critical patent/JPS6342146A/en
Publication of JPS6342146A publication Critical patent/JPS6342146A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the structure of excellent multilyer interconnections without step cutting and the like, by smoothing the edge part of a conductor layer comprising polycrystalline silicon. CONSTITUTION:A polycrystalline silicon film 3 is entirely etched until the thin part beneath an oxide film 6 is eliminated. With the remaining polycrystalline silicon film 3 as a mask, a gate oxide film 2 is removed. Then, a second gate oxide film 8 and an insulating oxide film 9 are formed on the exposed surface of a silicon substrate 1 and the polycrystalline silicon film 3 by hydrogen burning oxidation. The gate oxide film 8 is removed by wet etching. A second gate oxide film 8a is formed again by dry oxidation this time. At this time, the insulating oxide film 9 is also etched once. An oxide film 9a is obtained by dry oxidation. A polycrystalline silicon film 10 is deposited on the gate oxide film 8a and the oxide film 9a to form the upper conductor layer. Thus the conductor layer, which comprises a polycrystalline silicon layer and has a smooth edge, is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に多層電極の
形成方法を含む半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a method of forming a multilayer electrode.

〔従来の技術〕[Conventional technology]

一般に、ダイナミック型のMOSメモリあるいはCCD
デバイスには二層多結晶シリコン構造が採用されている
が、従来の製造方法を以下に説明する。
Generally, dynamic MOS memory or CCD
The device employs a two-layer polycrystalline silicon structure, and a conventional manufacturing method will be described below.

第3図(a)〜(c)は従来の半導体装置の製造方法を
説明するための工程順に示した半導体チップの断面図で
ある。
FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device.

先ず、第3図(a>に示すように、シリコン基板1上に
熱酸化により第1のゲート絶縁膜2を形成した後、多結
晶シリコン膜3′を成長させ、N型不純物、例えばりん
を拡散する。
First, as shown in FIG. 3 (a), a first gate insulating film 2 is formed on a silicon substrate 1 by thermal oxidation, a polycrystalline silicon film 3' is grown, and an N-type impurity, for example, phosphorus is added. Spread.

次に、第3図(b)に示すように、周知のホトリソグラ
フィ技術で多結晶シリコン3′及びゲート絶縁膜2をエ
ツチングする。その際、一般に、不純物が拡散された多
結晶シリコンのエツチング速度は速いのでザイドエッチ
ングはほとんどなく多結晶シリコン3′のエツジは非常
に急峻になっている。
Next, as shown in FIG. 3(b), the polycrystalline silicon 3' and the gate insulating film 2 are etched using a well-known photolithography technique. At this time, since the etching rate of polycrystalline silicon into which impurities have been diffused is generally fast, there is almost no oxide etching and the edges of the polycrystalline silicon 3' are very steep.

次に、第3図(C)に示すように多結晶シリコン3′を
酸化して眉間絶縁膜の酸化膜9′を形成すると同時にシ
リコン基板1上にも第2のゲート絶縁膜8′を形成する
。その後、第2の多結晶シリコン10’を成長後多結晶
シリコン膜3′と同様にN型不純物としてりんを拡散す
る。
Next, as shown in FIG. 3(C), the polycrystalline silicon 3' is oxidized to form an oxide film 9' for the glabellar insulating film, and at the same time, a second gate insulating film 8' is also formed on the silicon substrate 1. do. Thereafter, after growing the second polycrystalline silicon 10', phosphorus is diffused as an N-type impurity similarly to the polycrystalline silicon film 3'.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置の製造方法では、多結晶シリ
コンの導体層のエツジが急峻であるので、その上に、層
間絶縁膜と上層の多結晶シリコンからなる導体層とを堆
積するにつれて段差部の凹凸がますます激しくなって第
3図(C)に示すような角7′のような形状になり均一
に覆うことが出来ず段切れ等を起しやすくなるという欠
点がある。
In the conventional semiconductor device manufacturing method described above, the edge of the polycrystalline silicon conductor layer is steep, so as the interlayer insulating film and the upper layer of the polycrystalline silicon conductor layer are deposited on top of the edge, the step portion is formed. There is a drawback that the irregularities become more severe and take on the shape of a corner 7' as shown in FIG. 3(C), making it impossible to cover uniformly and making it easy to cause breakage and the like.

〔問題点を解決するための手段〕[Means for solving problems]

半導体基板表面に絶縁膜、多結晶シリコン膜。 Insulating film and polycrystalline silicon film on the surface of the semiconductor substrate.

第1の酸化膜及び耐酸化性膜を順次形成する工程、少く
とも前記耐酸化性膜及び前記第1の酸化膜を選択的に順
次除去して前記多結晶シリコン膜に所定の膜厚の露出部
を形成する工程、前記耐酸化性膜をマスクとして前記露
出部を酸化して第2の酸化膜を形成する工程及び前記耐
酸化性膜、前記第1及び第2の酸化膜を除去する工程を
含み前記多結晶シリコン膜からなる滑らかなエツジを備
えた導体層を形成して成る。
a step of sequentially forming a first oxide film and an oxidation-resistant film; selectively and sequentially removing at least the oxidation-resistant film and the first oxide film to expose the polycrystalline silicon film to a predetermined thickness; a step of forming a second oxide film by oxidizing the exposed portion using the oxidation-resistant film as a mask; and a step of removing the oxidation-resistant film, the first and second oxide films. A conductive layer with smooth edges made of the polycrystalline silicon film is formed.

〔実 h市 例 〕[Actual city example]

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(f)は本発明の第1図の実施例を説明
するための工程順に示した半導体チ・ツブの断面図であ
る。
FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the embodiment of FIG. 1 of the present invention.

先ず、第1図(a>に示すように、シリコン基板1上に
、酸化によって、100人の薄い第1のゲート酸化膜2
を形成し、更に、CVD法によって5000人の多結晶
シリコン膜3を堆積し、た後にP OCe 3を拡散源
としてりんを拡散する。続いて、厚さ1000人のCV
Dの酸化膜4及び厚さ500人の窒化膜5を順次形成す
る。
First, as shown in FIG.
A polycrystalline silicon film 3 of 5,000 layers is further deposited by the CVD method, and then phosphorus is diffused using P OCe 3 as a diffusion source. Next, a CV with a thickness of 1000 people
An oxide film 4 having a thickness of D and a nitride film 5 having a thickness of 500 mm are sequentially formed.

次に、第1図(b)に示すように、ホトリソグラフィ技
術と反応性イオンエツチングとにより、所定のパターン
で、窒化膜5.酸化膜4及び多結晶シリコン膜3を順次
エツチングして、膜厚3000人程度0多結晶シリコン
膜3の露出部を形成する。
Next, as shown in FIG. 1(b), the nitride film 5. The oxide film 4 and the polycrystalline silicon film 3 are sequentially etched to form an exposed portion of the polycrystalline silicon film 3 with a thickness of approximately 3,000 mm.

次に、第1図(c)に示すように、窒化膜5をマスクに
して1000’Cの水素バーニング酸化により多結晶シ
リコン膜3の露出部に酸化膜6を形成し、その下の多結
晶シリコン膜3が1000人程度人程ようにする。この
時、窒化膜5の端の下の部分の酸化t15!6がバーズ
ビーク7のような形になる。なおここで、酸化膜6を形
成するときに、多結晶シリコン膜3に含まれるりんがパ
イルアップして、ゲート酸化膜2を通してシリコン基板
1−に達しないように酸化膜6の下に多結晶シリコン膜
3を500〜2000人程度残す必要がある。
Next, as shown in FIG. 1(c), an oxide film 6 is formed on the exposed portion of the polycrystalline silicon film 3 by hydrogen burning oxidation at 1000'C using the nitride film 5 as a mask, and The silicon film 3 should have a capacity of about 1,000 people. At this time, the oxidized portion t15!6 below the edge of the nitride film 5 takes the shape of a bird's beak 7. Note that when forming the oxide film 6, the polycrystalline silicon film 6 is formed under the oxide film 6 to prevent phosphorus contained in the polycrystalline silicon film 3 from pile-up and reaching the silicon substrate 1- through the gate oxide film 2. It is necessary to leave about 500 to 2,000 people in the silicon film 3.

次に、第1図(d)に示すように、窒化膜5゜酸化膜4
及び6を除去した後、反応性イオンエツチングによって
、多結晶シリコン膜3を酸化膜6の下の薄い部分が無く
なるまで全面エツチングする。更に、残った多結晶シリ
コン膜3をマスクとしてゲート酸化膜2を除去する。
Next, as shown in FIG. 1(d), nitride film 5° oxide film 4
After removing the oxide film 6 and 6, the entire surface of the polycrystalline silicon film 3 is etched by reactive ion etching until the thin portion under the oxide film 6 is removed. Furthermore, gate oxide film 2 is removed using remaining polycrystalline silicon film 3 as a mask.

次に、第1図<e)に示すように、850℃の水素バー
ニング酸化によりシリコン基板1及び多結晶シリコン膜
3の露出面にそれぞれ膜厚350人の第2のゲート酸化
膜8及び絶縁用の膜厚的1000″Aの酸化膜9を形成
する。
Next, as shown in FIG. 1<e), a second gate oxide film 8 and an insulating film are formed on the exposed surfaces of the silicon substrate 1 and the polycrystalline silicon film 3 with a thickness of 350 mm by hydrogen burning oxidation at 850°C. An oxide film 9 having a thickness of 1000''A is formed.

しかし、水素バーニング酸化により形成した酸化膜の絶
縁耐圧は、−iに、低いので、ゲート酸化膜8を湿式の
エツチングにより除去して、第1図(f)に示すように
、今度は950℃のドライ酸化により再度厚さ350人
の第2のゲート酸化膜8aを形成する。この際、絶縁用
の酸化膜9も一旦エッチングされて650人となるが、
ドライ酸化により厚さ約1000人の酸化膜9aとなる
。更に、ゲート酸化膜8a及び酸化膜9aの上に多結晶
シリコン膜10を堆積して上層の導体層を形成する。
However, the dielectric strength voltage of the oxide film formed by hydrogen burning oxidation is as low as -i, so the gate oxide film 8 is removed by wet etching at 950° C. as shown in FIG. 1(f). A second gate oxide film 8a having a thickness of 350 wafers is again formed by dry oxidation. At this time, the insulating oxide film 9 is also etched, resulting in 650 people.
By dry oxidation, an oxide film 9a having a thickness of approximately 1000 wafers is formed. Furthermore, a polycrystalline silicon film 10 is deposited on gate oxide film 8a and oxide film 9a to form an upper conductor layer.

第2図は本発明の第2の実施例を説明するための半導体
チップの断面図である。
FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

この実施例では、多結晶シリコン膜3の、導体層を形成
した後にりん珪酸ガラス(以降PSGと称す)膜11を
形成する。更に、ホトリソグラフィ技術を用いてPSG
膜11の多結晶シリコン膜3上にコンタクト用の窓を開
孔した後電子ビーム蒸着法によりA2を堆積し所定のパ
ターンに整形して多結晶シリコン膜3に接続したAe電
極12を形成する。
In this embodiment, a phosphosilicate glass (hereinafter referred to as PSG) film 11 is formed after the conductor layer of the polycrystalline silicon film 3 is formed. Furthermore, using photolithography technology, PSG
After a contact window is opened on the polycrystalline silicon film 3 of the film 11, A2 is deposited by electron beam evaporation and shaped into a predetermined pattern to form an Ae electrode 12 connected to the polycrystalline silicon film 3.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では多結晶シリコンからなる
導体層のエツジの部分を滑らかにするので、その上に積
層する絶縁膜や上の導体層がエツジの部分の上でも均一
に形成され、段切れ等の無い良好な多層配線構造を提供
できるという効果がある。
As explained above, in the present invention, the edges of the conductor layer made of polycrystalline silicon are smoothed, so that the insulating film laminated thereon and the upper conductor layer are uniformly formed even on the edges, and the edges of the conductor layer made of polycrystalline silicon are smoothed. This has the effect of providing a good multilayer wiring structure with no breaks or the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(f>は本発明の第′1の実施例を説明
するための工程順に示した半導体チップの断面図、第2
図は本発明の第2の実施例を説明するための半導体チッ
プの断面図、第3図<a)〜(c)は従来の半導体装置
の製造方法を説明するための工程順に示した半導体チッ
プの断面図である。 1・・・シリコン基板、2・・・ゲート酸化膜、3,3
′・・・多結晶シリコン膜、4・・・酸化膜、5・・・
窒化膜、6・・・酸化膜、7・・・バーズビーク、7′
・・・角、8゜8’ 、8a・・・ゲート酸化膜、9.
9′、9a・・・酸化膜、10.10’・・・多結晶シ
リコン膜、11・−・P S G膜、12・・・Aff
電極。 0誌)(d) (b)                      
  (e)(C)                 
            (fツギ / 凹 (C〕 (b)
1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention;
The figure is a cross-sectional view of a semiconductor chip for explaining the second embodiment of the present invention, and FIGS. FIG. 1... Silicon substrate, 2... Gate oxide film, 3, 3
'... Polycrystalline silicon film, 4... Oxide film, 5...
Nitride film, 6... Oxide film, 7... Bird's beak, 7'
...Angle, 8°8', 8a...Gate oxide film, 9.
9', 9a...Oxide film, 10.10'...Polycrystalline silicon film, 11...PSG film, 12...Aff
electrode. 0 magazine) (d) (b)
(e) (C)
(f Tsugi / Concave (C) (b)

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面に絶縁膜、多結晶シリコン膜、第1の酸
化膜及び耐酸化性膜を順次形成する工程、少くとも前記
耐酸化性膜及び前記第1の酸化膜を選択的に順次除去し
て前記多結晶シリコン膜に所定の膜厚の露出部を形成す
る工程、前記耐酸化性膜をマスクとして前記露出部を酸
化して第2の酸化膜を形成する工程及び前記耐酸化性膜
、前記第1及び第2の酸化膜を除去する工程を含み滑ら
かなエッジを備えた前記多結晶シリコン膜からなる導体
層を形成することを特徴とする半導体装置の製造方法。
a step of sequentially forming an insulating film, a polycrystalline silicon film, a first oxide film, and an oxidation-resistant film on the surface of a semiconductor substrate, selectively and sequentially removing at least the oxidation-resistant film and the first oxide film; a step of forming an exposed portion of a predetermined thickness in the polycrystalline silicon film; a step of oxidizing the exposed portion using the oxidation-resistant film as a mask to form a second oxide film; A method for manufacturing a semiconductor device, comprising the step of removing the first and second oxide films to form a conductor layer made of the polycrystalline silicon film with smooth edges.
JP18631586A 1986-08-08 1986-08-08 Manufacture of semiconductor Pending JPS6342146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18631586A JPS6342146A (en) 1986-08-08 1986-08-08 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18631586A JPS6342146A (en) 1986-08-08 1986-08-08 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPS6342146A true JPS6342146A (en) 1988-02-23

Family

ID=16186180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18631586A Pending JPS6342146A (en) 1986-08-08 1986-08-08 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS6342146A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5156572A (en) * 1989-12-18 1992-10-20 Mazda Motor Corporation Speed shift control system of a continuous transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5156572A (en) * 1989-12-18 1992-10-20 Mazda Motor Corporation Speed shift control system of a continuous transmission

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