JPS6118348B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having an element including a diffusion region, such as a transistor.

In conventional diffusion techniques for manufacturing semiconductor devices made of silicon semiconductors, before the thermal diffusion process, the entire thin silicon oxide film formed in the previous process is removed, or a highly concentrated impurity glass layer is used. Either this was done and it spread. The latter method is technically more difficult than the former method because it involves vapor phase growth technology. Therefore, the former is generally used. However, with recent technology that uses polycrystalline silicon as wiring, for example, in a silicon gate insulated gate field effect transistor, if the polycrystalline silicon gate is formed in advance and then the source and drain regions are each diffused, the silicon gate can be used as the master. This allows the mask alignment process to be omitted, allowing elements to be formed with high density. However, the lower side of the peripheral edge of the polycrystalline silicon formed during the removal of the oxide film before the source and drain diffusion is subject to so-called underetching, which has become an important problem. To explain this with reference to FIG. 1, as shown in FIG. 1A, a silicon oxide film 2 is provided on a silicon semiconductor substrate 1, a part of which is selectively removed, and a thin silicon An oxide film 3 is formed. Furthermore, a crystalline silicon layer is grown over the entire surface, and a portion of it is selectively left to serve as wiring 4 and electrode 5. Thereafter, as shown in FIG. 1B, oxide film etching is performed to remove thin oxide film 3 using polycrystalline silicon layer 5 as a mask, thereby forming openings for source region 6 and drain region 7. At this time, the bottom of the periphery of the gate electrode 5 is also etched to form an under-etched region 10, and the thick oxide film 2 is also thinly etched to form an under-etched region 10 in a portion under the wiring 4. Next, impurity diffusion is performed to form a source region 6 and a drain region 7, and at the same time, polycrystalline silicon interconnection 4 and electrode 5, which have undergone impurity diffusion, are formed. Thereafter, the impurity glass layer is removed and a vapor phase grown silicon oxide film 8 is grown as shown in FIG. Complete. In this manufacturing method, since the silicon gate 5 is used as a mask for diffusion of the source and drain, there is an advantage that the mutual positions of the gate 5, the source region 6, and the drain region 7 can be exactly as designed. However, since no silicon oxide film is present in the under-etched portion 10, electrical short circuits between the polycrystalline silicon 5 and the source region 6 and drain region 7 are likely to occur.

In view of the above points, the present invention converts a thin silicon oxide film formed on a semiconductor substrate into a glass layer without removing the thin silicon oxide film, and forms a diffusion region in the semiconductor substrate through the glass layer. In this way, when a silicon electrode is formed on the thin silicon oxide film, impurity diffusion can be performed using this as a mask, and since the thin silicon oxide film is not removed, defects due to under-etched parts will occur. This results in a high yield.

Next, with reference to FIG. 2, an example of the method for manufacturing a semiconductor device according to the present invention will be described in the case where it is applied to a device corresponding to the conventional method shown in FIG. The silicon wiring 4 described with respect to FIG. 1A,
The process up to the formation of the electrode 5 is the same as the conventional method. After the silicon wiring and electrodes are formed, in the present invention, impurities are immediately diffused at high temperature without removing the thin silicon oxide film 3 (for example, if it is an N type, phosphorus,
If it is P type, perform boron). In order to reduce the resistance of the source and drain regions, the thickness of the thin silicon oxide film 3 is preferably 2000 Å or less.

By setting the impurity diffusion temperature above 900°C, the thin silicon oxide film 3 is formed into a glass layer (phosphorus silicate glass: PSG in the case of phosphorus, boron silicate glass in the case of boron) within 2 hours, as shown in FIG. 2A. The impurities are converted into silicate glass (BSG) 11 and diffused into the silicon semiconductor substrate 1 through the glass layer 11, forming the source region 6 and drain region 7.
is formed using the silicon gate 5 as a mask.
Note that the glass layer on the source and drain regions is formed by introducing impurities into the silicon oxide film, and the glass layer is formed on the upper surface and side surfaces of the polycrystalline gate electrode 5 due to the influence of oxygen contained in the heat treatment atmosphere. It is formed. Without removing the impurity glass layer 11 formed at this time, a silicon oxide film 8 is then formed on the entire surface by thermal oxidation or vapor phase growth as shown in FIG. 2B, contact holes are opened, and then aluminum wiring 9 to construct a transistor.

As described above, according to the manufacturing method of the present invention, since the thin silicon oxide film 3 is not etched, no under-etched portion 10 occurs, and the gate electrode 5 is surrounded by the dense glass layer 11, and the wiring formed by pinball or the like, the source, No electrical short circuit with the drain region occurs, resulting in a high yield. In the above description, the process of converting the thin silicon oxide film 3 into glass and the process of diffusing impurities through the glass are continuous, but each process may be clearly separated.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of an example of a conventional manufacturing method;
The figure is a sectional view showing an example of the manufacturing method according to the present invention. DESCRIPTION OF SYMBOLS 1... Silicon semiconductor substrate, 3... Thin silicon oxide film, 6, 7... Source and drain regions as diffusion regions, 11... Impurity glass layer.

Claims (1)

[Claims] 1. A step of forming a thin silicon oxide film on a semiconductor substrate, a step of forming a polycrystalline silicon gate electrode on a part of the thin silicon oxide film, and a step of forming a thin silicon oxide film in a heat treatment atmosphere without removing the thin silicon oxide film. By diffusing impurities, a glass layer is formed on the upper surface and side surfaces of the polycrystalline silicon gate electrode during the heat treatment, and the thin silicon oxide film other than directly under the gate electrode is converted into a glass layer. a step of introducing impurities into the semiconductor substrate through a glass layer to form source and drain regions; a step of forming a silicon oxide film thereon without removing the glass layer formed in the step; and a step of forming a silicon oxide film on the glass layer formed in the step; and a step of forming an opening on the drain region and connecting each electrode wiring.