JPS6021539A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize high density loading and high speed operation by providing a process for forming a narrow and deep element isolation region having a low specific dielectricity. CONSTITUTION:A film made of Al or Al2O3 is formed on a semiconducltor substrate 20 and a resist pattern 22 is also formed on the film 21 by the electron beam exposure method. With the resist pattern 22 used as the mask, the film 21 is anisotropically etched by the dry etching method. Next, the resist pattern 22 is removed and with the film 21 used as the mask, the semiconductor substrate 20 is anisotropically etched by the reactive ion etching method. For example, since the etching selection ratio of Al and Si substrate can be set to 70 times or more in the reactive ion etching utilizing CCl2F4 and the anisotropic etching is also possible, width of groove 23 can be set as narrow as several hundreds nm as in the case of the clearance of film 21 and depth of groove 23 can be set as deep as several mum.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device.

Semiconductor devices that enable high-density packaging and high-speed operation.

The present invention relates to a manufacturing method.

[Background of the invention] 1) Semiconductor devices are currently widely used.

A large number of semiconductors that are insulated and separated from each other on a substrate.

It has an element. Insulate and separate these elements.

(hereinafter referred to as the element isolation method).

The oxide film separation method is generally used. 2C:
The oxide film separation method is carried out through the steps shown in FIG. First, the semiconductor substrate 10 is heated in an oxygen atmosphere.

An oxide film 11 is formed by processing, and nitride is deposited on this oxide film 11.

A silicon oxide film 12 is deposited, and a resist pattern 13 is formed on the silicon nitride film 12 (FIG. 1(a)). Next, ``Silicone nitride is formed using this resist pattern 13 as a mask.

membrane] 2. After etching the oxide film 11, the cyst pattern 13 is removed (Fig. tblL). This semiconductor substrate is heat treated in an oxygen atmosphere at a temperature of about 1000° C. for several hours to several tens of hours [Fig. (C)]. At this time, nitriding 1
(1) On the surface of the semiconductor substrate not covered with the silicon film 12, an oxide film 14 is formed by reaction with oxygen.・
However, since the silicon nitride film has the property of effectively preventing oxygen from penetrating, it is possible to prevent the surface of the semiconductor substrate where the silicon nitride film exists from being oxidized 1). As a result, selective oxidation of the semiconductor substrate surface occurs.

I can do it. After that, the silicon nitride film 12 is removed.
tdl), and a semiconductor element is formed in the semiconductor substrate region where the silicon nitride film 12 was present. Each of these elements is insulated and separated by an oxide film 14. After that, wires are connected between the ``%1'' predetermined elements, and the manufacturing of the semiconductor device is completed.

Ru.

The purpose is to improve the separation characteristics of the oxide film separation method described above.
FIG. 1: Between the fat process and the fbl process, there is a resist.

It is also widely possible to introduce a step of ion-implanting impurity having a predetermined polarity using the dopant 13 as a mask.

It has been adopted. However, in these oxide film isolation methods, (1) since an oxide film is used in the element isolation region, the dielectric constant is as large as about 4 (which leads to an increase in wiring capacitance, and 1 (: (2) Oxygen diffuses into the oxide film 11 from the edge of the silicon nitride film 12, and this oxygen reacts with the semiconductor substrate 10, causing the semiconductor substrate 10 to spread laterally as well. As a result, the width of the elementary/pre-isolation region becomes extremely large (which makes it difficult to increase the density of semiconductor devices, and this also makes the wiring 11 long, making it difficult to improve the operating speed of semiconductor devices). Plan.

The problem was that there was no.

As mentioned above, conventional element isolation methods...

There is a problem 20 in that not only it is not possible to miniaturize the elements and increase the density of the semiconductor device, but also it is impossible to improve the operating speed.

[Purpose of the invention]

An object of the present invention is to solve the problems described in "-" in the prior art, and to form a process of forming a narrow and deep device isolation region with a low relative dielectric constant. An object of the present invention is to provide a manufacturing method for manufacturing a semiconductor device that enables mounting and high-speed operation. .

[Summary of the invention]

The present invention is characterized by a step of forming a film having a desired pattern on the surface of a semiconductor substrate, and then anisotropically etching the semiconductor substrate using the film having the desired pattern as a mask. A step of forming a trench having a substantially rectangular cross-section in the semiconductor substrate by removing the film, and a step of forming a first insulating film on the bottom and sidewall surfaces of the trench and the exposed surface of the semiconductor substrate. ) and then anisotropically etched the first insulating film.

near the bottom of the groove and the bottom of the side wall.

A second insulating film is deposited on the semiconductor substrate having the groove, a hollow gap is left in the groove, and the opening is removed ((second insulating film). Embed with a membrane and then bury this embedment.

Etching and removing the second insulating film on the outer semiconductor substrate.

The manufacturing method includes a step of removing. .

[Embodiments of the invention]

Two embodiments of the present invention will be described below with reference to FIG. 2, taking as an example a case where S15 is used as a semiconductor substrate.

Ru. It is made of 2M or At203 on the semiconductor substrate 20.

A film 2I with a thickness of several hundred nm is formed, and electrons are emitted onto the film 21.

Registration using beam exposure method or X-ray exposure method.

A stop pattern 22 is formed (FIG. 2 fal). Using the resist 10 pattern 22 as a mask, the film 21 is anisotropically etched by a dry etching method, for example, a reactive ion etching method using CCT4 [FIG. 2(b)].
. - Since anisotropic elatinization is performed, the gap between the film 21 and the resist pattern 22 can be approximately several hundred nm. Next, the resist pattern 22 is removed and the film 21 is used as a mask.

Then, the semiconductor substrate 20 is subjected to a reactive ion etching method.

Anisotropic etching is performed using a reactive ion beam etching method or an ion beam etching method (FIG. 2 fcl). For example, anti-I8! using CCl2F3!
The monolithic ion etching method is used to process AL and 81 substrates.

Since the etching selectivity can be increased to 70 times or more and etching can be performed anisotropically, the width of the groove 23 can be set to the same width as the gap between the membranes 21.

Similarly, the depth of the groove portion 23 is as small as several hundred nm.

The depth can be several μm. Furthermore, in the ion beam etching method using a mixed gas of Ar and 02, the etching selectivity between At and Si substrates can be increased to 6 or more.

Since anisotropic etching is possible, the width of the groove can be made small and the depth of the groove can be increased, similarly to the above-mentioned paternal ion etching method.Next, after removing the film 21, A first insulating film, for example, an oxide film 24 is formed by leaving a gap in the groove 23 (FIG. 2/fdl), for example, as an embodiment described in claim (2), a semiconductor The substrate 20 is heated to a temperature of 80°C in an oxygen atmosphere containing water vapor.
Heat treated at 0 to 1000°C to reduce the groove width by 1. /3 +=
.

An oxide film of about 100% is formed. Or claim number 3
In the example described in item ), a p-doped oxide film is deposited on the semiconductor substrate 20 by vapor phase growth at normal pressure to a thickness approximately equal to the width of the groove. next.

Reactive ion etching method 2 Reactive ion beam 2 (1
Etching method or ion beam etching.

The oxide film 24 is anisotropically etched by a desired amount using a method.

For example, a mixture of CF4 and H2.

In the reactive ion etching method using
Since anisotropic etching can be performed with an etching selectivity of 4 times or more with respect to the i-substrate, the groove 23 is opened.

With the oxide film on the sidewall of the portion 25 removed, the lower part of the groove portion 23 “
The oxide film on the sidewalls of 26 can be left. This allows °.

The width of the opening 25 of the groove 23 is greater than the width of the lower part 26 of the groove 23.

Can be made wider. Next, the half Il having the groove part 23 is
+A second insulating film, such as an oxide film 27, is deposited on the conductive substrate using a sputtering method, vapor deposition method, or vapor phase growth method [see the second figure]. As a result, a gap 28 is left in the lower part 26 of the groove 23, and the opening 25 of the groove 23 is filled.
nothing. For example, in the normal pressure vapor phase growth method, the thickness of the oxidized film 24 in the groove 23 is several hundreds of nanometers, and the opening of the groove 23 is set to several hundred nm.

When the depth of the portion 25 is approximately the same as the thickness of the oxide film, the opening can be filled by depositing the oxide film 27 to a thickness of about 1 μm, leaving a void. Next, a resist 29 is applied onto the oxide film 27 [FIG. 2(g)]. Resist 29!
If the zero thickness is increased to, for example, about 0.5 μm, the surface of the resist 29 becomes smooth. Next, a resist 29 and an oxide film 27 are sequentially removed from the surface using a dry etching method.

Etch evenly [Fig. 2 (river)]. Then, grooves will appear.

An oxide film 27 is embedded in the opening 25 of the groove 23 .
The oxide film on the semiconductor substrate other than 5 is removed. after that.

A semiconductor device is placed in the area of the semiconductor substrate from which the oxide film has been removed.

form a child; Each of these elements is connected to the opening 2 of the groove 23.
5 in the oxide film 27 and the void 28 in the lower part 26 of the groove 23.

More insulated and separated. In addition, the opening 251 of the groove 23
The 0 oxide film 27 is removed after the element isolation region fabrication process.
This prevents impurities from being ion-implanted into the semiconductor substrate in the groove 23, and the conductive film fills the gap 28 in the groove 23.
Prevent it from being deposited on the surface. Thereafter, predetermined elements and spaces are connected, and the manufacturing of the semiconductor device is completed. 1) In the embodiment of the present invention shown in FIG. 2, FIG. 2(a).

As shown in Figure 3, electron beam exposure method or X-ray exposure method is used. However, as a simple method to further reduce the width of the groove, instead of +al to fbl in Figure 2,
It is also effective to introduce the steps shown in the figure. 2.) Thickness of M or AL203 on semiconductor substrate 30.

A film 31 with a thickness of several hundred nm is formed, and a resist film is applied on the film 31.

A tongue 32 is formed (FIG. 3(a)). resist pattern.

Membrane using phosphoric acid-acetic acid mixture using No. 32 as a mask.

31 is selectively etched with a side etching amount of a desired amount, for example, several hundred nm [FIG. 3(b)]. Thereafter, with the resist pattern 32 mounted, a film 33 made of M or AL 203° is formed several tens of nanometers thinner than the thickness of the film 31 using a spaget method or a vapor deposition method.

[Figure 3 (C)]. Film 33 on resist pattern 32
is removed together with the resist by the lf1 lift-off process [Figure 3(d)]. In the process shown in FIG. 3, the gap 34 between the film 31 and the film 33, which serves as an erating mask, is determined by the amount of side etching of the film 31 in the process shown in FIG. The width 15 of the area can be reduced.

The effects of adopting the above-mentioned embodiments of the present invention will be described. (1) Since elements are separated and insulated using air gaps, the relative dielectric constant can be reduced to about 14 times, making it possible to improve isolation characteristics and increase the speed of semiconductor devices. (2) The width of the element isolation region is as shown in FIG.

tdl or the steps shown in Figure 3 fat ~ (di and Figure 2 (b).

Determined by the width of the groove formed in the process indicated by ~fdl.

Therefore, element isolation regions with a width of about several hundred nm can be formed, making it possible to increase the density of semiconductor devices. '(3) The element isolation region should be formed without completely filling the trench (,
It also involves an insulating film formation process using oxidation.

Since the stress applied to the semiconductor substrate can be reduced, the introduction of crystal defects into the semiconductor substrate can be prevented, and the separation characteristics can be improved. Regarding point 11), the technique disclosed in Japanese Patent Application No. 179098/1987 includes a step of covering the vicinity of the opening of the trench with an oxidized insulating film.

It is clearly different. That is, in the above-mentioned disclosed technology.

This is because an oxide insulating film with a large volume change is used.

Although the stress applied to the groove and its surroundings increases, 1) this problem can be solved by the method of the embodiment of the present invention.

Figure 4 shows the present invention in the isolation of a MOS transistor.

This is an example of application. Source 41. drain 4
2. Gate electrode 43. Gate oxide film 44 and M? (1
MOS including wiring 45) transistor is an element isolation region.

46. Since the dielectric constant of the element isolation region is small and element isolation can be performed with a small width, it is possible to increase the density of semiconductor devices made of MOS transistors.

and its characteristics can be improved.

FIG. 5 shows an embodiment in which the present invention is applied to the production of bipolar transistors. Emitter 51. “Base 5
2 and a collector 53.

The transistors are separated by element isolation regions 54. Furthermore, the present invention can be applied not only to isolation 55 between transistors but also between base 52 and collector 53. In this way, not only the spacing between bipolar transistors but also the size of the transistors themselves can be reduced.

FIG. 6 shows an embodiment in which two of the present inventions are applied to a complementary MO8 semiconductor device. The complementary MO8 semiconductor device is p
type transistor and n-type transistor.

These are formed on an n-type polar impurity region 61 and a p-polarity impurity region 62 provided on a semiconductor substrate 60. These impurity regions 211 are separated by element isolation regions 63 of the present invention. General.

In ordinary complementary MO8 semiconductor devices, p-electrode impurity.

The doped region and the n-type polar impurity region are in direct contact with each other.

Ru. This is why the complementary type is called latch-up.

5 transistors each from the boundaries of these impurity regions in order to alleviate problems specific to MO8 semiconductor devices.

must be kept away. However, the present invention.

By using this isolation method, transistors can be formed in contact with element isolation regions, making it possible to significantly increase the density of semiconductor devices and improve their characteristics. 10. Semiconductor devices are not only fabricated on bulk semiconductor devices or crystal substrates as described above, but also using semiconductor single crystal films formed on insulating substrates.

FIG. 7 shows 9 application examples of the present invention in which a single crystallized semiconductor film 71 is used on an insulating substrate 70, for example, sapphire. The transistors formed on this semiconductor film 71 are formed adjacent to each other with an element isolation region 72 in between. For this reason, it becomes easy to increase the density of semiconductor devices.

0 〔Effect of the invention〕 As explained above, according to the present invention, the size is small.

It has a relative dielectric constant. A fine and deep element isolation region can be easily formed, and a high-density and high-speed semiconductor device can be formed. 5

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining a conventional element isolation method, FIG. 2 is a process diagram of an embodiment of the present invention, and FIG. 3 is a diagram of the present invention. Partial process diagrams of other embodiments, FIGS. 4, 5, and 5. 6 and 7 are cross-sectional views showing ten examples of semiconductor devices manufactured by applying the present invention, respectively. Explanation of symbols 10, 20.60...Semiconductor substrate 11, 14.44...Oxide film 12...Silicon nitride film ・13, 22.32...Resist button 15
21, 31.33...Membrane 23...Groove 24...
First insulating film 25... Opening 27... Second insulating film 28... Gap 29... Resist 41... Source ・42... Drain 43... Gate electrode
2045...M wiring 46.54.63.72...Element isolation region 51...
Emitter 52... Base 53... Collector 61
... N-type polar impurity region 62 ... P-type region impurity region 70 ... Insulating substrate 71 ... Semiconductor film patent applicant
Nippon Telegraph and Telephone Public Corporation 10 Representative Patent Attorney Junnosuke Nakatoshi ・0. 15゜ years old 1 figure 2 figure 3 figure 4 spears 1'5V JP6 figure IP7 figure

Claims (3)

[Claims] (1) A step of forming a film having a desired pattern on the surface of a semiconductor substrate, anisotropically etching the semiconductor substrate using the film having the desired pattern as a mask, and then removing the film to form a cross-sectional shape. Kaha. forming a substantially rectangular groove in the semiconductor substrate; The bottom and sidewall surfaces of this groove and the exposed semiconductor substrate 1 ()
forming a first insulating film on the surface, and anisotropically etching the first insulating film to form the bottom of the trench. Only the face part and the part of the side wall part near the bottom. A process of leaving and removing the groove, and a half having this groove. A second insulating film is deposited on the conductor substrate, and a hollow gap is left in the groove portion, and the opening is filled with the second insulating film. Embedded area and then semiconductor substrate other than this embedded area. and a step of etching away the upper second insulating film. A method of manufacturing a semiconductor device, comprising: . (2) The step of forming the first insulating film on the bottom and sidewall surfaces of the trench (I) and the exposed surface of the semiconductor substrate is a step of heat-treating the substrate in an oxygen atmosphere to form an oxide film. Claim 1: A method for manufacturing a semiconductor device according to claim 1. (3) The step of forming the first insulating film on the bottom surface of the trench, the sidewall surface skin 1, and the exposed surface of the semiconductor substrate is performed by vapor deposition. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step is to deposit an insulating film by a suitable method.