WO2009157333A1 - Shallow trench isolation structure and method for forming the shallow trench isolation structure - Google Patents

Shallow trench isolation structure and method for forming the shallow trench isolation structure Download PDF

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WO2009157333A1
WO2009157333A1 PCT/JP2009/060849 JP2009060849W WO2009157333A1 WO 2009157333 A1 WO2009157333 A1 WO 2009157333A1 JP 2009060849 W JP2009060849 W JP 2009060849W WO 2009157333 A1 WO2009157333 A1 WO 2009157333A1
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Prior art keywords
groove
isolation structure
trench isolation
shallow trench
silicon dioxide
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PCT/JP2009/060849
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French (fr)
Japanese (ja)
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達郎 長原
昌伸 林
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Ａｚエレクトロニックマテリアルズ株式会社
ＡｚエレクトロニックマテリアルズＵｓａコーポレーション
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Publication of WO2009157333A1 publication Critical patent/WO2009157333A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Definitions

  • the present invention relates to a method for producing a silicon dioxide film in an electronic device. More particularly, the present invention relates to a method of forming a silicon dioxide film for use in forming an insulating film used in an electronic device, for example, forming a shallow trench isolation structure in the manufacture of an electronic device such as a semiconductor element. It is.
  • an isolation region In general, in an electronic device such as a semiconductor device, semiconductor elements such as transistors, resistors, and others are arranged on a substrate, but they need to be electrically insulated. Therefore, a region for separating the elements is required between these elements, which is called an isolation region. Conventionally, this isolation region is generally performed by selectively forming an insulating film on the surface of a semiconductor substrate.
  • a trench isolation structure is a structure in which a fine groove is formed on the surface of a semiconductor substrate and an insulator is filled in the groove to electrically separate elements formed on both sides of the groove.
  • Such a structure for element isolation is an element isolation structure that is effective for achieving the high degree of integration required in recent years because the isolation region can be made narrower than in the conventional method.
  • a method of applying a polysilazane composition and converting it to silicon dioxide has been studied (for example, Patent Documents 1 and 2).
  • the polysilazane composition is applied to the surface of the substrate on which the groove structure is formed, and the groove is filled with the polysilazane composition.
  • surplus silicon dioxide formed on the surface is removed by a chemical mechanical polishing method (hereinafter referred to as CMP).
  • the excess silicon dioxide is small in order to shorten the CMP process.
  • the polysilazane composition it is conceivable to apply the polysilazane composition at a relatively low concentration.
  • the solid content of the polysilazane composition filled in the groove is also relatively reduced.
  • the silicon dioxide formed in the groove after firing is insufficient, and the groove cannot be filled sufficiently, or a strong tensile stress is generated in the groove, adversely affecting the characteristics of the final electronic device.
  • the silicon dioxide formed in the groove does not sufficiently adhere to the inner surface of the groove, so that it falls off from the groove, and no silicon dioxide remains in the groove. As a result, a trench isolation structure having insufficient insulation characteristics is obtained.
  • Patent Document 3 a method of applying the polysilazane composition multiple times has also been proposed.
  • Patent Document 3 a method of applying the polysilazane composition multiple times has also been proposed.
  • Patent Document 3 such a method is not preferable from the viewpoint of process cost.
  • the concentration of the polysilazane composition is made relatively high, contrary to the above means.
  • surplus silicon dioxide formed on the substrate surface increases, so that the amount of silicon dioxide to be polished in the CMP process also increases and process cost increases.
  • the coating film of the polysilazane composition formed by coating becomes thick, moisture and oxygen taken from the atmosphere are not sufficiently supplied to the inside of the groove, and the conversion from polysilazane to silicon dioxide proceeds sufficiently inside the groove. The problem of not occurring also occurs. Further, when a thick film of silicon dioxide is formed, cracks may occur in the film due to residual stress in the film.
  • the present invention provides a trench isolation structure in which a polysilazane composition is applied relatively thinly and has sufficient insulating properties, and a method for manufacturing the same.
  • a shallow trench isolation structure provided by the present invention includes a substrate having a groove structure on a surface thereof, and a silicon dioxide film that embeds the groove, and the silicon dioxide film is on the surface side of the substrate. It is localized and has a hole at the bottom of the groove.
  • the manufacturing method of the shallow trench isolation structure includes: (A) A coating process in which a polysilazane composition is coated on a substrate surface having a groove structure to form a coating film, (B) An ultraviolet irradiation step of irradiating the surface of the coating film with ultraviolet rays to cure a part of polysilazane in the vicinity of the surface of the coating film to form pores at the bottom of the groove portion, and (C) the coating A baking step in which the entire coating film is cured to form a silicon dioxide film by baking the film, It is characterized by comprising.
  • a shallow trench isolation structure that is different from the conventional shallow trench isolation structure and has excellent insulation characteristics while having holes. Further, according to the method of the present invention, a shallow trench isolation structure can be formed easily and at low cost.
  • a trench isolation structure according to the present invention comprises a substrate having a groove structure on the surface and a silicon dioxide film in which the groove is embedded.
  • the silicon dioxide film in which the groove is embedded does not completely fill the groove, is localized on the surface side of the substrate, and there is a hole in the bottom of the groove. This is a characteristic of the shallow trench isolation structure. This structure is shown in FIG.
  • a silicon dioxide film (insulating film) 2 is formed in the vicinity of the surface of the groove portion of the substrate 1, and a hole 3 is formed at the bottom of the groove portion.
  • the holes 3 are not a collection of relatively small holes but are substantially one continuous. That is, the hole in the present invention has a belt-like or string-like shape along the shape of the groove.
  • the silicon dioxide film 2 in which the groove is embedded is present inside the groove, but is localized on the surface side of the substrate. In other words, it can be said that the silicon dioxide film 2 seals the holes 3 in the groove.
  • the interface between the hole 3 and the inner surface of the groove is in direct contact, and there is no silicon dioxide film on the inner surface of the groove.
  • such an isolation structure preferably has a specific size.
  • the groove width of the trench isolation groove is narrower and the aspect ratio is smaller. Excellent properties are exhibited at higher temperatures. That is, the groove width a is preferably 5 to 50 nm, and more preferably 5 to 40 nm.
  • the ratio of the groove depth b to the groove width a, that is, the aspect ratio b / a is preferably 10 to 100, and more preferably 10 to 50.
  • c is preferably 5 to 100 nm, and more preferably 5 to 50 nm.
  • the ratio of the cross-sectional area of the hole to the cross-sectional area of the groove structure is preferably 5 to 20%, and preferably 8 to 15%.
  • a dense silicon dioxide film can be obtained when the length of the holes in the groove depth direction or the ratio of the cross-sectional area of the holes is above a certain level, and the insulation characteristics of the isolation structure are sufficiently exhibited.
  • the pores become large, the silicon dioxide film is compressed and becomes dense, the tensile stress is reduced, and the physical strength is sufficient.
  • c / b is preferably 0.05 to 0.2, preferably 0.08 to 0. .15 is preferred.
  • the trench isolation structure according to the present invention exerts a strong effect when the groove width and aspect ratio and the hole size are as described herein, but these sizes are particularly limited.
  • the silicon dioxide film is localized on the surface side of the substrate, and has a structure having holes at the bottom of the groove, the present The effects of the invention can be obtained.
  • the shallow trench isolation structure as described above can be formed by any method.
  • One such method is (A) A coating process in which a polysilazane composition is coated on a substrate surface having a groove structure to form a coating film, (B) An ultraviolet irradiation step of irradiating the surface of the coating film with ultraviolet rays to cure a part of polysilazane in the vicinity of the surface of the coating film to form pores at the bottom of the groove portion, and (C) the coating A baking step in which the entire coating film is cured to form a silicon dioxide film by baking the film, There is a method comprising
  • a feature of the method for forming a shallow trench isolation structure according to the present invention is that after the polysilazane composition is applied, the surface of the coating film is first irradiated with ultraviolet rays to temporarily cure the vicinity of the surface, and then baked and applied.
  • the purpose is to convert the entire film into a silicon dioxide film.
  • polysilazane is oxidized and polymerized, thereby causing volume shrinkage.
  • a pulling force acts on the polysilazane composition in the groove or the silicon dioxide film formed by converting it.
  • the density of the silicon dioxide film is increased and becomes denser, and vacancies are generated at the bottom of the trench.
  • the silicon dioxide film tends to shrink further, but since it does not contact the bottom of the groove, no pulling force acts on the bottom surface, and the silicon dioxide film achieves a higher density. it can.
  • the trench was filled with a silicon dioxide film having a relatively low density, whereas the shallow trench isolator formed by the method of the present invention was used.
  • a silicon dioxide film (insulating film) having a high density is formed only near the surface.
  • a groove structure for forming a shallow trench isolation structure that is, a substrate having irregularities is prepared.
  • the material of the substrate is not particularly limited, and any conventionally known substrate such as a silicon substrate can be used. Further, any method can be used to form the groove on the substrate surface, which is also described in, for example, Patent Document 1 or 2. A specific method is as follows.
  • a silicon dioxide film is formed on the surface of a silicon substrate by, for example, a thermal oxidation method.
  • the thickness of the silicon dioxide film formed here is generally 5 to 30 nm.
  • a silicon nitride film is formed on the formed silicon dioxide film by, for example, a low pressure CVD method.
  • This silicon nitride film can function as a mask in a later etching process or a stop layer in a polishing process described later.
  • the silicon nitride film is generally formed with a thickness of 100 to 400 nm when formed.
  • a photoresist is applied on the silicon dioxide film or silicon nitride film thus formed.
  • the photoresist film is dried or cured as necessary, and then exposed and developed with a desired pattern to form a pattern.
  • the exposure method can be performed by any method such as mask exposure or scanning exposure. Also, any photoresist can be selected and used from the viewpoint of resolution and the like.
  • the silicon nitride film and the underlying silicon dioxide film are sequentially etched. By this operation, a desired pattern is formed on the silicon nitride film and the silicon dioxide film.
  • the silicon substrate is dry-etched to form trench isolation grooves.
  • the width of the trench isolation groove to be formed is determined by the pattern for exposing the photoresist film.
  • the width of the trench isolation groove in the semiconductor element is appropriately set depending on the target semiconductor element.
  • the above-described shallow trench It is preferably selected from the range described in the section of the isolation structure.
  • the trench isolation structure forming method according to the present invention does not fill the trench uniformly. For this reason, the groove structure formed on the substrate surface may be narrower and deeper.
  • a polysilazane composition as a material for the silicon dioxide film is applied on the silicon substrate thus prepared to form a coating film.
  • a conventionally known arbitrary polysilazane compound dissolved in a solvent can be used.
  • the polysilazane compound used for this invention is not specifically limited, As long as the effect of this invention is not impaired, it can select arbitrarily. These may be either inorganic compounds or organic compounds. Among these polysilazanes, preferred are those composed of combinations of units represented by the following general formulas (Ia) to (Ic): (Where m1 to m3 are numbers representing the degree of polymerization) Of these, those having a weight average molecular weight in terms of styrene of 700 to 30,000 are particularly preferred.
  • Examples of other polysilazanes include, for example, a general formula: (Wherein R 1 , R 2 and R 3 are each independently a hydrogen atom, an alkyl group, an alkenyl group, a cycloalkyl group, an aryl group, or a group directly connected to silicon such as a fluoroalkyl group other than these groups. A group which is carbon, an alkylsilyl group, an alkylamino group or an alkoxy group, provided that at least one of R 1 , R 2 and R 3 is a hydrogen atom and n is a number representing the degree of polymerization). Examples thereof include polysilazane having a skeleton composed of the above structural units and a number average molecular weight of about 100 to 50,000 or a modified product thereof. These polysilazane compounds can be used in combination of two or more.
  • the polysilazane composition used in the present invention comprises a solvent capable of dissolving the polysilazane compound.
  • the solvent used here is different from the solvent used for the dipping solution.
  • Such a solvent is not particularly limited as long as it can dissolve each of the above-mentioned components.
  • Specific examples of preferable solvents include the following: (A) Aromatic compounds such as benzene, toluene, xylene, ethylbenzene, diethylbenzene, trimethylbenzene, triethylbenzene, etc.
  • solvents can be used in combination of two or more as appropriate in order to adjust the evaporation rate of the solvent, to reduce the harmfulness to the human body, or to adjust the solubility of each component.
  • the polysilazane composition used in the present invention may contain other additive components as necessary.
  • examples of such components include a crosslinking accelerator that accelerates the crosslinking reaction of polysilazane, a catalyst for the reaction to be converted into silicon dioxide, a viscosity modifier for adjusting the viscosity of the composition, and the like.
  • a phosphorus compound such as tris (trimethylsilyl) phosphate may be contained for the purpose of obtaining a sodium gettering effect when used in a semiconductor device.
  • the content of each of the above components varies depending on the application conditions, firing conditions, and the like.
  • the content of the polysilazane compound is preferably 1 to 30% by weight, more preferably 2 to 20% by weight, based on the total weight of the polysilazane composition.
  • the concentration of polysilazane contained in the polysilazane composition is not limited to this, and any concentration of polysilazane composition can be used as long as the trench isolation structure specified in the present invention can be formed. .
  • the content of various additives other than polysilazane varies depending on the type of the additive, etc., but the amount added to the polysilazane compound is preferably 0.001 to 40% by weight, and 0.005 to 30% by weight. More preferably, it is 0.01 to 20% by weight.
  • the polysilazane composition can be applied on the substrate by any method. Specific examples include spin coating, curtain coating, dip coating, and others. Of these, spin coating is particularly preferable from the viewpoint of uniformity of the coating surface.
  • the thickness of the coating film to be applied that is, the thickness of the coating film in the portion having no groove on the substrate surface is preferably 20 to 150 nm, and more preferably 30 to 100 nm. If the thickness of this coating film is excessively high, the ultraviolet rays described below may not reach the vicinity of the surface in the groove, while if the film thickness is too thin, the polysilazane composition filled in the groove is insufficient, Care must be taken because the sidewall of the trench may collapse or a silicon dioxide film having a sufficient thickness may not be formed.
  • the surface of the coating film of the polysilazane composition is irradiated with ultraviolet rays.
  • the purpose of this ultraviolet ray is to cause an oxidation or polymerization reaction in the vicinity of the surface of the polysilazane coating film formed in the coating process. Therefore, it is necessary for the ultraviolet rays to reach the inside of the groove.
  • the wavelength of the ultraviolet rays used depends on the type of polysilazane composition, but is preferably 150 to 200 nm, and more preferably 170 to 190 nm.
  • the light energy to be irradiated is preferably 0.05 to 100 mJ / cm 2 , more preferably 0.1 to 50 J / cm 2 .
  • Irradiation can generally be performed in air.
  • oxygen absorbs light having a wavelength of 200 nm or less, for example, depending on the oxygen concentration in the atmosphere and the distance between the light source and the substrate, the light is absorbed by the oxygen in the atmosphere before reaching the substrate surface. In other words, sufficient light may not reach the inside of the groove.
  • Patent Documents 4 and 5 disclose a method for forming an SOG film including irradiation with ultraviolet rays. However, these methods are to fill the trench uniformly with an insulating film, and to achieve a structure different from the present invention.
  • (C) Firing step Following the ultraviolet irradiation step, the polysilazane coating film is baked to convert the entire coating film into a silicon dioxide film.
  • the prototype of the silicon dioxide film formed by the ultraviolet irradiation process is completely converted into a silicon dioxide film, that is, an insulating film.
  • the baking is performed using a curing furnace or a hot plate, and contains water vapor. It is preferably performed in a gas or oxygen atmosphere. Water vapor is important to fully convert the silicon-containing compound or silicon-containing polymer, as well as the polysilazane compound, if present, to silicon dioxide, preferably 1% or more, more preferably 10% or more, most preferably 20% or more.
  • the conversion of the silazane compound to the silicon dioxide film is likely to proceed, the occurrence of defects such as voids is reduced, and the characteristics of the silicon dioxide film are improved.
  • an inert gas is used as the atmospheric gas, nitrogen, argon, helium, or the like is used.
  • the temperature condition for curing varies depending on the type of polysilazane composition to be used and the combination of processes. However, higher temperatures tend to increase the rate at which silicon-containing compounds, silicon-containing polymers, and polysilazane compounds are converted to silicon dioxide films, and lower temperatures are due to oxidation of the silicon substrate or changes in crystal structure. There is a tendency for adverse effects on device characteristics to be reduced. From such a viewpoint, in the method according to the present invention, heating is usually performed at 1000 ° C. or lower, preferably 400 to 900 ° C.
  • the temperature raising time to the target temperature is generally 1 to 100 ° C./min
  • the curing time after reaching the target temperature is generally 1 minute to 10 hours, preferably 15 minutes to 3 hours. If necessary, the curing temperature or the composition of the curing atmosphere can be changed stepwise.
  • the polysilazane compound present in the coating film can be converted into silicon dioxide, and the final shallow trench isolation structure can be obtained.
  • the thus obtained shallow trench isolation structure according to the present invention has a high physical strength with reduced tensile stress in the vicinity of the groove. This is because vacancies are formed at the bottom of the groove by ultraviolet irradiation performed prior to firing, and the density of the polysilazane composition present in the portion immediately above the vacancies or the precursor of the silicon dioxide film derived therefrom is high. In addition, this is because the density of the silicon dioxide film formed by firing increases.
  • the method for forming a shallow trench isolation structure according to the present invention requires the steps (A) to (C) described above, but the following auxiliary steps may be combined as necessary.
  • (A) Solvent removal step After the coating step, the substrate coated with the polysilazane composition can be pre-baked prior to the firing step. This step aims to remove at least a part of the solvent contained in the coating film.
  • the temperature in the solvent removal step is usually in the range of 50 to 250 ° C., preferably 80 to 200 ° C.
  • the time required for the solvent removal step is generally 0.5 to 10 minutes, preferably 1 to 5 minutes.
  • polishing Step After curing, it is preferable to remove unnecessary portions of the cured silicon dioxide film.
  • the silicon dioxide film formed on the inner side of the groove on the substrate is left by the polishing process, and the silicon dioxide film formed on the flat portion of the substrate surface is removed by polishing.
  • This process is a polishing process.
  • This polishing step can be performed immediately after pre-baking, in addition to the curing treatment, or in the case of combining the pre-baking step.
  • Polishing is generally performed by CMP.
  • This polishing by CMP can be performed with a general abrasive and polishing apparatus.
  • the polishing agent an aqueous solution in which an abrasive such as silica, alumina, or ceria and other additives are dispersed as required can be used.
  • a typical CMP apparatus can be used.
  • (C) Etching Step the silicon dioxide film derived from the polysilazane composition formed on the flat portion of the substrate surface is almost removed, but the silicon dioxide film remaining on the flat portion of the substrate surface is removed. In order to remove this, it is preferable to further perform an etching process.
  • An etching solution is generally used for the etching treatment, and the etching solution is not particularly limited as long as it can remove the silicon dioxide film.
  • a hydrofluoric acid aqueous solution containing ammonium fluoride is used. The concentration of ammonium fluoride in this aqueous solution is preferably 5% or more, and more preferably 30% or more.
  • Example 1 First, a silicon substrate having a groove structure on the surface was prepared.
  • the width of the groove was 40 nm and the depth was 600 nm (aspect ratio 15).
  • a solution of polysilazane in dibutyl ether (solid content concentration based on the total weight of the composition is 12% by weight) is spin-coated on the above substrate at 1000 rpm and a part of the solvent at 150 ° C. for 1 minute. Was removed. At this time, the film thickness of the polysilazane composition coating film in the portion other than the groove structure on the substrate surface was 80 nm. Further, this substrate was cut perpendicularly to the surface, and a cross section of the groove structure was observed using a scanning electron microscope (S-4700 type (trade name) manufactured by Hitachi, Ltd.). I was not able to admit.
  • S-4700 type (trade name) manufactured by Hitachi, Ltd.
  • the surface of the substrate was irradiated with ultraviolet rays having a wavelength of 172 nm at 10 mW / cm 2 for 3 minutes using an excimer UV irradiation device (manufactured by USHIO INC.).
  • H 2 O / (O 2 + H 2 O) 80 mol%
  • the wet etching rate of the silicon dioxide film formed immediately above the pores was measured using a 0.5 wt% hydrofluoric acid aqueous solution containing 20 wt% ammonium fluoride as a buffering agent.
  • the wet etching rate of the silicon dioxide film according to Example 1 was 1.80 based on the thermal oxide film.
  • Comparative Example 1 A polysilazane coating film was formed on a substrate having a groove structure in the same manner as in Example 1 except that ultraviolet rays were not irradiated. When the cross section of this coating film was observed, the inside of the groove was almost uniformly filled and no voids were observed.
  • Example 2 Further, firing and annealing were performed in the same manner as in Example 1, and the tensile stress of the obtained sample was measured and found to be 120 MPa. It was very high compared to Example 1, and it was found that defects such as cracks and dropouts were likely to occur inside the groove.
  • the wet etching rate was measured in the same manner as in Example 1.
  • the wet etching rate of the silicon dioxide film according to Comparative Example 1 was 4.10 based on the thermal oxide film.
  • the wet etching rate has a positive correlation with the film stress (tensile stress), that is, the silicon dioxide film according to Example 1 has a low wet etching rate and is excellent.
  • the wet etching rate exceeds 3, the use is limited from the viewpoint of practicality.

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Abstract

Disclosed is a shallow trench isolation structure having excellent insulating properties.  Also disclosed is a simple and low-cost method for formation of the shallow trench isolation structure.  The shallow trench isolation structure has a surface groove structure embedded with a silicon dioxide film.  The silicon dioxide film is localized on the surface side of a substrate, and vacancies are present on the bottom part of the grooves.  The isolation structure can be formed by coating a polysilazane composition onto a surface of a substrate, exposing the surface of the coating film to ultraviolet light to cure a part of the polysilazane present near the surface of the coating film, and, furthermore, firing the coating film.

Description

シャロー・トレンチ・アイソレーション構造とその形成方法Shallow trench isolation structure and formation method thereof
　本発明は、電子デバイスにおける二酸化ケイ素膜の製造法に関するものである。さらに詳しくは、本発明は半導体素子などの電子デバイスの製造において、電子デバイスに用いられる絶縁膜の形成、例えばシャロー・トレンチ・アイソレーション構造の形成に用いるための二酸化ケイ素膜を形成させる方法に関するものである。 The present invention relates to a method for producing a silicon dioxide film in an electronic device. More particularly, the present invention relates to a method of forming a silicon dioxide film for use in forming an insulating film used in an electronic device, for example, forming a shallow trench isolation structure in the manufacture of an electronic device such as a semiconductor element. It is.
　一般に、半導体装置の様な電子デバイスにおいては、半導体素子、例えばトランジスタ、抵抗、およびその他、が基板上に配置されているが、これらは電気的に絶縁されている必要がある。したがって、これら素子の間には、素子を分離するための領域が必要であり、これをアイソレーション領域と呼ぶ。従来は、このアイソレーション領域を半導体基板の表面に選択的に絶縁膜を形成させることにより行うことが一般的であった。 In general, in an electronic device such as a semiconductor device, semiconductor elements such as transistors, resistors, and others are arranged on a substrate, but they need to be electrically insulated. Therefore, a region for separating the elements is required between these elements, which is called an isolation region. Conventionally, this isolation region is generally performed by selectively forming an insulating film on the surface of a semiconductor substrate.
　一方、電子デバイスの分野においては、近年、高密度化、および高集積化が進んでいる。このような高密度および高集積度化が進むと、必要な集積度に見合った、微細なアイソレーション構造を形成させることが困難となり、そのようなニーズに合致した新たなアイソレーション構造が要求される。そのようなものとして、トレンチ・アイソレーション構造が挙げられる。この構造は、半導体基板の表面に微細な溝を形成させ、その溝の内部に絶縁物を充填して、溝の両側に形成される素子の間を電気的に分離する構造である。このような素子分離のための構造は、従来の方法に比べてアイソレーション領域を狭くできるため、昨今要求される高集積度を達成するために有効な素子分離構造である。 On the other hand, in the field of electronic devices, in recent years, higher density and higher integration are progressing. As such high density and high integration progress, it becomes difficult to form a fine isolation structure that meets the required integration, and a new isolation structure that meets such needs is required. The An example of such a structure is a trench isolation structure. This structure is a structure in which a fine groove is formed on the surface of a semiconductor substrate and an insulator is filled in the groove to electrically separate elements formed on both sides of the groove. Such a structure for element isolation is an element isolation structure that is effective for achieving the high degree of integration required in recent years because the isolation region can be made narrower than in the conventional method.
　このようなトレンチ・アイソレーション構造を形成させるための方法のひとつとして、ポリシラザン組成物を塗布し、それを二酸化ケイ素に転化させる方法が検討されている（例えば、特許文献１および２）。このような方法では、ポリシラザン組成物を溝構造が形成された基板表面に塗布して溝内にポリシラザン組成物を充填し、次いでポリシラザン組成物を焼成などにより硬化させて二酸化ケイ素に転化させ、基板表面に形成された余剰の二酸化ケイ素を化学的機械的研磨方法（Chemical Mechanical Polishing：以下、ＣＭＰといいます）によって除去するのが一般的である。 As one method for forming such a trench isolation structure, a method of applying a polysilazane composition and converting it to silicon dioxide has been studied (for example, Patent Documents 1 and 2). In such a method, the polysilazane composition is applied to the surface of the substrate on which the groove structure is formed, and the groove is filled with the polysilazane composition. In general, surplus silicon dioxide formed on the surface is removed by a chemical mechanical polishing method (hereinafter referred to as CMP).
　このような方法でトレンチ・アイソレーション構造を形成させる場合、製造プロセスの効率を考えると、ＣＭＰ工程を短縮するためには余剰の二酸化ケイ素が少ないほうが好ましい。このために、ポリシラザン組成物を相対的に低濃度として塗布することが考えられる。しかし、ポリシラザン組成物を低濃度にすると、溝内に充填されるポリシラザン組成物の固形分も相対的に少なくなる。その結果、焼成後に溝内に形成される二酸化ケイ素が不足し、溝内を十分に充填できなかったり、溝内に強い引張応力が発生して、最終的な電子デバイスの特性に悪影響を与えることがある。最悪の場合には、溝内に形成された二酸化ケイ素が溝内面と十分に密着しないために溝内から脱落し、溝内には二酸化ケイ素が残存しないことさえ起こりえる。この結果、絶縁特性が不十分なトレンチ・アイソレーション構造となってしまう。 When the trench isolation structure is formed by such a method, in view of the efficiency of the manufacturing process, it is preferable that the excess silicon dioxide is small in order to shorten the CMP process. For this purpose, it is conceivable to apply the polysilazane composition at a relatively low concentration. However, when the polysilazane composition is at a low concentration, the solid content of the polysilazane composition filled in the groove is also relatively reduced. As a result, the silicon dioxide formed in the groove after firing is insufficient, and the groove cannot be filled sufficiently, or a strong tensile stress is generated in the groove, adversely affecting the characteristics of the final electronic device. There is. In the worst case, the silicon dioxide formed in the groove does not sufficiently adhere to the inner surface of the groove, so that it falls off from the groove, and no silicon dioxide remains in the groove. As a result, a trench isolation structure having insufficient insulation characteristics is obtained.
　このようなポリシラザン組成物濃度を低くすることによる問題点を解決するために、ポリシラザン組成物を複数回塗布する方法も提案されている（特許文献３）。しかしながら、このような方法はプロセスコストの観点からは好ましくない。 In order to solve the problems caused by lowering the polysilazane composition concentration, a method of applying the polysilazane composition multiple times has also been proposed (Patent Document 3). However, such a method is not preferable from the viewpoint of process cost.
　このような問題点を回避するためには、前記の手段とは反対に、ポリシラザン組成物の濃度を相対的に高くすることが考えられる。しかし、この場合には基板表面に形成される余剰の二酸化ケイ素が増加するため、ＣＭＰ工程において研磨すべき二酸化ケイ素量も増加してプロセスコストが増大する。さらには、塗布により形成されるポリシラザン組成物の塗膜が厚くなるので、雰囲気から取り込まれる水分および酸素が溝内部まで十分に供給されず、溝内部でポリシラザンから二酸化ケイ素への転化が十分に進行しないという問題も発生する。また、二酸化ケイ素の厚い膜が形成された場合には、膜中残留応力により膜にクラックが発生することもある。 In order to avoid such problems, it is conceivable that the concentration of the polysilazane composition is made relatively high, contrary to the above means. However, in this case, surplus silicon dioxide formed on the substrate surface increases, so that the amount of silicon dioxide to be polished in the CMP process also increases and process cost increases. Furthermore, since the coating film of the polysilazane composition formed by coating becomes thick, moisture and oxygen taken from the atmosphere are not sufficiently supplied to the inside of the groove, and the conversion from polysilazane to silicon dioxide proceeds sufficiently inside the groove. The problem of not occurring also occurs. Further, when a thick film of silicon dioxide is formed, cracks may occur in the film due to residual stress in the film.
　以上の通り、ポリシラザン組成物を塗布し、二酸化ケイ素に転化させる方法を用いた場合には、ポリシラザン組成物の濃度によって異なった問題が発生する傾向にあり、その最適な条件を調整するために多大な労力が必要であった。 As described above, when a method of applying a polysilazane composition and converting it to silicon dioxide is used, there is a tendency that different problems occur depending on the concentration of the polysilazane composition. It took a lot of effort.
特許第３１７８４１２号公報（段落０００５～００１６）Japanese Patent No. 3178812 (paragraphs 0005 to 0016) 特開２００１－３０８０９０号公報JP 2001-308090 A 特開２００７－０３６２６７号公報JP 2007-036267 A 特開平０８－１２５０２１号公報JP 08-1225021 A 特開平０１－２４８５２８号公報Japanese Patent Laid-Open No. 01-248528
　本発明は上記のような問題点に鑑みて、ポリシラザン組成物を相対的に薄く塗布し、かつ十分な絶縁特性を有するトレンチ・アイソレーション構造、およびその製造法を提供するものである。 In view of the above problems, the present invention provides a trench isolation structure in which a polysilazane composition is applied relatively thinly and has sufficient insulating properties, and a method for manufacturing the same.
　本発明により提供されるシャロー・トレンチ・アイソレーション構造は、表面に溝構造を有する基板と、前記溝を埋設する二酸化ケイ素膜とを具備してなり、前記二酸化ケイ素膜が前記基板の表面側に局在し、前記溝の底部に空孔を具備してなることを特徴とするものである。 A shallow trench isolation structure provided by the present invention includes a substrate having a groove structure on a surface thereof, and a silicon dioxide film that embeds the groove, and the silicon dioxide film is on the surface side of the substrate. It is localized and has a hole at the bottom of the groove.
　また、本発明により提供されるシャロー・トレンチ・アイソレーション構造の製造方法は、
（Ａ）溝構造を有する基板表面にポリシラザン組成物を塗布して塗膜を形成させる塗布工程、
（Ｂ）前記塗膜の表面に紫外線を照射して、塗膜の表面近傍にあるポリシラザンの一部を硬化させ、溝部分の底部に空孔を形成させる紫外線照射工程、および
（Ｃ）前記塗膜を焼成することにより、塗膜全体を硬化させて二酸化ケイ素膜を形成させる焼成工程、
を含んでなることを特徴とするものである。 In addition, the manufacturing method of the shallow trench isolation structure provided by the present invention includes:
(A) A coating process in which a polysilazane composition is coated on a substrate surface having a groove structure to form a coating film,
(B) An ultraviolet irradiation step of irradiating the surface of the coating film with ultraviolet rays to cure a part of polysilazane in the vicinity of the surface of the coating film to form pores at the bottom of the groove portion, and (C) the coating A baking step in which the entire coating film is cured to form a silicon dioxide film by baking the film,
It is characterized by comprising.
　本発明によれば、従来のシャロー・トレンチ・アイソレーション構造とは異なった、空孔を有していながら絶縁特性にすぐれたシャロー・トレンチ・アイソレーション構造が提供される。また、本発明の方法によれば、簡便かつ低コストでシャロー・トレンチ・アイソレーション構造を形成させることができる。 According to the present invention, there is provided a shallow trench isolation structure that is different from the conventional shallow trench isolation structure and has excellent insulation characteristics while having holes. Further, according to the method of the present invention, a shallow trench isolation structure can be formed easily and at low cost.
本発明によるシャロー・トレンチ・アイソレーション構造の断面模式図。The cross-sectional schematic diagram of the shallow trench isolation structure by this invention.
　以下、本発明の実施の形態について、詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail.
シャロー・トレンチ・アイソレーション構造
　本発明によるトレンチ・アイソレーション構造は、表面に溝構造を有する基板と、前記溝を埋設する二酸化ケイ素膜とを具備してなる。そして、溝を埋設している二酸化ケイ素膜が、溝内を完全に充填しておらず、前記基板の表面側に局在し、前記溝の底部には空孔が存在することが本発明によるシャロー・トレンチ・アイソレーション構造の特徴である。この構造を図示すると図１の通りである。 Shallow Trench Isolation Structure A trench isolation structure according to the present invention comprises a substrate having a groove structure on the surface and a silicon dioxide film in which the groove is embedded. According to the present invention, the silicon dioxide film in which the groove is embedded does not completely fill the groove, is localized on the surface side of the substrate, and there is a hole in the bottom of the groove. This is a characteristic of the shallow trench isolation structure. This structure is shown in FIG.
　すなわち、基板１の溝部の表面近傍に二酸化ケイ素膜（絶縁膜）２が形成され、溝部の底部には空孔３が形成されている。この図１から明らかなように、本発明において空孔３は相対的に小さな空孔が集合したものではなく、実質的に一つの連続したものとなっている。すなわち、本発明における空孔は、溝の形状に沿った帯状または紐状の形状を有するものである。そして、溝を埋設している二酸化ケイ素膜２は、溝の内側に存在するが、基盤の表面側に局在している。すなわち、二酸化ケイ素膜２は溝内に空孔３を封じ込んでいるといえる。そして、空孔３と溝の内面との界面は直接接触しており、溝の内側表面には二酸化ケイ素膜は存在しない。従来、シャロー・トレンチ・アイソレーション構造を形成させる場合、溝内を絶縁膜で緻密かつ均一に充填することが好ましいと考えられていた。
確かに、溝内が緻密かつ均一に充填することによりアイソレーション構造の絶縁性は高くなる。しかしながら、本発明者らの検討によれば、実際に基板表面上に素子が実装された場合、溝内の底部には電界が比較的かかりにくいために、あまり高い絶縁性は要求されないことがわかった。しかも、溝内に形成される空孔は、それ自体絶縁性が比較的高い。すなわち、特に高い絶縁性が要求されるのは素子に近い表面近傍であり、表面近傍に緻密な絶縁膜を形成させれば、溝の底部に空孔があったとしても、アイソレーション構造として必要な絶縁性を達成できるのである。そして、溝の底部に空孔が形成されるがゆえに、その直上にある二酸化ケイ素膜が圧縮され、より緻密な二酸化ケイ素膜となるものと考えられる。 That is, a silicon dioxide film (insulating film) 2 is formed in the vicinity of the surface of the groove portion of the substrate 1, and a hole 3 is formed at the bottom of the groove portion. As is apparent from FIG. 1, in the present invention, the holes 3 are not a collection of relatively small holes but are substantially one continuous. That is, the hole in the present invention has a belt-like or string-like shape along the shape of the groove. The silicon dioxide film 2 in which the groove is embedded is present inside the groove, but is localized on the surface side of the substrate. In other words, it can be said that the silicon dioxide film 2 seals the holes 3 in the groove. The interface between the hole 3 and the inner surface of the groove is in direct contact, and there is no silicon dioxide film on the inner surface of the groove. Conventionally, when forming a shallow trench isolation structure, it has been considered preferable to fill the groove with an insulating film densely and uniformly.
Certainly, the insulation of the isolation structure is enhanced by filling the inside of the groove densely and uniformly. However, according to the study by the present inventors, it is found that when an element is actually mounted on the substrate surface, an electric field is relatively difficult to be applied to the bottom of the groove, so that a very high insulating property is not required. It was. In addition, the holes formed in the grooves themselves have a relatively high insulating property. That is, particularly high insulation is required in the vicinity of the surface near the element, and if a dense insulating film is formed in the vicinity of the surface, even if there is a hole in the bottom of the groove, it is necessary as an isolation structure Can achieve a good insulation. And since a void | hole is formed in the bottom part of a groove | channel, it is thought that the silicon dioxide film immediately above it is compressed and becomes a more precise silicon dioxide film.
　ここで、このようなアイソレーション構造が好ましい絶縁特性を達成するためには、特定の寸法であることが好ましいが、本発明においてはトレンチ・アイソレーション溝の溝幅がより狭く、またアスペクト比がより高い場合に優れた特性を示す。すなわち、溝の幅ａが５～５０ｎｍであることが好ましく、５～４０ｎｍであることが好ましい。また、溝の幅ａに対する溝の深さｂの比、すなわちアスペクト比ｂ／ａが１０～１００であることが好ましく、１０～５０であることがより好ましい。 Here, in order to achieve a preferable insulation characteristic, such an isolation structure preferably has a specific size. However, in the present invention, the groove width of the trench isolation groove is narrower and the aspect ratio is smaller. Excellent properties are exhibited at higher temperatures. That is, the groove width a is preferably 5 to 50 nm, and more preferably 5 to 40 nm. The ratio of the groove depth b to the groove width a, that is, the aspect ratio b / a is preferably 10 to 100, and more preferably 10 to 50.
　また、空孔の溝深さ方向の長さをｃとしたとき、ｃが５～１００ｎｍであることが好ましく、５～５０ｎｍであることがより好ましい。また、溝の長さ方向に垂直な断面を観察したとき、溝構造の断面積に対する、空孔の断面積の割合が５～２０％であることが好ましく、８～１５％であることが好ましい。この空孔の溝深さ方向の長さ、または空孔の断面積の割合が一定以上あるときに緻密な二酸化ケイ素膜が得られ、アイソレーション構造の絶縁特性が十分に発揮される。また空孔が大きくなることにより、二酸化ケイ素膜が圧縮されて緻密となり、引張り応力が低減されるとともに、その物理的強度が十分なものとなる。 Further, when the length of the hole in the groove depth direction is c, c is preferably 5 to 100 nm, and more preferably 5 to 50 nm. Further, when a cross section perpendicular to the length direction of the groove is observed, the ratio of the cross-sectional area of the hole to the cross-sectional area of the groove structure is preferably 5 to 20%, and preferably 8 to 15%. . A dense silicon dioxide film can be obtained when the length of the holes in the groove depth direction or the ratio of the cross-sectional area of the holes is above a certain level, and the insulation characteristics of the isolation structure are sufficiently exhibited. In addition, since the pores become large, the silicon dioxide film is compressed and becomes dense, the tensile stress is reduced, and the physical strength is sufficient.
　また、本発明において溝の底部に空孔が存在するが、その部分には二酸化ケイ素膜はほとんど存在しない。すなわち、空孔部分においては、溝内壁には二酸化ケイ素はほとんど付着していない。このため、溝構造の断面積に対する、空孔の断面積の割合は、ｃ／ｂに相当するので、ｃ／ｂは、０．０５～０．２であることが好ましく、０．０８～０．１５であることが好ましい。 Further, in the present invention, there is a hole at the bottom of the groove, but there is almost no silicon dioxide film in that portion. That is, in the hole portion, silicon dioxide hardly adheres to the inner wall of the groove. For this reason, since the ratio of the cross-sectional area of the holes to the cross-sectional area of the groove structure corresponds to c / b, c / b is preferably 0.05 to 0.2, preferably 0.08 to 0. .15 is preferred.
　なお、本発明によるトレンチ・アイソレーション構造は、ここに記載したような溝の溝幅およびアスペクト比、ならびに空孔の大きさであるとき、効果が強く発現するが、これらの大きさは特に限定されず、基板上の溝が二酸化ケイ素膜により埋設され、その二酸化ケイ素膜が基板の表面側に局在し、前記溝の底部に空孔を具備してなる構造を有するものであれば、本発明の効果を得ることができる。 It should be noted that the trench isolation structure according to the present invention exerts a strong effect when the groove width and aspect ratio and the hole size are as described herein, but these sizes are particularly limited. As long as the groove on the substrate is embedded with a silicon dioxide film, the silicon dioxide film is localized on the surface side of the substrate, and has a structure having holes at the bottom of the groove, the present The effects of the invention can be obtained.
シャロー・トレンチ・アイソレーション構造の形成方法
　上記のようなシャロー・トレンチ・アイソレーション構造は、任意の方法で形成させることができる。そのような方法のひとつとして、
（Ａ）溝構造を有する基板表面にポリシラザン組成物を塗布して塗膜を形成させる塗布工程、
（Ｂ）前記塗膜の表面に紫外線を照射して、塗膜の表面近傍にあるポリシラザンの一部を硬化させ、溝部分の底部に空孔を形成させる紫外線照射工程、および
（Ｃ）前記塗膜を焼成することにより、塗膜全体を硬化させて二酸化ケイ素膜を形成させる焼成工程、
を含んでなる方法がある。 Method for Forming Shallow Trench Isolation Structure The shallow trench isolation structure as described above can be formed by any method. One such method is
(A) A coating process in which a polysilazane composition is coated on a substrate surface having a groove structure to form a coating film,
(B) An ultraviolet irradiation step of irradiating the surface of the coating film with ultraviolet rays to cure a part of polysilazane in the vicinity of the surface of the coating film to form pores at the bottom of the groove portion, and (C) the coating A baking step in which the entire coating film is cured to form a silicon dioxide film by baking the film,
There is a method comprising
　本発明によるシャロー・トレンチ・アイソレーション構造の形成方法の特徴は、ポリシラザン組成物を塗布した後、まず塗膜の表面に紫外線を照射して表面近傍を仮に硬化させ、その後に焼成して、塗膜全体を二酸化ケイ素膜に転化させることにある。まず、基板表面に紫外線を照射することにより、ポリシラザンの酸化および重合が起こり、それによって体積収縮が起こる。この結果、溝内のポリシラザン組成物またはそれが転化して形成された二酸化ケイ素膜に引き上げられる力が作用する。そして、表面近傍においては、二酸化ケイ素膜の密度が高くなって、より緻密になり、トレンチ底部には空孔が生じるのである。引き続く焼成工程においては、二酸化ケイ素膜はさらに収縮する傾向にあるが、溝内の底部には接触していないために底面方向には引っ張り力が作用せず、二酸化ケイ素膜はより高い密度が達成できる。 A feature of the method for forming a shallow trench isolation structure according to the present invention is that after the polysilazane composition is applied, the surface of the coating film is first irradiated with ultraviolet rays to temporarily cure the vicinity of the surface, and then baked and applied. The purpose is to convert the entire film into a silicon dioxide film. First, by irradiating the substrate surface with ultraviolet rays, polysilazane is oxidized and polymerized, thereby causing volume shrinkage. As a result, a pulling force acts on the polysilazane composition in the groove or the silicon dioxide film formed by converting it. In the vicinity of the surface, the density of the silicon dioxide film is increased and becomes denser, and vacancies are generated at the bottom of the trench. In the subsequent firing process, the silicon dioxide film tends to shrink further, but since it does not contact the bottom of the groove, no pulling force acts on the bottom surface, and the silicon dioxide film achieves a higher density. it can.
　すなわち、従来は溝内を均一に充填しようとするために、溝内を比較的密度が低い二酸化ケイ素膜が充填していたのに対して、本願発明の方法により形成されるシャロー・トレンチ・アイソレーション構造は、密度の高い二酸化ケイ素膜（絶縁膜）が表面近傍にのみ形成されるのである。 In other words, in the past, in order to uniformly fill the trench, the trench was filled with a silicon dioxide film having a relatively low density, whereas the shallow trench isolator formed by the method of the present invention was used. In the structure, a silicon dioxide film (insulating film) having a high density is formed only near the surface.
　本発明によるシャロー・トレンチ・アイソレーション構造の形成方法について、より詳細に説明すると以下の通りである。 The method for forming the shallow trench isolation structure according to the present invention will be described in more detail as follows.
（Ａ）塗布工程
　まず、シャロー・トレンチ・アイソレーション構造を形成させるための溝構造、すなわち凹凸を有する基板を用意する。基板の材質は特に限定されず、従来知られている任意の基板、たとえばシリコン基板を用いることができる。また基板表面に溝を形成するには、任意の方法を用いることができ、例えば特許文献１または２にも記載されている。具体的な方法は、以下に示すとおりである。 (A) Application Step First, a groove structure for forming a shallow trench isolation structure, that is, a substrate having irregularities is prepared. The material of the substrate is not particularly limited, and any conventionally known substrate such as a silicon substrate can be used. Further, any method can be used to form the groove on the substrate surface, which is also described in, for example, Patent Document 1 or 2. A specific method is as follows.
　まず、シリコン基板表面に、例えば熱酸化法により、二酸化ケイ素膜を形成させる。ここで形成させる二酸化ケイ素膜の厚さは一般に５～３０ｎｍである。 First, a silicon dioxide film is formed on the surface of a silicon substrate by, for example, a thermal oxidation method. The thickness of the silicon dioxide film formed here is generally 5 to 30 nm.
　必要に応じて、形成された二酸化ケイ素膜上に、例えば減圧ＣＶＤ法により、窒化シリコン膜を形成させる。この窒化シリコン膜は、後のエッチング工程におけるマスク、あるいは後述する研磨工程におけるストップ層として機能させることのできるものである。窒化シリコン膜は、形成させる場合には、一般に１００～４００ｎｍの厚さで形成させる。 If necessary, a silicon nitride film is formed on the formed silicon dioxide film by, for example, a low pressure CVD method. This silicon nitride film can function as a mask in a later etching process or a stop layer in a polishing process described later. The silicon nitride film is generally formed with a thickness of 100 to 400 nm when formed.
　このように形成させた二酸化ケイ素膜または窒化シリコン膜の上に、フォトレジストを塗布する。必要に応じてフォトレジスト膜を乾燥または硬化させた後、所望のパターンで露光および現像してパターンを形成させる。露光の方法はマスク露光、走査露光など、任意の方法で行うことができる。また、フォトレジストも解像度などの観点から任意のものを選択して用いることができる。 A photoresist is applied on the silicon dioxide film or silicon nitride film thus formed. The photoresist film is dried or cured as necessary, and then exposed and developed with a desired pattern to form a pattern. The exposure method can be performed by any method such as mask exposure or scanning exposure. Also, any photoresist can be selected and used from the viewpoint of resolution and the like.
　形成されたフォトレジスト膜をマスクとして、窒化シリコン膜およびその下にある二酸化ケイ素膜を順次エッチングする。この操作によって、窒化シリコン膜および二酸化ケイ素膜に所望のパターンが形成される。 Using the formed photoresist film as a mask, the silicon nitride film and the underlying silicon dioxide film are sequentially etched. By this operation, a desired pattern is formed on the silicon nitride film and the silicon dioxide film.
　パターンが形成された窒化シリコン膜および二酸化ケイ素膜をマスクとして、シリコン基板をドライエッチングして、トレンチ・アイソレーション溝を形成させる。 Using the silicon nitride film and silicon dioxide film on which the pattern is formed as a mask, the silicon substrate is dry-etched to form trench isolation grooves.
　形成されるトレンチ・アイソレーション溝の幅は、フォトレジスト膜を露光するパターンにより決定される。半導体素子におけるトレンチ・アイソレーション溝の幅は、目的とする半導体素子により適切に設定されるが、本発明においては前記のシャロー・トレンチ。アイソレーション構造の項で述べた範囲から選択されることが好ましい。本発明によるトレンチ・アイソレーション構造の形成方法は、従来の方法とは異なり、溝内を均一に充填するものではない。このため、基板表面に形成される溝構造が、より狭く、より深いものであってもよい。 The width of the trench isolation groove to be formed is determined by the pattern for exposing the photoresist film. The width of the trench isolation groove in the semiconductor element is appropriately set depending on the target semiconductor element. In the present invention, the above-described shallow trench. It is preferably selected from the range described in the section of the isolation structure. Unlike the conventional method, the trench isolation structure forming method according to the present invention does not fill the trench uniformly. For this reason, the groove structure formed on the substrate surface may be narrower and deeper.
　次いで、このように準備されたシリコン基板上に、二酸化ケイ素膜の材料となるポリシラザン組成物を塗布して、塗膜を形成させる。このポリシラザン組成物は、従来知られている任意のポリシラザン化合物を溶媒に溶解させたものを用いることができる。 Next, a polysilazane composition as a material for the silicon dioxide film is applied on the silicon substrate thus prepared to form a coating film. As the polysilazane composition, a conventionally known arbitrary polysilazane compound dissolved in a solvent can be used.
　本発明に用いられるポリシラザン化合物は特に限定されず、本発明の効果を損なわない限り任意に選択することができる。これらは、無機化合物あるいは有機化合物のいずれのものであってもよい。これらポリシラザンのうち、好ましいものとして下記一般式（Ｉａ）～（Ｉｃ）で表される単位の組み合わせからなるものが挙げられる： 
Figure JPOXMLDOC01-appb-C000001
 （式中、ｍ１～ｍ３は重合度を表す数である）
　このうち、特に好ましいものとしてスチレン換算重量平均分子量が７００～３０，０００であるものが好ましい。 The polysilazane compound used for this invention is not specifically limited, As long as the effect of this invention is not impaired, it can select arbitrarily. These may be either inorganic compounds or organic compounds. Among these polysilazanes, preferred are those composed of combinations of units represented by the following general formulas (Ia) to (Ic):
Figure JPOXMLDOC01-appb-C000001
 (Where m1 to m3 are numbers representing the degree of polymerization)
Of these, those having a weight average molecular weight in terms of styrene of 700 to 30,000 are particularly preferred.
　また、他のポリシラザンの例として、例えば、主として一般式：
Figure JPOXMLDOC01-appb-C000002
 （式中、Ｒ１、Ｒ２およびＲ３は、それぞれ独立に水素原子、アルキル基、アルケニル基、シクロアルキル基、アリール基、もしくはこれらの基以外でフルオロアルキル基等のケイ素に直結する基が炭素である基、アルキルシリル基、アルキルアミノ基またはアルコキシ基を表す。但し、Ｒ１、Ｒ２およびＲ３の少なくとも１つは水素原子であり、ｎは重合度を表す数である）で表される構造単位からなる骨格を有する数平均分子量が約１００～５０，０００のポリシラザンまたはその変性物が挙げられる。これらのポリシラザン化合物は２種類以上を組み合わせて用いることもできる。 Examples of other polysilazanes include, for example, a general formula:
Figure JPOXMLDOC01-appb-C000002
 (Wherein R 1 , R 2 and R 3 are each independently a hydrogen atom, an alkyl group, an alkenyl group, a cycloalkyl group, an aryl group, or a group directly connected to silicon such as a fluoroalkyl group other than these groups. A group which is carbon, an alkylsilyl group, an alkylamino group or an alkoxy group, provided that at least one of R 1 , R 2 and R 3 is a hydrogen atom and n is a number representing the degree of polymerization). Examples thereof include polysilazane having a skeleton composed of the above structural units and a number average molecular weight of about 100 to 50,000 or a modified product thereof. These polysilazane compounds can be used in combination of two or more.
　本発明に用いられるポリシラザン組成物は、前記のポリシラザン化合物を溶解し得る溶媒を含んでなる。ここで用いられる溶媒は、前記の浸漬用溶液に用いられる溶媒とは別のものである。このような溶媒としては、前記の各成分を溶解し得るものであれば特に限定されるものではないが、好ましい溶媒の具体例としては、次のものが挙げられる：
（ａ）芳香族化合物、例えば、ベンゼン、トルエン、キシレン、エチルベンゼン、ジエチルベンゼン、トリメチルベンゼン、トリエチルベンゼン等、（ｂ）飽和炭化水素化合物、例えばｎ－ペンタン、ｉ－ペンタン、ｎ－ヘキサン、ｉ－ヘキサン、ｎ－ヘプタン、ｉ－ヘプタン、ｎ－オクタン、ｉ－オクタン、ｎ－ノナン、ｉ－ノナン、ｎ－デカン、ｉ－デカン等、（ｃ）脂環式炭化水素化合物、例えばエチルシクロヘキサン、メチルシクロヘキサン、シクロヘキサン、シクロヘキセン、ｐ－メンタン、デカヒドロナフタレン、ジペンテン、リモネン等、（ｄ）エーテル類、例えばジプロピルエーテル、ジブチルエーテル、ジエチルエーテル、メチルターシャリーブチルエーテル（以下、ＭＴＢＥという）、アニソール等、および（ｅ）ケトン類、例えばメチルイソブチルケトン（以下、ＭＩＢＫという）等。これらのうち、（ｂ）飽和炭化水素化合物、（ｃ）脂環式炭化水素化合物（ｄ）エーテル類、および（ｅ）ケトン類がより好ましい。 The polysilazane composition used in the present invention comprises a solvent capable of dissolving the polysilazane compound. The solvent used here is different from the solvent used for the dipping solution. Such a solvent is not particularly limited as long as it can dissolve each of the above-mentioned components. Specific examples of preferable solvents include the following:
(A) Aromatic compounds such as benzene, toluene, xylene, ethylbenzene, diethylbenzene, trimethylbenzene, triethylbenzene, etc. (b) Saturated hydrocarbon compounds such as n-pentane, i-pentane, n-hexane, i-hexane , N-heptane, i-heptane, n-octane, i-octane, n-nonane, i-nonane, n-decane, i-decane, etc., (c) alicyclic hydrocarbon compounds such as ethylcyclohexane, methylcyclohexane Cyclohexane, cyclohexene, p-menthane, decahydronaphthalene, dipentene, limonene, etc., (d) ethers such as dipropyl ether, dibutyl ether, diethyl ether, methyl tertiary butyl ether (hereinafter referred to as MTBE), anisole, and the like, and (E) Keto S, such as methyl isobutyl ketone (hereinafter, referred to as MIBK) and the like. Of these, (b) saturated hydrocarbon compounds, (c) alicyclic hydrocarbon compounds (d) ethers, and (e) ketones are more preferred.
　これらの溶媒は、溶剤の蒸発速度の調整のため、人体への有害性を低くするため、または各成分の溶解性の調製のために、適宜２種以上混合したものも使用できる。 These solvents can be used in combination of two or more as appropriate in order to adjust the evaporation rate of the solvent, to reduce the harmfulness to the human body, or to adjust the solubility of each component.
　本発明に用いられるポリシラザン組成物は、必要に応じてその他の添加剤成分を含有することもできる。そのような成分として、例えばポリシラザンの架橋反応を促進する架橋促進剤等、二酸化ケイ素に転化させる反応の触媒、組成物の粘度を調製するための粘度調整剤などが挙げられる。また、半導体装置に用いられたときにナトリウムのゲッタリング効果などを目的に、リン化合物、例えばトリス（トリメチルシリル）フォスフェート等、を含有することもできる。 The polysilazane composition used in the present invention may contain other additive components as necessary. Examples of such components include a crosslinking accelerator that accelerates the crosslinking reaction of polysilazane, a catalyst for the reaction to be converted into silicon dioxide, a viscosity modifier for adjusting the viscosity of the composition, and the like. In addition, a phosphorus compound such as tris (trimethylsilyl) phosphate may be contained for the purpose of obtaining a sodium gettering effect when used in a semiconductor device.
　また、前記の各成分の含有量は、塗布条件や焼成条件などによって変化する。ただし、ポリシラザン化合物の含有率がポリシラザン組成物の総重量を基準として１～３０重量％であることが好ましく、２～２０重量％とすることがより好ましい。ただし、ポリシラザン組成物に含まれるポリシラザンの濃度はこれに限定されるものではなく、本発明において特定されたトレンチ・アイソレーション構造を形成できるのであれば、任意濃度のポリシラザン組成物を用いることができる。また、ポリシラザン以外の各種添加剤の含有量は、添加剤の種類などによって変化するが、ポリシラザン化合物に対する添加量が０．００１～４０重量％であることが好ましく、０．００５～３０重量％であることがより好ましく、０．０１～２０重量％であることがさらに好ましい。 In addition, the content of each of the above components varies depending on the application conditions, firing conditions, and the like. However, the content of the polysilazane compound is preferably 1 to 30% by weight, more preferably 2 to 20% by weight, based on the total weight of the polysilazane composition. However, the concentration of polysilazane contained in the polysilazane composition is not limited to this, and any concentration of polysilazane composition can be used as long as the trench isolation structure specified in the present invention can be formed. . Further, the content of various additives other than polysilazane varies depending on the type of the additive, etc., but the amount added to the polysilazane compound is preferably 0.001 to 40% by weight, and 0.005 to 30% by weight. More preferably, it is 0.01 to 20% by weight.
　前記のポリシラザン組成物は、任意の方法で基板上に塗布することができる。具体的には、スピンコート、カーテンコート、ディップコート、およびその他が挙げられる。これらのうち、塗膜面の均一性などの観点からスピンコートが特に好ましい。塗布される塗膜の厚さ、すなわち基板表面の溝のない部分における塗膜の厚さは、２０～１５０ｎｍであることが好ましく、３０～１００ｎｍであることがより好ましい。この塗膜の厚さが過度に高いと、溝内の表面近傍まで後述する紫外線が到達しないことがあり、一方で膜厚が薄すぎると、溝内に充填されるポリシラザン組成物が不足し、トレンチの側壁が倒れたり、十分な膜厚の二酸化ケイ素膜が形成できないことがあるので注意が必要である。 The polysilazane composition can be applied on the substrate by any method. Specific examples include spin coating, curtain coating, dip coating, and others. Of these, spin coating is particularly preferable from the viewpoint of uniformity of the coating surface. The thickness of the coating film to be applied, that is, the thickness of the coating film in the portion having no groove on the substrate surface is preferably 20 to 150 nm, and more preferably 30 to 100 nm. If the thickness of this coating film is excessively high, the ultraviolet rays described below may not reach the vicinity of the surface in the groove, while if the film thickness is too thin, the polysilazane composition filled in the groove is insufficient, Care must be taken because the sidewall of the trench may collapse or a silicon dioxide film having a sufficient thickness may not be formed.
（Ｂ）紫外線照射工程
　次いで、ポリシラザン組成物の塗膜の表面に紫外線を照射する。この紫外線は塗布工程で形成されたポリシラザン塗膜の表面近傍に酸化または重合反応を起こさせることを目的としている。したがって、溝内まで紫外線が到達する必要がある。 (B) Ultraviolet irradiation step Next, the surface of the coating film of the polysilazane composition is irradiated with ultraviolet rays. The purpose of this ultraviolet ray is to cause an oxidation or polymerization reaction in the vicinity of the surface of the polysilazane coating film formed in the coating process. Therefore, it is necessary for the ultraviolet rays to reach the inside of the groove.
　用いられる紫外線の波長はポリシラザン組成物の種類にも依存するが、１５０～２００ｎｍであることが好ましく、１７０～１９０ｎｍであることがより好ましい。照射する光エネルギーは、好ましくは０．０５～１００ｍＪ／ｃｍ２、より好ましくは０．１～５０Ｊ／ｃｍ２、である。 The wavelength of the ultraviolet rays used depends on the type of polysilazane composition, but is preferably 150 to 200 nm, and more preferably 170 to 190 nm. The light energy to be irradiated is preferably 0.05 to 100 mJ / cm 2 , more preferably 0.1 to 50 J / cm 2 .
　照射は一般に空気中で行うことができる。しかし、酸素は例えば２００ｎｍ以下の波長を有する光を吸収するため、雰囲気の酸素濃度や光源と基板との間の距離によっては、光が基板表面に到達するまでに雰囲気中の酸素に吸収されてしまい、十分な光が溝内まで到達しないこともあり得る。このため、必要に応じて、窒素などの紫外線吸収のない不活性気体と空気または酸素とが混合された雰囲気下、あるいは紫外線吸収のない不活性気体雰囲気下で紫外線照射を行うことも好ましい。 Irradiation can generally be performed in air. However, since oxygen absorbs light having a wavelength of 200 nm or less, for example, depending on the oxygen concentration in the atmosphere and the distance between the light source and the substrate, the light is absorbed by the oxygen in the atmosphere before reaching the substrate surface. In other words, sufficient light may not reach the inside of the groove. For this reason, it is also preferable to perform ultraviolet irradiation in an atmosphere in which an inert gas such as nitrogen that does not absorb ultraviolet rays and air or oxygen is mixed, or in an inert gas atmosphere that does not absorb ultraviolet rays.
　このような紫外線照射によって、溝内に充填されたポリシラザンのうち、基板表面近傍に存在するものが酸化または重合反応を起こし、溝内底部からポリシラザン組成物を引き上げ、緻密な二酸化ケイ素膜と溝内底部の空孔の原型ができあがる。 By such ultraviolet irradiation, among the polysilazanes filled in the grooves, those existing in the vicinity of the substrate surface cause an oxidation or polymerization reaction, and the polysilazane composition is pulled up from the bottom of the grooves to form a dense silicon dioxide film and the grooves. A prototype of the hole at the bottom is completed.
　なお、特許文献４および５には、紫外線を照射することを含むＳＯＧ膜の形成方法が開示されている。しかし、これらの方法は溝内を均一に絶縁膜で充填するものであり、本発明とは異なった構造を達成するためのものである。 Note that Patent Documents 4 and 5 disclose a method for forming an SOG film including irradiation with ultraviolet rays. However, these methods are to fill the trench uniformly with an insulating film, and to achieve a structure different from the present invention.
（Ｃ）焼成工程
　紫外線照射工程に引き続き、ポリシラザン塗膜を焼成して、塗膜全体を二酸化ケイ素膜に転化させる。この焼成によって、紫外線照射工程により形成された二酸化ケイ素膜の原型が完全に二酸化ケイ素膜、すなわち絶縁膜に転化される、焼成は、硬化炉やホットプレートを用いて、水蒸気を含んだ、不活性ガスまたは酸素雰囲気下で行うことが好ましい。
水蒸気は、ケイ素含有化合物またはケイ素含有重合体、ならびに存在する場合にはポリシラザン化合物を二酸化ケイ素に十分に転化させるのに重要であり、好ましくは１％以上、より好ましくは１０％以上、最も好ましくは２０％以上とする。特に水蒸気濃度が２０％以上であると、シラザン化合物の二酸化ケイ素膜への転化が進行しやすくなり、ボイドなどの欠陥の発生が少なくなり、二酸化ケイ素膜の特性が改良されるので好ましい。雰囲気ガスとして不活性ガスを用いる場合には、窒素、アルゴン、またはヘリウムなどを用いる。 (C) Firing step Following the ultraviolet irradiation step, the polysilazane coating film is baked to convert the entire coating film into a silicon dioxide film. By this baking, the prototype of the silicon dioxide film formed by the ultraviolet irradiation process is completely converted into a silicon dioxide film, that is, an insulating film. The baking is performed using a curing furnace or a hot plate, and contains water vapor. It is preferably performed in a gas or oxygen atmosphere.
Water vapor is important to fully convert the silicon-containing compound or silicon-containing polymer, as well as the polysilazane compound, if present, to silicon dioxide, preferably 1% or more, more preferably 10% or more, most preferably 20% or more. In particular, when the water vapor concentration is 20% or more, the conversion of the silazane compound to the silicon dioxide film is likely to proceed, the occurrence of defects such as voids is reduced, and the characteristics of the silicon dioxide film are improved. When an inert gas is used as the atmospheric gas, nitrogen, argon, helium, or the like is used.
　硬化させるための温度条件は、用いるポリシラザン組成物の種類や、工程の組み合わせ方によって変化する。しかしながら、温度が高いほうがケイ素含有化合物、ケイ素含有重合体、およびポリシラザン化合物が二酸化ケイ素膜に転化される速度が速くなる傾向にあり、また、温度が低いほうがシリコン基板の酸化または結晶構造の変化によるデバイス特性への悪影響が小さくなる傾向がある。このような観点から、本発明による方法では、通常１０００℃以下、好ましくは４００～９００℃で加熱を行う。ここで、目標温度までの昇温時間は一般に１～１００℃／分であり、目標温度に到達してからの硬化時間は一般に１分～１０時間、好ましくは１５分～３時間、である。必要に応じて硬化温度または硬化雰囲気の組成を段階的に変化させることもできる。 The temperature condition for curing varies depending on the type of polysilazane composition to be used and the combination of processes. However, higher temperatures tend to increase the rate at which silicon-containing compounds, silicon-containing polymers, and polysilazane compounds are converted to silicon dioxide films, and lower temperatures are due to oxidation of the silicon substrate or changes in crystal structure. There is a tendency for adverse effects on device characteristics to be reduced. From such a viewpoint, in the method according to the present invention, heating is usually performed at 1000 ° C. or lower, preferably 400 to 900 ° C. Here, the temperature raising time to the target temperature is generally 1 to 100 ° C./min, and the curing time after reaching the target temperature is generally 1 minute to 10 hours, preferably 15 minutes to 3 hours. If necessary, the curing temperature or the composition of the curing atmosphere can be changed stepwise.
　この加熱により、塗布膜中に存在するポリシラザン化合物を二酸化ケイ素に転化させて最終的なシャロー・トレンチ・アイソレーション構造を得ることができる。このようにして得られた、本発明によるシャロー・トレンチ・アイソレーション構造は、溝部近傍の引張り応力が低減されており、物理的強度が高いものである。これは、焼成に先立って行われる紫外線照射によって溝底部に空孔が形成され、空孔の直上部分に存在するポリシラザン組成物またはそれに由来する二酸化ケイ素膜の前駆体の密度が高くなっているために、焼成によって形成される二酸化ケイ素膜の密度が高くなるためである。 By this heating, the polysilazane compound present in the coating film can be converted into silicon dioxide, and the final shallow trench isolation structure can be obtained. The thus obtained shallow trench isolation structure according to the present invention has a high physical strength with reduced tensile stress in the vicinity of the groove. This is because vacancies are formed at the bottom of the groove by ultraviolet irradiation performed prior to firing, and the density of the polysilazane composition present in the portion immediately above the vacancies or the precursor of the silicon dioxide film derived therefrom is high. In addition, this is because the density of the silicon dioxide film formed by firing increases.
　本発明によるシャロー・トレンチ・アイソレーション構造の形成方法は、前記した（Ａ）～（Ｃ）の工程を必須とするが、必要に応じて、下記の補助工程を組み合わせることもできる。 The method for forming a shallow trench isolation structure according to the present invention requires the steps (A) to (C) described above, but the following auxiliary steps may be combined as necessary.
（ａ）溶媒除去工程
　塗布工程後、焼成工程に先立って、ポリシラザン組成物が塗布された基板をプリベーク処理をすることができる。この工程では、塗膜中に含まれる溶媒の少なくとも一部を除去することを目的とする。 (A) Solvent removal step After the coating step, the substrate coated with the polysilazane composition can be pre-baked prior to the firing step. This step aims to remove at least a part of the solvent contained in the coating film.
　通常、溶媒除去工程では、実質的に一定温度で加熱する方法がとられる。このとき、実質的にポリシラザンの酸化または重合反応が起こらない条件で溶媒除去を行うべきである。したがって、溶媒除去工程における温度は通常５０～２５０℃、好ましくは８０～２００℃、の範囲内である。溶媒除去工程の所要時間は一般に０．５～１０分、好ましくは１～５分、である。 Usually, in the solvent removal step, a method of heating at a substantially constant temperature is used. At this time, the solvent should be removed under conditions that do not substantially oxidize or polymerize the polysilazane. Therefore, the temperature in the solvent removal step is usually in the range of 50 to 250 ° C., preferably 80 to 200 ° C. The time required for the solvent removal step is generally 0.5 to 10 minutes, preferably 1 to 5 minutes.
（ｂ）研磨工程
　硬化させた後、硬化した二酸化ケイ素膜の不要な部分は除去することが好ましい。そのために、まず研磨工程により、基板上の溝部内側に形成された二酸化ケイ素膜を残し、基板表面の平坦部上に形成された二酸化ケイ素膜を研磨により除去する。この工程が研磨工程である。この研磨工程は、硬化処理の後に行うほか、プリベーク工程を組み合わせる場合には、プリベーク直後に行うこともできる。 (B) Polishing Step After curing, it is preferable to remove unnecessary portions of the cured silicon dioxide film. For this purpose, first, the silicon dioxide film formed on the inner side of the groove on the substrate is left by the polishing process, and the silicon dioxide film formed on the flat portion of the substrate surface is removed by polishing. This process is a polishing process. This polishing step can be performed immediately after pre-baking, in addition to the curing treatment, or in the case of combining the pre-baking step.
　研磨は、一般的にＣＭＰにより行う。このＣＭＰによる研磨は、一般的な研磨剤および研磨装置により行うことができる。具体的には、研磨剤としてはシリカ、アルミナ、またはセリアなどの研磨材と、必要に応じてその他の添加剤とを分散させた水溶液などを用いることができる、研磨装置としては、市販の一般的なＣＭＰ装置を用いることができる。 Polishing is generally performed by CMP. This polishing by CMP can be performed with a general abrasive and polishing apparatus. Specifically, as the polishing agent, an aqueous solution in which an abrasive such as silica, alumina, or ceria and other additives are dispersed as required can be used. A typical CMP apparatus can be used.
（ｃ）エッチング工程
　前記の研磨工程において、基板表面の平坦部上に形成されたポリシラザン組成物に由来する二酸化ケイ素膜はほとんど除去されるが、基板表面の平坦部に残存している二酸化ケイ素膜を除去するために、さらにエッチング処理を行うことが好ましい。エッチング処理はエッチング液を用いるのが一般的であり、エッチング液としては、二酸化ケイ素膜を除去できるものであれば特に限定されないが、通常はフッ化アンモニウムを含有するフッ酸水溶液を用いる。この水溶液のフッ化アンモニウム濃度は５％以上であることが好ましく、３０％以上であることがより好ましい。 (C) Etching Step In the polishing step, the silicon dioxide film derived from the polysilazane composition formed on the flat portion of the substrate surface is almost removed, but the silicon dioxide film remaining on the flat portion of the substrate surface is removed. In order to remove this, it is preferable to further perform an etching process. An etching solution is generally used for the etching treatment, and the etching solution is not particularly limited as long as it can remove the silicon dioxide film. Usually, a hydrofluoric acid aqueous solution containing ammonium fluoride is used. The concentration of ammonium fluoride in this aqueous solution is preferably 5% or more, and more preferably 30% or more.
　本発明を諸例を用いて説明すると以下の通りである。 The present invention will be described with reference to various examples as follows.
実施例１
　まず、表面に溝構造を有するシリコン基板を準備した。その溝の幅は４０ｎｍであり、深さは６００ｎｍ（アスペクト比１５）であった。 Example 1
First, a silicon substrate having a groove structure on the surface was prepared. The width of the groove was 40 nm and the depth was 600 nm (aspect ratio 15).
　ポリシラザンのジブチルエーテル溶液（組成物の総重量を基準とした固形分濃度が１２重量％）を前記の基板に回転数１０００ｒｐｍの条件でスピンコートし、１５０℃で１分間の条件で溶媒の一部を除去した。このとき、基板表面の溝構造以外の部分におけるポリシラザン組成物塗膜の膜厚は８０ｎｍであった。また、この基板を表面に垂直に切断して溝構造の断面を走査型電子顕微鏡（株式会社日立製作所製Ｓ－４７００型（商品名））を用いて観察したところ、溝内には空孔は認められなかった。 A solution of polysilazane in dibutyl ether (solid content concentration based on the total weight of the composition is 12% by weight) is spin-coated on the above substrate at 1000 rpm and a part of the solvent at 150 ° C. for 1 minute. Was removed. At this time, the film thickness of the polysilazane composition coating film in the portion other than the groove structure on the substrate surface was 80 nm. Further, this substrate was cut perpendicularly to the surface, and a cross section of the groove structure was observed using a scanning electron microscope (S-4700 type (trade name) manufactured by Hitachi, Ltd.). I was not able to admit.
　この基板表面に、エキシマＵＶ照射装置（ウシオ電機株式会社製）を用いて、波長１７２ｎｍの紫外線を１０ｍＷ／ｃｍ２で３分間照射した。 The surface of the substrate was irradiated with ultraviolet rays having a wavelength of 172 nm at 10 mW / cm 2 for 3 minutes using an excimer UV irradiation device (manufactured by USHIO INC.).
　このときの溝構造の断面を走査型電子顕微鏡を用いて観察したところ、溝構造の底部に空孔が形成されていることが確認できた。 When the cross section of the groove structure at this time was observed using a scanning electron microscope, it was confirmed that holes were formed at the bottom of the groove structure.
　さらにこの基板を、水蒸気酸化炉ＶＦ－１０００（商品名：光洋サーモシステム株式会社製）にて、酸素／水蒸気混合ガス（Ｈ２Ｏ／（Ｏ２＋Ｈ２Ｏ）＝８０ｍｏｌ％）を８リットル／分の速度で流した雰囲気下、４００℃で１時間、焼成した。さらに引き続いて、Ｎ２雰囲気下７００℃でアニール処理を１時間行った。得られた試料の引張り応力を測定したところ、１０Ｍｐａであった。 Further, this substrate was subjected to an oxygen / steam mixed gas (H 2 O / (O 2 + H 2 O) = 80 mol%) in a steam oxidation furnace VF-1000 (trade name: manufactured by Koyo Thermo System Co., Ltd.) at 8 liters / Baking was carried out at 400 ° C. for 1 hour in an atmosphere that flowed at a rate of minutes. Subsequently, annealing treatment was performed at 700 ° C. for 1 hour in an N 2 atmosphere. It was 10 Mpa when the tensile stress of the obtained sample was measured.
　また、その断面を走査型電子顕微鏡で観察したところ、焼成前の空孔が維持されており、溝の底部に空孔を有するシャロー・トレンチ・アイソレーション構造が形成されていた。 Further, when the cross section was observed with a scanning electron microscope, the holes before firing were maintained, and a shallow trench isolation structure having holes at the bottom of the groove was formed.
　ここで、空孔の直上に形成された二酸化ケイ素膜のウェットエッチングレートを、緩衝剤として２０重量％のフッ化アンモニウムを含む、０．５重量％濃度のフッ酸水溶液を用いて、測定した。実施例１による二酸化ケイ素膜のウェットエッチングレートは熱酸化膜を基準として１．８０であった。 Here, the wet etching rate of the silicon dioxide film formed immediately above the pores was measured using a 0.5 wt% hydrofluoric acid aqueous solution containing 20 wt% ammonium fluoride as a buffering agent. The wet etching rate of the silicon dioxide film according to Example 1 was 1.80 based on the thermal oxide film.
比較例１
　実施例１に対して、紫外線を照射しないほかは同様にして、溝構造を有する基板上にポリシラザン塗膜を形成させた。この塗膜の断面を観察したところ、溝内はほぼ均一に充填され、空隙は認められなかった。 Comparative Example 1
A polysilazane coating film was formed on a substrate having a groove structure in the same manner as in Example 1 except that ultraviolet rays were not irradiated. When the cross section of this coating film was observed, the inside of the groove was almost uniformly filled and no voids were observed.
　さらに実施例１と同様に焼成およびアニール処理を行い、得られた試料の引張り応力を測定したところ、１２０ＭＰａであった。実施例１に比較して非常に高く、溝内部にクラックや脱落などの欠陥が起きやすいことがわかった。 Further, firing and annealing were performed in the same manner as in Example 1, and the tensile stress of the obtained sample was measured and found to be 120 MPa. It was very high compared to Example 1, and it was found that defects such as cracks and dropouts were likely to occur inside the groove.
　また、その断面を走査型電子顕微鏡で観察したところ、溝内に空孔の無いシャロー・トレンチ・アイソレーション構造が形成されていた。 Further, when the cross section was observed with a scanning electron microscope, a shallow trench isolation structure having no voids was formed in the groove.
　得られた二酸化ケイ素膜について、実施例１と同様にウェットエッチングレートを測定した。比較例１よる二酸化ケイ素膜のウェットエッチングレートは熱酸化膜を基準として４．１０であった。ここで、ウェットエッチングレートは膜応力（引張応力）と正の相関関係があることが知られている、すなわち、実施例１による二酸化ケイ素膜はウェットエッチングレートが低く優れている。なお、一般にこのウェットエッチングレートが３を超えると実用性の観点から用途が限定される。 For the obtained silicon dioxide film, the wet etching rate was measured in the same manner as in Example 1. The wet etching rate of the silicon dioxide film according to Comparative Example 1 was 4.10 based on the thermal oxide film. Here, it is known that the wet etching rate has a positive correlation with the film stress (tensile stress), that is, the silicon dioxide film according to Example 1 has a low wet etching rate and is excellent. In general, when the wet etching rate exceeds 3, the use is limited from the viewpoint of practicality.
　　１　基板
　　２　絶縁膜
　　３　空孔 1 Substrate 2 Insulating film 3 Hole

Claims (10)

  1. 　表面に溝構造を有する基板と、前記溝を埋設する二酸化ケイ素膜とを具備してなり、前記二酸化ケイ素膜が前記基板の表面側に局在し、前記溝の底部に空孔を具備してなることを特徴とする、シャロー・トレンチ・アイソレーション構造。 A substrate having a groove structure on the surface, and a silicon dioxide film embedded in the groove, wherein the silicon dioxide film is localized on the surface side of the substrate, and has a void at the bottom of the groove. A shallow trench isolation structure characterized by
  2. 　前記溝の溝幅が、５～５０ｎｍである、請求項１に記載のシャロー・トレンチ・アイソレーション構造。 The shallow trench isolation structure according to claim 1, wherein a groove width of the groove is 5 to 50 nm.
  3. 　前記溝のアスペクト比が、１０～１００である、請求項１または２に記載のシャロー・トレンチ・アイソレーション構造。 The shallow trench isolation structure according to claim 1 or 2, wherein the groove has an aspect ratio of 10 to 100.
  4. 　前記空孔の溝深さ方向の長さが５～１００ｎｍである、請求項１～３のいずれか１項に記載のシャロー・トレンチ・アイソレーション構造。 The shallow trench isolation structure according to any one of claims 1 to 3, wherein a length of the hole in a groove depth direction is 5 to 100 nm.
  5. （Ａ）溝構造を有する基板表面にポリシラザン組成物を塗布して塗膜を形成させる塗布工程、
    （Ｂ）前記塗膜の表面に紫外線を照射して、塗膜の表面近傍にあるポリシラザンの一部を硬化させ、溝部分の底部に空孔を形成させる紫外線照射工程、および
    （Ｃ）前記塗膜を焼成することにより、塗膜全体を硬化させて二酸化ケイ素膜を形成させる焼成工程、
    を含んでなることを特徴とする、シャロー・トレンチ・アイソレーション構造の形成方法。     (A) A coating process in which a polysilazane composition is coated on a substrate surface having a groove structure to form a coating film,
    (B) An ultraviolet irradiation step of irradiating the surface of the coating film with ultraviolet rays to cure a part of polysilazane in the vicinity of the surface of the coating film to form pores at the bottom of the groove portion, and (C) the coating A baking step in which the entire coating film is cured to form a silicon dioxide film by baking the film,
    A method of forming a shallow trench isolation structure, comprising:
  6. 　塗布工程（Ａ）と紫外線照射工程（Ｂ）との間に、前記ポリシラザン組成物に含まれる溶剤の少なくとも一部を蒸発させて除去する溶媒除去工程をさらに含んでなる、請求項５に記載のシャロー・トレンチ・アイソレーション構造の形成方法。 The solvent removal step of evaporating and removing at least a part of the solvent contained in the polysilazane composition between the coating step (A) and the ultraviolet irradiation step (B). A method of forming a shallow trench isolation structure.
  7. 　溝内部に形成された二酸化ケイ素膜を残し、基板表面に形成された余剰の二酸化ケイ素膜を研磨により除去する、請求項５または６に記載のシャロー・トレンチ・アイソレーション構造の形成方法。 The method for forming a shallow trench isolation structure according to claim 5 or 6, wherein the silicon dioxide film formed inside the groove is left, and an excess silicon dioxide film formed on the substrate surface is removed by polishing.
  8. 　ポリシラザン組成物の固形分含有率が、組成物の総重量を基準として１～３０重量％である、請求項５～７のいずれか１項に記載のシャロー・トレンチ・アイソレーション構造の形成方法。 The method for forming a shallow trench isolation structure according to any one of claims 5 to 7, wherein the solid content of the polysilazane composition is 1 to 30% by weight based on the total weight of the composition.
  9. 　塗布工程（Ａ）において形成される塗膜の厚さが、基板上の溝構造のない部分において１５０ｎｍ以下である、請求項５～８のいずれか１項に記載のシャロー・トレンチ・アイソレーション構造の形成方法。 The shallow trench isolation structure according to any one of claims 5 to 8, wherein a thickness of the coating film formed in the coating step (A) is 150 nm or less in a portion having no groove structure on the substrate. Forming method.
  10. 　焼成工程における焼成温度が、４００～１１００℃である、請求項５～９のいずれか１項に記載のシャロー・トレンチ・アイソレーション構造の形成方法。 The method for forming a shallow trench isolation structure according to any one of claims 5 to 9, wherein a firing temperature in the firing step is 400 to 1100 ° C.
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Publication number Priority date Publication date Assignee Title
JPS6021539A (en) * 1983-07-15 1985-02-02 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH01248528A (en) * 1988-03-30 1989-10-04 Ushio Inc Hardening of sog film
JP3178412B2 (en) * 1998-04-27 2001-06-18 日本電気株式会社 Method of forming trench isolation structure
JP2004531070A (en) * 2001-06-14 2004-10-07 ストミクロエレクトロニクス・ソシエテ・アノニム Deep insulating trench and method of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021539A (en) * 1983-07-15 1985-02-02 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH01248528A (en) * 1988-03-30 1989-10-04 Ushio Inc Hardening of sog film
JP3178412B2 (en) * 1998-04-27 2001-06-18 日本電気株式会社 Method of forming trench isolation structure
JP2004531070A (en) * 2001-06-14 2004-10-07 ストミクロエレクトロニクス・ソシエテ・アノニム Deep insulating trench and method of forming the same

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