JP4987898B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In the development of semiconductor devices, improvement in speed, reduction in power consumption, and suppression of manufacturing costs are required. In order to satisfy these requirements, it is necessary to miniaturize the semiconductor device and reduce the area of the semiconductor device. One effective means for that purpose is to miniaturize an element isolation region provided to isolate a semiconductor element or the like included in a semiconductor device.

  In recent years, a silicon oxide insulating film is formed in a trench (element isolation groove) formed by an anisotropic etching method such as reactive ion etching (RIE) as a method for manufacturing a fine element isolation region. Shallow Trench Isolation (STI) technology is used, which is formed by embedding silicon.

As a method for forming an insulating film while suppressing generation of voids and seams in the insulating film in such a trench, a spin on glass (SOG) method is known. In this method, a silicon compound (for example, polysilazane (polyperhydrosilazane) [-(SiH ₂ NH) n-]), which is a silicon oxide material, is applied by spin coating, and the silicon compound is oxidized. A silicon oxide insulating film is formed in the trench. A silicon oxide film (insulating film) formed by such a method is particularly called a coating-type silicon oxide film.

The coating type silicon oxide film formed by such a method generally has the following problems.
(1) The film density is low.
(2) There are many impurities in the film.

  As a method for solving these problems, there is a method in which a silicon compound is oxidized to form a coated silicon oxide film, and then an annealing process is performed in an atmosphere of nitrogen or the like. By performing the annealing treatment (heat treatment), the bonding structure of the coated silicon oxide film can be made denser. At the same time, impurities still remaining in the coated silicon oxide film can be removed. Therefore, the problem of the coating type silicon oxide film can be solved.

  However, in the process of forming the coating type silicon oxide film through such treatment, the coating type silicon oxide film contracts and film stress is generated, thereby generating defects in the coating type silicon oxide film, and the coating type. New problems such as peeling of the silicon oxide film and deformation of the element isolation region have arisen.

  Therefore, the following proposals have been made as a method for solving such a new problem.

  In Patent Document 1, instead of forming all the silicon oxide insulating films in the trench by the SOG method, first, a coating type silicon oxide film is formed by the SOG method in the lower half of the trench, and then the coating type oxidation film is formed. There has been proposed a method of embedding an HTO (High Temperature Oxide) film (silicon oxide film) having a finer bond structure than the coated silicon oxide film in the upper half of the trench, which is above the silicon film.

  In Patent Document 2, a coating type silicon oxide film is formed by the SOG method in the lower half of the trench, and a high density plasma chemical vapor phase is formed in the upper half of the trench, which is on the coating type silicon oxide film. There has been proposed a method of embedding a silicon oxide film having a finer bond structure than a coated silicon oxide film by using a growth (High Density Plasma Chemical Vapor Deposition: HDP-CVD) method.

  However, any of the proposed methods requires a CMP (Chemical Mechanical Polishing) process twice or more. That is, since the number of steps is greatly increased and complicated, there is a problem that the process margin is lowered.

  Further, in Patent Document 2, a silicon oxide film having a finer bond structure than that of a coating type silicon oxide film is embedded in the lower half of the trench by HDP-CVD, and further, the trench is exposed on the silicon oxide film. A method of embedding a coating-type silicon oxide film in the upper half has also been proposed. However, this method also has a coating-type silicon oxide film embedded in the upper half of the trench. Therefore, in the coating-type silicon oxide film occupying the upper half of the trench, peeling of the coating-type silicon oxide film and subsequent wet etching are performed. Therefore, there is a problem that a local shape abnormality occurs in the coated silicon oxide film.

JP 2000-114362 A JP 2003-31650 A

  In view of the above circumstances, an object of the present invention is to provide a method for producing a high-quality coated silicon oxide film with few defects.

  According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor, wherein an element isolation groove is formed in a semiconductor substrate, a silicon compound film is formed in the element isolation groove so as to be embedded in the element isolation groove, By the first oxidation treatment at a temperature, the surface of the silicon compound film is modified into a volatile emission preventing layer that allows passage of oxidants and impurities but does not allow passage of volatiles including silicon atoms. A coated silicon oxide film is formed in the element isolation trench by a second oxidation process at a second temperature higher than the first temperature.

  According to the method for manufacturing a semiconductor device of the present invention, a high-quality coated silicon oxide film with few defects can be obtained.

The graph showing the accumulated amount of volatiles having a molecular weight of 76 from the heat treatment temperature and the polysilazane film. The top view (part) of the semiconductor device of embodiment of this invention. Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 1). Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 2). Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 3). Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 4). Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 5). Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 6). Schematic process sectional drawing for demonstrating the manufacturing process of 1st, 4th, 5th embodiment of this invention (the 7). Schematic process sectional drawing for demonstrating the manufacturing process of the 2nd Embodiment of this invention (the 1). Schematic process sectional drawing for demonstrating the manufacturing process of the 2nd Embodiment of this invention (the 2). Schematic process sectional drawing for demonstrating the manufacturing process of the 2nd Embodiment of this invention (the 3). Schematic process sectional drawing for demonstrating the manufacturing process of the 2nd Embodiment of this invention (the 4). Schematic process sectional drawing for demonstrating the manufacturing process of the 2nd Embodiment of this invention (the 5). Schematic process sectional drawing for demonstrating the manufacturing process of the 3rd Embodiment of this invention (the 1). Schematic process sectional drawing for demonstrating the manufacturing process of the 3rd Embodiment of this invention (the 2). Schematic process sectional drawing for demonstrating the manufacturing process of the 3rd Embodiment of this invention (the 3).

  Before describing embodiments of the present invention, a method for forming an insulating film of coated silicon oxide, which has been performed by the present inventor, will be briefly described.

  In this specification, the silicon compound film refers to a film containing silicon atoms that is oxidized to become a coating-type silicon oxide film.

  An example in which an insulating film made of a coated silicon oxide film is formed inside a trench (element isolation groove) of a semiconductor device will be described.

  A semiconductor film is formed over the semiconductor substrate, and a plurality of trenches are formed in part of the semiconductor substrate and the semiconductor film. Next, a silicon compound coating solution (silicon compound solution) in which a silicon compound (for example, polysilazane) as a material of the silicon compound film is dissolved in a solvent is prepared. The trench is filled with this silicon compound coating solution. Then, pre-baking (heat treatment) is performed, thereby evaporating the solvent contained in the silicon compound coating solution. In this way, a silicon compound film is formed inside the plurality of trenches. Next, high-temperature oxidation treatment is performed in an atmosphere such as water vapor. By doing so, the silicon compound film is oxidized, and a coating type silicon oxide film is formed inside the plurality of trenches. Further, annealing treatment (heating treatment) is performed in order to further refine the bonding structure of the coated silicon oxide film.

  Until now, the present inventor has formed a coating type silicon oxide film in the trench by the above method.

  However, in order to further improve the performance, reliability, etc. of the semiconductor device, it is necessary to reduce defects in the coated silicon oxide film inside the trench of the semiconductor device.

  When the silicon compound film is oxidized to form a coated silicon oxide film, high-temperature oxidation treatment or heat treatment causes film shrinkage or film stress, thereby causing defects in the coated silicon oxide film. It is considered.

  First, the inventor independently analyzed the cause of the shrinkage of the coated silicon oxide film during the high-temperature oxidation treatment by oxidizing the silicon compound film to form the coated silicon oxide film.

  The present inventor conducted an experiment in order to know what phenomenon occurs in the silicon compound film during the high-temperature oxidation treatment. That is, in order to know the relationship between the molecular weight of volatiles released from the silicon compound film during the high-temperature oxidation treatment and the emission amount, and the temperature of the high-temperature oxidation treatment, a thermal desorption spectrum (TDS) is used. Was measured.

The details are as follows.
A polysilazane film was formed as a silicon compound film by the above-described method using polysilazane as a silicon compound and dibutyl ether as a solvent in which the polysilazane was dissolved. Next, this polysilazane film was heated while raising the temperature in the presence of an oxidizing agent, and the molecular weight of volatile matter released from the polysilazane film and the pressure of the volatile matter for each molecular weight were measured. The pressure of the volatile matter is proportional to the integrated amount released of the volatile matter.

  The measurement results are shown in FIG. A curve B in FIG. 1 shows the pressure of the volatile matter having a molecular weight of 76 released from the polysilazane film, that is, the integrated amount of release as the temperature of the oxidation treatment increases (for the curve A in FIG. I will explain later.) Note that the curve C in FIG. 1 is the background.

  As can be seen from curve B in FIG. 1, when the oxidation treatment temperature is 300 ° C. or lower, the volatile matter having a molecular weight of 76 is hardly released from the polysilazane film. However, it can be seen that when the oxidation temperature exceeds 300 ° C., the amount of volatiles having a molecular weight of 76 increases rapidly.

The volatiles of the molecular weight of 76, and polysilazane film, a solvent that appears to remain in trace amounts in the polysilazane film (dibutyl ether), the presumed that based on the various elements and molecular structure contained in, SiO _3, SiC ₄ and CH ₄ O ₂ Si. That is, when the temperature of the oxidation treatment exceeds 300 ° C., it is assumed that a low molecular weight substance containing silicon atoms is volatilized from the polysilazane film.

  From the results obtained by such measurement, the present inventor considered the reason why the coated silicon oxide film contracts as follows.

  That is, the silicon compound film (polysilazane film) is oxidized by a high-temperature oxidation treatment at a high temperature, for example, 300 ° C. or higher in the presence of an oxidizing agent, and becomes a coated silicon oxide film. During such a high temperature oxidation treatment, low molecular weight volatiles containing silicon atoms constituting the silicon compound film escape from the silicon compound film and are released. The coated silicon oxide film during the oxidation treatment has a flexible bond structure. For this reason, the coating type silicon oxide film causes film shrinkage in an attempt to make up for the portion from which silicon atoms are lost.

  Based on such unique considerations, the present inventor reduced the shrinkage of the coated silicon oxide film, thereby reducing the defects of the coated silicon oxide film. We thought that it would be good to prevent low molecular weight volatiles containing silicon atoms from being released. For this purpose, the present inventor considered that the oxidation treatment for oxidizing the silicon compound film may be performed at a low temperature, for example, at a temperature of 300 ° C. or lower. However, even if the surface of the silicon compound film can be oxidized by such low-temperature oxidation treatment, it is difficult to sufficiently oxidize the inside of the silicon compound film.

  Therefore, if the inventor cannot avoid using a method of oxidizing a silicon compound film at a high temperature, the low molecular weight volatiles containing silicon atoms are required before performing the high temperature oxidation treatment (second oxidation treatment). It was thought that a volatile matter emission preventing layer having a property of preventing the passage of sapphire should be formed on the silicon compound film. Since such a volatile matter emission preventing layer is on the silicon compound film, it is possible to prevent low molecular weight volatiles containing silicon atoms from being released from the silicon compound film during high-temperature oxidation treatment. It is.

  Further, the present inventor not only has the property that this volatile emission preventing layer does not allow low molecular weight volatiles containing silicon atoms to pass through, but also has the property of allowing oxygen, ozone, water and other oxidizing agents to pass through. I thought of having it. By having the property of allowing these oxidants to pass, the oxidant can reach the silicon compound film located under the volatile emission prevention layer even after the formation of the volatile emission prevention layer. This is because the silicon compound film can be oxidized.

  In addition, the present inventor considered that the volatile matter emission preventing layer has a property of allowing hydrogen and nitrogen to pass through in addition to the properties described so far. Since the volatile matter emission preventing layer has such properties, hydrogen, nitrogen, and the like, which are impurities of the coating type silicon oxide film, are evaporated from the silicon compound film and the coating type silicon oxide film, and these substances are removed from the silicon compound film and the silicon compound film. This is because it can be removed from the coated silicon oxide film.

  Therefore, the present inventor, based on various experimental results so far and the molecular structure of the low molecular weight volatiles containing silicon atoms, has all the properties as described above for the volatile emission preventing layer. To prepare, the volatile emission prevention layer was selected to be formed of silicon oxide.

  Furthermore, the following advantages can be obtained by forming the volatile matter emission preventing layer from silicon oxide.

  When the volatile emission prevention layer is formed of a material other than silicon oxide, even if the volatile emission prevention layer has all the properties described above, The contained molecules or the like may become impurities and contaminate the insulating film (silicon oxide film) inside the trench. Furthermore, when such impurities enter the insulating film inside the trench and contaminate the insulating film, this may cause defects in the insulating film.

  On the other hand, when the volatile matter emission preventing layer is formed of silicon oxide, there is an advantage that there is no fear of contaminating the insulating film because it is the same material as the insulating film (silicon oxide film) inside the trench.

  Further, by forming the volatile matter emission preventing layer with silicon oxide, it is possible to use a modification in which the surface of the silicon compound film already formed in the trench is oxidized to form the volatile matter emission preventing layer. By doing so, it is not necessary to bother to stack a separate silicon oxide film on the silicon compound film, thereby avoiding a significant increase in the number of steps for forming the coated silicon oxide film. There is an advantage that you can.

  However, by adopting this method, the following new problem occurs.

  That is, when a modification that forms a volatile matter emission prevention layer is performed using an oxidation process at a high temperature, which is a conventional method for oxidizing a silicon compound film, low molecular weight volatiles containing silicon atoms are generated from the silicon compound film. As a result, the silicon compound film contracts. Further, the shrinkage of the silicon compound film causes a problem that defects occur in the silicon compound film.

  Therefore, the present inventor has performed the formation of the volatile matter emission preventing layer using a modification (first oxidation treatment) that oxidizes the surface of the silicon compound film at a low temperature, for example, an ozone oxidation treatment at a low temperature. did. This makes it possible to modify the surface of the silicon compound film and form a volatile emission preventing layer while avoiding the release of low molecular weight volatiles containing silicon atoms.

  Further, by forming the volatile emission preventing layer with silicon oxide, silicon oxide exists on the surface of the silicon compound film, and the surface of the silicon compound film is subjected to the oxidation treatment after the formation of the volatile emission preventing layer. Since the silicon compound film is oxidized with the silicon oxide at the starting point as the starting point, the entire silicon compound film is efficiently oxidized.

  Next, the present inventor conducted an experiment to confirm whether emission of volatile matter from the silicon compound film is prevented when the silicon oxide volatile matter release preventing layer is formed. The result of this confirmation experiment will be described with reference to FIG.

  FIG. 1 shows the cumulative release amount of volatiles having a molecular weight of 76 released from the polysilazane film (silicon compound film) as the temperature of the oxidation treatment increases. A curve A in FIG. 1 is a case where a volatile matter emission preventing layer is formed on the surface of the polysilazane film. On the other hand, curve B in FIG. 1 is the case where the volatile matter emission preventing layer was not formed on the surface of the polysilazane film. Note that the curve C in FIG. 1 is the background.

  As shown in FIG. 1, when the temperature of the oxidation treatment is increased to 300 ° C. or higher, the amount of volatiles having a molecular weight of 76 is rapidly increased from the polysilazane film without the volatile matter release preventing layer (see curve B in FIG. 1). ). On the other hand, from the polysilazane film having the volatile matter emission preventing layer, even when the temperature of the oxidation treatment rises, almost no volatile matter having a molecular weight of 76 is emitted (see curve A in FIG. 1). That is, it was confirmed that the formation of a volatile matter emission preventing layer on the surface of the polysilazane film prevents the emission of low molecular weight volatiles containing silicon atoms.

  Furthermore, it was confirmed whether or not the shrinkage of the coated silicon oxide film can be suppressed by forming a silicon oxide volatile matter release preventing layer on the surface of the silicon compound film to prevent the release of volatile matter.

Details are as follows.
Here, the shrinkage of the coated silicon oxide film is measured by comparing the thickness of the polysilazane film (silicon compound film) and then the coated silicon oxide film obtained by high-temperature oxidation treatment, Examined. As an index representing shrinkage, the shrinkage rate, specifically, the difference between the thickness of the polysilazane film and the thickness of the coated silicon oxide film obtained by high-temperature oxidation treatment was divided by the thickness of the polysilazane film. Use things.

  When produced under the same conditions, the shrinkage rate of the film in which the volatile matter emission preventing layer was not formed was 19%. In contrast, the shrinkage rate of the film on which the volatile matter emission preventing layer was formed was only 10%. That is, from this result, it was found that the shrinkage of the coating type silicon oxide film can be suppressed by forming the volatile matter emission preventing layer.

  As described above, the formation of the silicon oxide volatile emission prevention layer on the surface of the silicon compound film prevents the emission of low molecular weight volatiles containing silicon atoms during the high-temperature oxidation treatment. It has become clear that there is an effect of suppressing shrinkage of the coated silicon oxide film.

  However, even when the volatile matter emission preventing layer is formed and the coating type silicon oxide film is formed as described above, film stress is still generated in the coating type silicon oxide film.

  Therefore, in order to further improve the quality of the coated silicon oxide film, the present inventor needs to suppress the generation of film stress and thereby further reduce defects in the coated silicon oxide film. I thought it was.

  The present inventor has thought that the film stress generated in the coated silicon oxide film may be generated during the annealing process (heating process). The details of the film stress generation mechanism of the coating-type silicon oxide film, which the inventor originally considered, are as follows.

  First, it is considered that the following changes have occurred in the coated silicon oxide film during the annealing treatment.

  In the coated silicon oxide film before the annealing treatment, there may be a portion that is not oxidized. Furthermore, the coated silicon oxide film before the annealing treatment has not reached a strong bonding structure. Then, by subjecting such a coated silicon oxide film to an annealing process, this non-oxidized portion is oxidized. At the same time, the coated silicon oxide film changes so as to form a dense and strong bond structure.

  In other words, some of the silicon atoms in the bonded structure of the coated silicon oxide film before the annealing process remain bonded to hydrogen atoms, nitrogen atoms, or the like. Furthermore, the bonding structure of the coated silicon oxide film before annealing is not such that silicon atoms and oxygen atoms are regularly bonded. Then, by performing an annealing process on such a coated silicon oxide film, hydrogen atoms and nitrogen atoms remaining in the bonded structure of the coated silicon oxide film are removed and replaced with oxygen atoms. At the same time, the coated silicon oxide film changes so as to have a regular, dense, and strong bond structure in which each silicon atom is bonded to another silicon atom through an oxygen atom.

  That is, during the annealing process, it is considered that the above two changes occur simultaneously in the coated silicon oxide film.

  During the annealing process, the inventor removed hydrogen atoms and nitrogen atoms remaining in the coating-type silicon oxide film from the coating-type silicon oxide film and replaced them with oxygen atoms to form a dense and strong bonding structure. It was thought that the bond structure was distorted by forming the coated silicon oxide film. Furthermore, the present inventor has thought that film stress may be generated by the distortion of the joint structure.

  Therefore, in order to suppress the generation of the film stress of the coated silicon oxide film, the present inventor has made the coated silicon oxide film dense and strong before the coated silicon oxide film forms a dense and strong bonding structure. We thought that it would be sufficient to remove the hydrogen and nitrogen atoms in the film and replace them with oxygen atoms while avoiding the formation of a simple bond structure. In other words, it was considered that it is only necessary to oxidize the non-oxidized portion in the coated silicon oxide film before the annealing treatment.

  As such a method, the present inventor considered performing an oxidation treatment (third oxidation treatment) at a low temperature, for example, ozone oxidation at a low temperature. This is because the unoxidized portion of the coated silicon oxide film can be oxidized without making the coated silicon oxide film a dense and strong bonding structure.

  The present inventor has confirmed whether or not the generation of the film stress of the coated silicon oxide film is prevented by performing an oxidation treatment (third oxidation treatment) at a low temperature before the annealing treatment. Specifically, the film stress of the coated silicon oxide film was measured by optically measuring the warpage of the semiconductor substrate on which the coated silicon oxide film was formed. The results are as follows.

  A coated silicon oxide film was formed by the method described above. That is, the polysilazane film (silicon compound film) is subjected to high-temperature oxidation treatment at 500 ° C. for 5 minutes in a water vapor atmosphere. Next, annealing treatment was performed at 850 ° C. for 30 minutes in a nitrogen atmosphere to form a coated silicon oxide film. The film stress of the coating type silicon oxide film thus obtained was 115 MPa.

  On the other hand, a coating type silicon oxide film was formed by adding ozone oxidation treatment (third oxidation treatment) at a low temperature before annealing treatment while using the same method. The film stress of the coating type silicon oxide film thus obtained was 88 MPa.

  That is, it was found that the film stress of the finally obtained coated silicon oxide film was reduced by adding an oxidation treatment (third oxidation treatment) at a low temperature.

  Therefore, from this result, it was confirmed that the generation of the film stress of the coating type silicon oxide film is suppressed by adding the low temperature oxidation treatment (third oxidation treatment) before the annealing treatment.

  The present invention has been made based on the unique knowledge of the present inventors as described above.

An embodiment of the present invention will be described below.
Here, as an example, one embodiment of the present invention will be described as a method for manufacturing a NAND flash memory. However, the present invention is not limited to the manufacturing method of the NAND flash memory.

(First embodiment)
FIG. 2 is a schematic plan view (part) of the semiconductor device according to the first embodiment of the present invention. More specifically, it is a schematic plan view (a part) of a NAND flash memory. A schematic plan view of the semiconductor device in the second to fifth embodiments described later is also shown in the same manner as FIG.

  As shown in FIG. 2, in the NAND flash memory according to the first embodiment, a plurality of active areas 101 are formed along the vertical direction of the drawing. Further, the plurality of active regions 101 are arranged at a certain interval in the horizontal direction of the paper surface and are parallel to each other. A plurality of gate electrodes 102 are formed so as to be orthogonal to the plurality of active regions 101 when viewed in plan. A plurality of memory cells 60 are formed at a plurality of portions where the active region 101 and the gate electrode 102 intersect three-dimensionally. In other words, the plurality of memory cells 60 are arranged in a matrix in the NAND flash memory. Further, each pair of memory cells 60 adjacent to each other in the horizontal direction of the paper surface is arranged via an STI (Shallow Trench Isolation) 103 for separating each memory cell 60. The plurality of STIs 103 include a trench (element isolation groove) and an insulating film (coating silicon oxide film) that occupies the trench.

  3 to 9 are schematic process cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. These figures correspond to a cross section taken along the line AA 'in FIG. In addition, schematic process sectional drawing of the manufacturing method of the semiconductor device of the 4th and 5th embodiment demonstrated later is also represented similarly to FIGS.

  A method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS.

  On a semiconductor substrate (silicon substrate) 1, a gate insulating film (SiON film) 2 is 8 nm, a floating gate film (P-doped polycrystalline silicon film) 3 is 80 nm, gate insulation from chemical mechanical polishing (CMP). A CMP stopper film (SiN film) 4 for protecting the film 2, the floating gate film 3, and the like is sequentially laminated to 70 nm. Next, a mask material film (silicon oxide) 5 serving as a reactive ion etching (RIE) mask is applied to the entire surface of the semiconductor substrate 1 so as to cover the CMP stopper film 4 by chemical vapor deposition (CVD). The film is formed by the method. Further, a photoresist film material 6 is applied to the entire surface of the semiconductor substrate 1 by using a spin coating method so as to cover the mask material film 5. Thereby, a photoresist film 16 is formed (see FIG. 3A).

  Next, a desired pattern is formed on the photoresist film 16 by a lithography technique to form a photoresist pattern 26 (see FIG. 3B).

  Using the photoresist pattern 26 on which the pattern is formed as a mask, a pattern is formed on the mask material film 5 using the RIE method. Thereby, the mask material film 5 becomes the hard mask 15 (see FIG. 4A).

  The photoresist pattern 26 is removed by ashing and etching using a mixed solution of sulfuric acid and hydrogen peroxide (see FIG. 4B).

  Thereafter, the CMP stopper film 4, the floating gate film 3, and the gate insulating film 2 are sequentially etched using the hard mask 15 as a mask and using the RIE method. Further, the semiconductor substrate 1 is etched until the etching depth becomes 220 nm with respect to the thickness of the semiconductor substrate 1. As a result, a plurality of trenches (element isolation trenches) 50 extending from the CMP stopper film 4 to the semiconductor substrate 1 are formed. For example, the width of the trench 50 to be formed between a pair of adjacent memory cells 60 is 30 nm, and the width of the trench 50 in the peripheral circuit in which a plurality of control transistors are arranged is 100 nm or more. (See FIG. 5A).

  Thereafter, the silicon compound solution 8 is applied to the entire semiconductor substrate 1 on which the trench 50 is formed.

Specifically, the silicon compound is, for example, polysilazane (polyperhydrosilazane) [— (SiH ₂ NH) n—], hydrogen silsesquiosan (HSQ) [— (HSiO _3/2 ) n—], and the like. Is a silicon compound that is oxidized to silicon oxide (coated silicon oxide). Further, the silicon compound solution 8 is obtained by dissolving such a silicon compound in an organic solvent such as dibutyl ether or xylene.

  Here, as the silicon compound solution 8, a solution in which polyperhydrosilazane having an average molecular weight of 2000 to 6000 is dissolved in dibutyl ether as an organic solvent is used. Therefore, the following description will be made using a polysilazane solution as the silicon compound solution 8.

  The polysilazane solution 8 is applied by spin coating so as to cover the entire surface of the semiconductor substrate 1 and occupy the entire trench 50. By doing so, a polysilazane solution 8 having a film shape with a thickness of about 400 to 600 nm with respect to the upper surface of the hard mask 15 is formed on the semiconductor substrate 1 (FIG. 5B). )reference).

  Subsequently, the polysilazane solution 8 is pre-baked (heat treatment) using a hot plate at 150 ° C. for 3 minutes. Thus, dibutyl ether (solvent) is evaporated from the polysilazane solution 8 present as a film on the semiconductor substrate 1 and in the trench 50, and a polysilazane film (silicone) is formed on the semiconductor substrate 1 and in the trench 50. Compound film) 18 is formed. At this stage, the polysilazane film 18 contains a trace amount of organic solvent, and its composition is in a state close to the composition of the SiN film having a low crystal density (see FIG. 6A).

  Next, the polysilazane film 18 is at a temperature (first temperature) lower than the temperature (second temperature) of the high-temperature oxidation treatment (second oxidation treatment) to be performed later. The surface of the polysilazane film 18 is oxidized and modified (first oxidation treatment) by being exposed to an ozone atmosphere at a temperature of 0 ° C. or lower. That is, the surface of the polysilazane film 18 can pass an oxidant such as oxygen, ozone, water, and impurities such as nitrogen and hydrogen, and a volatile emission preventing layer (silicon oxide film) that cannot pass volatiles including silicon atoms. ) 28. Specifically, a portion of the polysilazane film 18 at a depth of about 40 nm to 50 nm from the surface of the polysilazane film 18 is oxidized and modified to form a volatile matter emission preventing layer (silicon oxide film) 28 (FIG. 6 ( b)).

This modification (first oxidation treatment) is performed, for example, by irradiating the polysilazane film 18 with the excimer UV lamp for several minutes in the air at room temperature. By doing in this way, oxygen contained about 20% in the atmosphere is changed to ozone by UV light. Then, this ozone is used as an oxidizing agent to perform modification that oxidizes the surface of the polysilazane film 18. Further, the polysilazane film can be obtained by heating the entire semiconductor substrate 1 with a hot plate at a temperature of 300 ° C. or lower for 10 minutes to 1 hour while being exposed to ozone (ozone concentration 200 g / m ³ or more). 18 surfaces can be oxidized.

Next, the polysilazane film 18 is oxidized to the inside thereof to form a coating type silicon oxide film (insulating film) 38 integrated with the volatile matter emission preventing layer. Oxidation process). For example, as the high temperature oxidation treatment, heating at 300 to 1000 ° C. is performed in an atmosphere of H ₂ O, O ₂ , N ₂ or the like. As another method, for example, heat treatment is performed in a steam (H ₂ O) atmosphere at 500 ° C. for 5 minutes. Note that conditions such as the temperature of the high-temperature oxidation treatment are determined depending on the desired performance of the element to be manufactured. In this way, a coating type silicon oxide film 38 is formed (see FIG. 7A).

  Next, the coating type silicon oxide film 38 is exposed to an ozone atmosphere at a temperature (third temperature) lower than that of the annealing (heat treatment) to be performed later, specifically, at 300 ° C. or lower. Treatment (third oxidation treatment) is performed. As a result, as described above, the non-oxidized portion of the coated silicon oxide film 38 is oxidized without strengthening the bonding structure of the coated silicon oxide film 38. More specifically, hydrogen and nitrogen remaining in the coated silicon oxide film 38 are removed and replaced with oxygen without strengthening the bonding structure of the coated silicon oxide film 38.

Also in this step, the same method as that used in the formation of the volatile matter emission preventing layer 28 described above can be used. That is, a method of irradiating the application type silicon oxide film 38 with UV light with an excimer UV lamp for several minutes in the atmosphere at room temperature can be used. Alternatively, it can also be performed by heating the entire semiconductor substrate 1 with a hot plate at 300 ° C. or lower for 10 minutes to 1 hour while being exposed to an ozone atmosphere (ozone concentration 200 g / m ³ or more).

  Next, the coated silicon oxide film 38 is annealed (heated) in a nitrogen atmosphere at 850 ° C. for 30 minutes. By doing so, the coated silicon oxide film 38 embedded in the trench 50 has a strong bonding structure.

  Next, using the CMP stopper film 4, a flattening process for flattening the coated silicon oxide film 38 is performed by CMP. At this time, the excess coating type silicon oxide film 38 on the surface of the semiconductor substrate 1, in other words, the portion of the coating type silicon oxide film 38 not embedded in the trench 50 is planarized by the CMP method to be removed. To do. At this time, the hard mask 15 is also removed (see FIG. 7B).

  Further, the coated silicon oxide film 38 embedded in the trench 50 is etched (etched back) by 120 nm along the thickness direction of the semiconductor substrate 1 by using the RIE method. In this way, the upper surface of the coated silicon oxide film 38 embedded in the trench 50 has the thickness of the floating gate film 3 of each memory cell 60 disposed on both sides of the trench 50 so as to sandwich the trench 50. It is located in the middle (see FIG. 8A).

  Next, the CMP stopper film 4 is removed using phosphoric acid heated to 150 ° C. (see FIG. 8B).

  Thereafter, an ONO (silicon oxide film-silicon nitride film-silicon oxide film) film 9 serving as an interelectrode insulating film (IPD) is formed on the upper surface of the coated silicon oxide film 38 and the upper surface of the floating gate film 3 in the memory cell 50. A single layer is laminated so as to cover a part of the side wall. Next, a control gate electrode film (P-doped polycrystalline Si film) 10, a WSi film 11, and a SiN film 12 are sequentially stacked on the ONO film 9. Further, the SiN film 12, the WSi film 11, the control gate electrode film 10, the ONO film 9, and the floating gate film 3 are sequentially processed into a desired shape by using a known lithography technique and RIE method. (See FIG. 9).

  Thereafter, through a process of forming an interlayer insulating film (PMD) and a wiring, a NAND flash memory is finally completed.

  As a modification of the present embodiment, a hot water treatment can be added to improve the electrical characteristics of the coated silicon oxide film. Details are as follows.

Similar to the above-described embodiment, the polysilazane solution 8 is applied to the semiconductor substrate 1, and the polysilazane solution 8 is pre-baked (heat treatment) to form the polysilazane film 18. Further, the polysilazane film 18 is exposed to an ozone atmosphere of 300 ° C. or lower to form a volatile matter emission preventing layer 28 (first oxidation treatment). Next, hot water treatment (details of conditions and the like will be described later) is performed on the polysilazane film 18. By this warm water treatment, water penetrates the polysilazane film 18 through the volatile matter emission preventing layer 28. Thereafter, a high-temperature oxidation process (second oxidation process) at 300 to 1000 ° C. is performed in the presence of an oxidizing agent to form a coating type silicon oxide film 38. Further, similarly to the embodiment described above, the coated silicon oxide film 38 is exposed to an ozone atmosphere of 300 ° C. or lower (third oxidation treatment), and then the coated silicon oxide film 38 is subjected to N _2. Annealing treatment (heating treatment) is performed in an atmosphere. The subsequent steps are the same as those in the embodiment described above.

  Specifically, this hot water treatment is performed by immersing the polysilazane film 18 in pure water maintained at 50 ° C. to 70 ° C. for about several minutes to one hour.

  Furthermore, as another modification of the present embodiment, the oxidation treatment (second oxidation treatment) at 300 to 1000 ° C. in the presence of an oxidizing agent may be performed a plurality of times. Further, when the oxidation treatment is performed a plurality of times as described above, ozone treatment (third oxidation treatment) for exposing the coated silicon oxide film 38 to an ozone atmosphere of 300 ° C. or lower is performed a plurality of times between each oxidation treatment. You can go.

  As described above, according to the first embodiment of the present invention, the shrinkage of the coating type silicon oxide film is prevented, and the generation of the film stress of the coating type silicon oxide film is suppressed, so that the high quality with few defects is obtained. A coating-type silicon oxide insulating film can be obtained.

(Second Embodiment)
As a second embodiment, an impurity diffusion prevention film (silicon oxide film) 7 is formed after the trench (element isolation groove) 50 is formed and before the polysilazane solution 8 is applied to the entire surface of the semiconductor substrate 1. Is. The impurity diffusion preventing film 7 is formed so as to cover the side wall of each memory cell 60 and the side wall of the trench 50, so that a small amount of impurities contained in the coated silicon oxide film 38 can be applied to the coated silicon oxide film 38. From being diffused to the memory cell 60 on both sides of the coated silicon oxide film 38, and the adhesion between the coated silicon oxide film 38 and the side wall of the trench 50 is improved, thereby providing a NAND flash memory. The effect of increasing the mechanical strength of can be obtained.

  As described above, the schematic plan view of the semiconductor device according to the second embodiment is the same as FIG. Note that the description of FIG. 2 is omitted here.

  10 to 14 are schematic process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. These drawings correspond to a cross section of the semiconductor device according to the embodiment of the present invention taken along the line AA ′ in FIG. 2.

  Hereinafter, the second embodiment will be described with reference to FIGS. 10 to 14. Note that description of steps similar to those of the first embodiment is omitted.

  In the same manner as in the first embodiment, a gate insulating film 2, a floating gate film 3, a CMP stopper film 4, a mask material film 5, and a photoresist film 16 are sequentially stacked on the semiconductor substrate 1. To do. Next, a desired pattern is formed on the photoresist film 16 to form a photoresist pattern 26. Further, using the photoresist pattern 26 as a mask, a pattern is formed on the mask material film 5 to form the hard mask 15. Next, the photoresist pattern 26 is removed. Thereafter, the CMP stopper film 4, the floating gate film 3, the gate insulating film 2, and the semiconductor substrate 1 are etched by the RIE method using the hard mask 15 as a mask. Thereby, a plurality of trenches (element isolation grooves) 50 are formed in the semiconductor substrate 1 (see FIG. 10A).

Next, an impurity diffusion preventing film 7 is formed. In detail, silicon oxide is covered with the silane-based gas (dichlorosilane or monosilane) and N ₂ O as raw materials by using the CVD method so as to cover the entire semiconductor substrate 1. Then, it is laminated to a thickness of 10 nm so as to cover the side surface of the CMP stopper film 4, the side surface of the floating gate film 3, the side surface of the gate insulating film 2, and the side wall and bottom of the trench 50 (FIG. 10B). reference).

  Next, a polysilazane solution (silicon compound solution) 8 is applied by the same method as in the first embodiment. At this time, the upper surface of the semiconductor substrate 1 is covered with the polysilazane solution 8 and the inside of the trench 50 is filled with the polysilazane solution 8 (see FIG. 11A).

  Thereafter, a polysilazane film (silicon compound film) 18 is formed by the same method as in the first embodiment as shown in FIG. Further, as shown in FIG. 12A, a volatile matter emission preventing layer 28 is formed (first oxidation treatment). Next, as shown in FIG. 12B, a coating-type silicon oxide film 38 is formed (second oxidation treatment).

  Next, using the same method as in the first embodiment, through the steps shown in FIGS. 13A, 13B, and 14, the NAND flash memory is finally completed.

  As described above, according to the second embodiment of the present invention, similarly to the first embodiment, the shrinkage of the coated silicon oxide film is prevented and the generation of the film stress of the coated silicon oxide film is prevented. Thus, a high-quality coated silicon oxide insulating film with few defects can be obtained. Furthermore, it is possible to prevent a minute amount of impurities contained in the coated silicon oxide film 38 from diffusing into each film provided in the memory cell 60 or the like.

(Third embodiment)
In the first embodiment described above, the modification (first oxidation treatment) for forming the volatile emission preventing layer (silicon oxide film) 28 is performed by pre-baking (heating treatment) the polysilazane solution (silicon compound solution) 8. Had gone after. In the third embodiment, the volatile matter emission preventing layer 28 is formed before the polysilazane solution 8 is pre-baked.

  As described above, even if the order of the steps for forming the volatile portion emission preventing layer 28 is changed, the volatile matter emission preventing layer 28 formed of silicon oxide is volatile containing silicon atoms, as in the first embodiment. Since it has the property of preventing the release of an object, allowing an oxidant such as oxygen and impurities such as nitrogen to pass through, and further allowing the solvent contained in the polysilazane solution 8 to pass therethrough, the same effect as the first embodiment Can be obtained.

  Note that the semiconductor device according to the third embodiment also has the same configuration as the semiconductor device according to the first embodiment described above. As described above, the schematic plan view of the semiconductor device according to the third embodiment is the same as FIG. Here, the description of FIG. 2 is omitted.

  Moreover, schematic process sectional drawing which shows the main manufacturing methods of the semiconductor device of 3rd Embodiment is represented by FIGS. 15-17. These drawings correspond to a cross section of the semiconductor device according to the embodiment of the present invention taken along the line AA ′ in FIG. 2.

  Hereafter, the main manufacturing method of 3rd Embodiment is demonstrated using FIGS. 15-17. Note that description of steps similar to those of the first embodiment is omitted.

  In the same manner as in the first embodiment, a gate insulating film 2, a floating gate film 3, a CMP stopper film 4, a mask material film 5, and a photoresist film 16 are sequentially stacked on the semiconductor substrate 1. To do. Further, a plurality of trenches 50 are formed in the semiconductor substrate 1 (see FIG. 15A).

  Next, a polysilazane solution (silicon compound solution) 8 in which a silicon compound (for example, polysilazane) is dissolved in an organic solvent (for example, dibutyl ether) is formed on the semiconductor substrate 1 and inside the trench (element isolation groove) 50. Apply. In this way, a film-like polysilazane solution 8 is formed on the semiconductor substrate 1 and in the trench 50 (see FIG. 15B).

  Next, this polysilazane solution 8 is exposed to an ozone atmosphere of 300 ° C. or lower to perform modification (first oxidation treatment) that oxidizes the surface of the polysilazane solution 8, and volatiles are formed on the surface of the polysilazane solution 8. A release prevention layer (silicon oxide) 28 is formed (see FIG. 16A). Instead of exposing to an ozone atmosphere, the polysilazane solution 8 may be exposed to an oxygen or water vapor atmosphere.

  Further, pre-baking (heat treatment) is performed on the polysilazane solution 8 using a hot plate at 150 ° C. for 3 minutes. As a result, the organic solvent is evaporated from the film-like polysilazane solution 8 under the volatile emission preventing layer 28 via the volatile emission preventing layer 28, and the semiconductor substrate is formed under the volatile emission preventing layer 28. 1 and a polysilazane film (silicon compound film) 18 are formed on the trench 50 (see FIG. 16B).

  Thereafter, as in the first embodiment, an oxidation process (second oxidation process) for oxidizing the polysilazane film 18 is performed. By doing so, the polysilazane film 18 is oxidized and integrated with the volatile matter emission preventing layer 28 to form a coated silicon oxide film 38 (see FIG. 17).

  Further, since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted. Similar to the first embodiment, the NAND flash memory is finally completed through the steps shown in FIGS. 7A, 7B, 8A, 8B, and 9. FIG.

  As described above, according to the third embodiment of the present invention, similarly to the first embodiment, the shrinkage of the coated silicon oxide film is prevented and the generation of the film stress of the coated silicon oxide film is prevented. Thus, a high-quality coated silicon oxide insulating film with few defects can be obtained.

(Fourth embodiment)
In the embodiment described so far, the volatile matter emission preventing layer (silicon oxide film) 28 is formed by using ozone oxidation as the first oxidation treatment. In the fourth embodiment, the volatile matter emission preventing layer 28 is formed by another method different from the embodiments described so far. More specifically, the surface of the polysilazane film 18 is oxidized by irradiating the polysilazane film (silicon compound film) 18 with oxygen radicals to form a silicon oxide volatile matter emission preventing layer 28 on the surface of the polysilazane film 18. To do.

  The semiconductor device according to the fourth embodiment has the same configuration as the semiconductor device according to the first embodiment described above. As described above, the schematic plan view of the semiconductor device according to the fourth embodiment is the same as FIG. Here, the description of FIG. 2 is omitted.

  Further, as described above, the schematic process cross-sectional view showing the semiconductor device manufacturing method of the fourth embodiment is the same as FIGS. 3 to 9.

  Hereinafter, the fourth embodiment will be described with reference to FIGS. 3 to 9. Note that description of steps similar to those of the first embodiment is omitted.

  In the same manner as in the first embodiment, a gate insulating film 2, a floating gate film 3, a CMP stopper film 4, a mask material film 5, and a photoresist film 16 are sequentially stacked on the semiconductor substrate 1. (See FIG. 3A). Further, through the steps shown in FIGS. 3B to 4B, a plurality of trenches (element isolation grooves) 50 are formed in the semiconductor substrate 1 (see FIG. 5A). Next, through the process shown in FIG. 5B, a polysilazane film (silicon compound film) 18 is formed on the semiconductor substrate 1 and in the trench 50 (see FIG. 6A).

  Next, oxygen radicals are irradiated to the polysilazane film 18. Oxygen radicals can be generated by irradiating a mixed gas of oxygen and argon gas with microwaves. More specifically, the oxygen contained in the mixed gas is preferably 5% or more, and more preferably 25%. In this way, the generated oxygen radical is irradiated to the polysilazane film 18 for 1 minute to perform modification (first oxidation treatment) that oxidizes the surface of the polysilazane film 18. By this modification, a silicon oxide volatile emission preventing layer (silicon oxide film) 28 is formed on the surface of the polysilazane film 18 (see FIG. 6B).

  Further, similarly to the embodiment described so far, a high-temperature oxidation process (second oxidation process) for oxidizing the polysilazane film 18 is performed. By doing so, the polysilazane film 18 is oxidized and integrated with the volatile matter emission preventing layer 28 to become a coated silicon oxide film 38 (see FIG. 7A).

  Since the subsequent steps are the same as those in the first embodiment, description thereof will be omitted. That is, the NAND flash memory is finally completed through the steps shown in FIGS. 7B, 8A, 8B, and 9 by the same method as in the first embodiment.

  Furthermore, as a modification of the fourth embodiment, there is a method of irradiating OH radicals simultaneously with oxygen radicals. By simultaneously irradiating OH radicals, the oxidation of the polysilazane film can be further promoted. Specifically, in the above-described embodiment, the mixed gas for generating oxygen radicals is further mixed with hydrogen gas and irradiated with microwaves to generate OH radicals simultaneously with oxygen radicals. Can do. The polysilazane film 18 is irradiated with oxygen radicals and OH radicals generated in this way for 1 minute. Other steps are the same as those in the above-described embodiment.

  As described above, according to the third embodiment of the present invention, the shrinkage of the coated silicon oxide film is prevented and the film stress of the coated silicon oxide film is prevented as in the other embodiments described so far. By preventing the occurrence of this, it is possible to obtain a high-quality coated silicon oxide insulating film with few defects.

(Fifth embodiment)
In the embodiments described so far, the volatile matter emission preventing layer (silicon oxide film) 28 is formed using ozone oxidation or oxygen radical irradiation as the first oxidation treatment. In the fifth embodiment, the volatile matter emission preventing layer 28 is formed by another method different from the embodiments described so far. More specifically, oxygen ions are injected into the polysilazane film (silicon compound film) 18 to modify the surface of the polysilazane film 18 (first oxidation treatment), thereby forming the volatile matter emission preventing layer 28. To do. The fifth embodiment has the advantage that the thickness of the volatile matter emission preventing layer 28 to be formed can be easily controlled by changing the implantation conditions when oxygen ions are implanted.

  Note that the semiconductor device according to the fifth embodiment also has the same configuration as the semiconductor device according to the first embodiment described above. As described above, the schematic plan view of the semiconductor device according to the fifth embodiment is the same as FIG. Here, the description of FIG. 2 is omitted.

  Furthermore, as described above, the schematic process cross-sectional view showing the semiconductor device manufacturing method of the fifth embodiment is the same as FIGS. 3 to 9. Therefore, the fifth embodiment will be described below with reference to FIGS. Note that description of steps similar to those of the first embodiment is omitted.

  In the same manner as in the first embodiment, a gate insulating film 2, a floating gate film 3, a CMP stopper film 4, a mask material film 5, and a photoresist film 16 are sequentially stacked on the semiconductor substrate 1. (See FIG. 3A). Further, through the steps shown in FIGS. 3B to 4B, trenches (element isolation grooves) 50 are formed in the semiconductor substrate 1 (see FIG. 5A). Next, through the process shown in FIG. 5B, a polysilazane film (silicon compound film) 18 is formed on the semiconductor substrate 1 and in the trench 50 (see FIG. 6A).

Next, oxygen ions are implanted into the polysilazane film 18. The film thickness of the volatile matter emission preventing layer 28 formed on the surface of the polysilazane film 18 can be controlled by the oxygen ion implantation conditions at this time. For example, oxygen ions are implanted into the polysilazane film 18 under conditions of an oxygen ion implantation energy of 10 keV and an oxygen ion implantation amount of 1.0 × 10 ¹⁴ / cm ² . In this way, a modification (first oxidation treatment) is performed to oxidize the surface of the polysilazane film 18, and a silicon oxide volatile emission prevention layer (silicon oxide film) 28 is formed on the surface of the polysilazane film 18. (See FIG. 6B).

  Next, as in the embodiment described so far, a high-temperature oxidation process (second oxidation process) is performed in order to oxidize the entire polysilazane film 18. By performing this treatment, the polysilazane film 18 is oxidized and becomes a coated silicon oxide film 38 integrated with the volatile matter emission preventing layer 28 (see FIG. 7A).

  Further, since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted. Through the steps shown in FIGS. 7B, 8A, 8B, and 9, a NAND flash memory is finally completed.

  As described above, according to the fifth embodiment of the present invention, similarly to the other embodiments described so far, the shrinkage of the coated silicon oxide film is prevented, and the film stress of the coated silicon oxide film is reduced. By preventing the occurrence of this, it is possible to obtain a high-quality coated silicon oxide insulating film with few defects. Furthermore, the thickness of the volatile matter emission preventing layer 28 to be formed can be easily controlled by changing the implantation conditions for implanting oxygen ions.

  In addition, this invention is not limited to said each embodiment, Various forms other than these can be taken.

1 Semiconductor substrate (silicon substrate)
2 Gate insulation film (SiON film)
3 Floating gate film (P-doped polycrystalline silicon film)
4 CMP stopper film (SiN film)
5 Mask material film (silicon oxide film)
6 Photoresist film material 7 Impurity diffusion prevention film (silicon oxide film)
8 Polysilazane solution (silicon compound solution)
9 ONO film (silicon oxide film-silicon nitride film-silicon oxide film)
10 Control gate electrode film (P-doped polycrystalline Si film)
11 WSi film 12 SiN film 16 Photoresist film 15 Hard mask 18 Polysilazane film (silicon compound film)
26 Photoresist pattern 28 Volatile emission preventing layer (silicon oxide)
38 Coating type silicon oxide film (insulating film)
50 trench (element isolation groove)
60 Memory cell 101 Active region 102 Gate electrode 103 STI

Claims (4)

A plurality of memory cells in a semiconductor substrate, forming an element isolation trench between the memory cells adjacent,
An impurity diffusion prevention film is formed in the element isolation trench so as to cover the side surface of each memory cell,
A silicon compound film is formed so as to embed the element isolation groove inside the element isolation groove where the impurity diffusion prevention film is formed ,
By performing oxidation treatment of any one of ozone oxidation, oxygen ion implantation, and oxygen radical irradiation at a first temperature, the surface of the silicon compound film contains silicon atoms while allowing the passage of an oxidant and impurities. Modified to a volatile emission prevention layer through which volatiles cannot pass,
By acid treatment at higher than said first temperature the second temperature, the interior of the device isolation trench, forming a coating type silicon oxide film,
A method for manufacturing a semiconductor device. Forming an isolation groove in a semiconductor substrate;
Applying a silicon compound solution in which a silicon compound is dissolved in a solvent so as to embed the element isolation groove inside the element isolation groove,
By performing oxidation treatment of any one of ozone oxidation, oxygen ion implantation, and oxygen radical irradiation at the first temperature, the surface of the silicon compound solution is allowed to pass through the oxidizing agent, impurities, and the solvent while being allowed to pass through the silicon. It is modified to a volatile emission prevention layer through which volatiles containing atoms cannot pass,
By the heat treatment, the solvent is evaporated through the volatile matter emission preventing layer to form a silicon compound film from the silicon compound solution under the volatile matter emission preventing layer,
By acid treatment at higher than said first temperature the second temperature, the interior of the device isolation trench, forming a coating type silicon oxide film,
A method for manufacturing a semiconductor device.   3. The method of manufacturing a semiconductor device according to claim 1, wherein either the polysilazane film or the HSQ film is formed as the silicon compound film. After forming the coating type silicon oxide film,
Ozone treatment at the third temperature,
Heat-treating the coated silicon oxide film at a temperature higher than the third temperature;
The method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that.

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