JPS6123657B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method of forming integrated circuits.

As is known in the art, semiconductor devices formed on a single crystal body can be isolated from each other by forming isolation grooves. The isolation groove extends from the surface of an epitaxial layer formed on the semiconductor substrate, through the layer, and into the substrate. Air, or preferably an oxide having a dielectric constant lower than that of the crystal in the groove, provides dielectric separation between semiconductor devices. It is sometimes desirable to increase the degree of isolation by forming highly conductive regions having impurities of a conduction type opposite to that of the epitaxial layer of the substrate beneath the bottom wall of the isolation groove. Although various techniques have been proposed for forming such regions, they are either relatively complex, unreliable, or unsuitable for fabricating high-throughput, high-density, low-cost monolithic integrated circuits. It's something that doesn't exist.

According to the invention, a corrosion-resistant mask with windows is placed on the surface of the semiconductor. Separation grooves are etched into the semiconductor by first contacting the portion of the surface exposed by the window with an anisotropic etchant to form a groove with sidewalls that intersect the surface at an acute angle. naughty) The groove formed is
Further etching occurs by contacting an isotropic etchant with the walls of the etched groove exposed by the window. In this case, the isotropic corrosive agent will destroy the semiconductor part under the anti-corrosion mask, so the mask will be located on top of the side walls of the groove, and the bottom wall of the groove will be the window. It will be placed below. When particles are implanted into the semiconductor through the window, the mask shields the sidewalls of the groove from the particles, and the window prevents the particles from implanting into the bottom wall of the groove. enable.

In selected embodiments of the invention, the surface of the semiconductor is oriented parallel to its <100> crystal plane. The anisotropic etchant initially forms the separation trenches with sidewalls substantially parallel to the <111> crystal planes of the semiconductor. Using an anisotropic etchant, a small degree of discontinuity between the plane and the sidewall of the semiconductor forms a separation groove, and this small degree of discontinuity is completed by an isotropic etchant. This facilitates the formation of interconnect leads over the isolation grooves during subsequent metallization steps. The isotropic etchant also removes the portion of the semiconductor beneath the mask so that the mask extends over the sidewalls of the groove and the bottom wall of the groove is exposed by the window, thus contributing to the formation of the isolation groove. Ion implantation of the used corrosion-resistant mask
It can be used as a mask to ensure that ions are implanted into the bottom wall of the separation groove. That is, this process is a self-aligning process that precisely controls the formation of the separation region under the bottom wall of the separation groove. Since the placement of the separation region is precisely controlled, the required depth of the separation groove can be reduced. As a result, the metallization process reduces the depth in forming the interconnect leads. Each of these features, the self-aligning process and the reduced separation groove depth, improve the productivity and cost of the process.

In one embodiment of the invention, after the particles are implanted, a heating step is used to simultaneously oxidize the surface of the semiconductor and drive the transistor base region dopant and the implanted particles further into the semiconductor. By pushing the implanted particles further into the semiconductor, the depth of the grooves can be reduced, thereby improving the surface flatness. The groove depth requirements are best reduced by using this heating step since the implanted particles and base dopant are forced in at the same time.

In another embodiment of the invention, a layer of silicon nitride is used as the layer of the corrosion-resistant mask. The heating step does not oxidize the silicon nitride layer, but the silicon sidewalls and bottom walls of the grooves are oxidized and covered with a layer of silicon dioxide, so that the flatness of the surface is further improved.

The use of an isotropic etchant eliminates the need for corner compensation in the groove forming mask to obtain a nearly square shape in the etched groove.

The foregoing and other features of the invention will become readily apparent from the following description taken in conjunction with the accompanying drawings.

Turning now to FIG. 1, a single crystal semiconductor 10 is shown having a wafer 12 of P-type conductivity silicon having a flat surface 14 oriented parallel to the <100> crystal plane of the wafer 12. . Wafer 1
2, a subcollector region (not shown) of the opposite conductivity, ie N ⁺ type conductivity, may be diffused using photolithography and diffusion processing. wafer 12
An epitaxial layer 18 of N-type conductivity (here between 2.0 and 3.0 .mu.m thick, preferably 2.5 .mu.m thick) is formed on the surface 14 of the substrate in a conventional manner.
The epitaxial layer 18 has a flat surface 20 on the wafer 1.
It is oriented parallel to the <100> crystal plane of 2.
A silicon dioxide layer 22 having a thickness of 1000 to 2000 Å, preferably 1500 Å, is formed on the surface 20 of the epitaxial layer 18 as shown in a conventional manner, in this case by thermal growth, forming a base diffusion mask. To create a window 24, a window 24 is etched into the silicon dioxide layer 22 using conventional photolithography techniques. Note that although only one window 24 is shown, in practice multiple windows may be used to form base regions for other semiconductor devices (not shown) formed on the same wafer 12. is formed in epitaxial layer 18. Additionally, such diffusion is used to form resistors (not shown) as is well known in the art. Although the formation of a single transistor is discussed for simplicity, multiple active and/or passive devices may also be formed in epitaxial layer 18. Referring again to FIG. 1, the epitaxial layer 18 is grown by diffusing a P-type conductive dopant, here boron, with a surface concentration on the order of 10 ²⁰ atoms/cm ³ using conventional diffusion techniques. A base region 26 is formed therein. The base diffusion is performed in a conventional manner, the depth of the base region 26 being 1000-1500 Å thick. (The steps following this relatively shallow pre-positioning of boron atoms push the boron atoms further into epitaxial layer 18 in the manner to be described.) After forming base region 26 as described. , the silicon dioxide layer 22 is removed in a conventional manner. Note that base region 26 is formed by silicon dioxide layer 2.
2 as a mask by implanting boron ions through window 24. Also, if boron ion implantation is used to form base region 26, a photoresist mask may be used in place of the silicon dioxide mask.

Turning now to FIG. 2, a silicon dioxide layer 28, now between 3000 and 8000 Angstroms thick, has been formed on the surface 20 of epitaxial layer 18 as shown.
In this case almost all the silicon dioxide layer 28
The base doping agent is epitaxial layer 1
To prevent significant further indentation into the epitaxial layer 18, a relatively low temperature (ie, below 900° C.) chemical vapor deposition process is used to form the surface 20 of the epitaxial layer 18.

A window 30 is formed in the silicon dioxide layer 28 as shown using conventional photolithography to form an epitaxial layer to form an isolation groove 32 around an active semiconductor device, here a transistor as described above. A portion of surface 20 of 18 is exposed. Additionally, the mask (not shown) used to expose portions of surface 20 during the formation of window 30 is oriented to etch the window along the <110> crystal axis of the silicon wafer. determined. The silicon dioxide layer 28 with the windows 30 thus serves as a corrosion-resistant mask for the formation of the separation grooves 32 mentioned above. In particular, the groove 32 is first exposed to an anisotropic etchant, here an ethylene diamine-pyrocatechin solution, to the surface 2 exposed by the window 30.
0 into the epitaxial layer 18 (and now into a portion of the base region 26, as shown). Alternatively, other anisotropic corrosives may be used, such as saturated aqueous solutions of sodium hydroxide. Such an anisotropic etchant etches the portion of epitaxial layer 18 exposed by window 30, but causes very little etching to the silicon underlying silicon dioxide layer 28. The anisotropic etchant produces grooves 32 having a trapezoidal cross section as shown. Groove 32 has sidewalls parallel to the <111> crystal plane of wafer 12. Such a side wall 3
4 is an acute angle θ with respect to the flat surface 20, here
It forms 54.7°. The width of window 30 is 2.5 here.
It is μm. The etching process continues until the bottom wall 36 of the groove 32 reaches a depth of between 0.3 and 0.8 .mu.m from the surface 20, preferably 0.5 .mu.m.

Please note that anisotropic etching is performed on groove 32.
is stopped when the bottom wall 36 of is in the epitaxial layer. That is, when the groove 32 is etched to a depth of 0.5 μm by the anisotropic corrosive agent, the anisotropic corrosive agent is stopped and the groove 32 is etched by the isotropic corrosive agent (here, in volume ratio, 9HNO ₃ :0.9HF: _3CH3OOH )
is etched by contacting the silicon exposed by window 30. As shown in FIG. 3, the isotropic etchant reaches all of the boundaries of the grooves 32 etched by the anisotropic etchant and further reaches the epitaxial layer 18 (and base region 26). Also note that such an isotropic etchant will attack the silicon beneath the silicon dioxide layer 28, but not the sidewall 3.
The acute angle that 4 makes with surface 20 is substantially maintained. That is, the trapezoidal cross-section of groove 32 initially formed by the anisotropic etchant is substantially retained by the isotropic etchant. (The grooves 32, as originally created by the anisotropic etchant, are shown in dashed lines in FIG. 3.) Etching the silicon beneath the silicon dioxide layer 28 results in the formation of sidewalls, as shown. 3
A layer 28 forms a roof or protection over window 3 and
2 to expose the bottom wall 36. That is, the silicon dioxide layer 28 forms a mask extending over the sidewalls of the resulting groove 32 and the bottom wall 36 of the groove 32 is located below the window 30. Note that the isotropic etch step is performed before the bottom wall 36 of the groove 32 passes through the surface 14 of the wafer 12 (where the bottom wall 36 is 0.6 mm from the surface 14).
~0.8 μm) is stopped. That is, it is desirable that all grooves 32 be formed in the epitaxial layer 18. (It should be noted that although the depth of groove 32 is formed by an etching process and this process can be relatively accurately controlled, it is important to note that the depth of groove 32 is The process used cannot be controlled very precisely.Therefore, if the epitaxial layer 18 is somewhat thinner than its nominal design depth, the bottom wall 3
6 may be formed on the surface 14 and slightly in the wafer 12. ) As will become apparent later, forming a relatively shallow groove 32 facilitates the metallization process, since the depth of the interconnect leads passing over the groove 32 formed by this metallization process is also relatively shallow. It's because it's over.

To increase the degree of separation provided by the relatively shallow grooves 32, a doping agent of P-type conductivity, here in the form of B ⁺ F ₂ primary ions, is added by a conventional ion implantation process. Boron ions are implanted into bottom wall 36 to form region 38. Ion implantation is illustrated in FIG. 3 by arrows (not labeled). The silicon dioxide layer 28 is
In addition to serving as a corrosion-resistant mask during the formation of groove 32, it also serves as a mask for the ion implantation process, as window 30 directs the ions to bottom wall 36.
This is because the layer 28 protects the sidewall 34 from the ions while allowing the ions to pass through. The use of B ⁺ F ₂ ions offers the advantage of using readily available high ion flux equipment that performs implants at relatively small depths of entry (i.e., 1000-1800 Å) in relatively short times. Implant energy levels of 10-18 KeV are generally required to obtain such small penetration depths with straight boron ions. Performing short-duration implants at such energy levels with straight boron ions requires relatively high ion flow levels and equipment capable of operating at such low energy levels; Flow operated devices are generally not as readily available as high energy level high ion flow devices. B ⁺ F ₂ primary ions are now implanted at an energy level of 70 KeV to keep the depth of penetration into the silicon dioxide layer below 1500 Å. Because of this small depth of penetration, i.e. less than 1500 Å, the protruding or protective portion of the silicon dioxide layer 28, which has a nominal thickness of 6000 Å, can be removed even if the edges of that layer 28 forming the window 30 are etched. Even a slight taper to a thickness of 2000 Å (as indicated by dotted line 40 in FIG. 3) as a result of the process provides sufficient protection against ion implantation into the sidewalls 34. Here, the amount of ion implantation is 10 ¹² to 10 ¹⁵ ions/
cm ² range, preferably 10 ¹³ ions/cm ² .

The semiconductor 10 thus formed is then
In order to remove (anneal) damage to the silicon crystal structure caused by the ion implantation process, it is
It is heated for about 20 minutes at a temperature in the range of 900° to 1000°C. Next, here we use hydrofluoric acid (HF)
The solution removes the silicon dioxide layer 28. There, the semiconductor 10 is placed in an oxidizing atmosphere of a humid oxygen stream at a temperature of 1000
4, a new silicon dioxide layer 42 is formed over the entire surface 20, including the sidewalls 34 and bottom walls 36 of the grooves 32, as shown in FIG. Here, silicon dioxide 42 grows to a thickness of 3000 Å.
Because semiconductor 10 has been processed at temperatures in the range of 900 DEG C. to 1000 DEG C., the boron dopant in base region 26 and the boron ions in the region below bottom wall 36, region 38, are forced deeper into semiconductor 10. In particular, the boron doping agent in the base region 26 is 0.6 to 0.8 μm away from the surface 20.
The implanted boron is likewise forced further into the semiconductor 10 to form an isolation region 38 from the bottom wall 36 into at least the wafer 12 as shown. spread. It should therefore be noted that the heating step used to drive the boron dopant in base region 26 and the ion implanted boron in region 38 further into semiconductor 10 to the desired depth is performed simultaneously as previously described. A new silicon dioxide layer 42 is formed. If desired, the thickness of layer 42 may be uniformly increased by adding silicon dioxide using conventional chemical vapor deposition techniques.

A silicon dioxide layer 42 is formed using conventional photolithography.
Openings 48, 50, and 51 (FIG. 5) are formed in the holes 48, 50, and 51 (FIG. 5), followed by a P-type conductive base contact region 56 and an N-type conductive emitter region 52, as illustrated, by well-known diffusion or ion implantation techniques. and an N-type conductive collector region 54.

Metal leads 58b are then formed in ohmic contact with the base, emitter and collector regions 56, 52, 54, respectively, over portions of the silicon dioxide layer 42 through windows formed in the silicon dioxide layer 42 by conventional metal metallization processes. , 58e, 58c are formed. The resulting structure is shown in FIG.

The formation of an active semiconductor device, here a transistor, has been described, and etched grooves 32
Ion implantation region 38 and oxide layer 42 formed in
and separating said semiconductor device from other active or passive semiconductor devices (not shown) formed in the epitaxial layer 18 outside the area bounded by the groove 32. It should be noted that Junction isolation is provided in the semiconductor device by the formation of ion implanted regions 38 and etched oxidized grooves 3.
2 provides insulating layer separation to the device described above.
The formation of the ion implant region 38 provides dielectric isolation compared to the depth that would be required in the groove if the ion implant region were not formed to provide additional junction isolation as described above. This reduces the required depth of the groove. Although the self-alignment process described above used a corrosion-resistant mask to form grooves 32, it also serves as an ion implant mask, which ensures accurate placement of ion implant regions 38. The first use of an anisotropic corrosive agent was to form the groove 32 on the side wall 3 of this.
4 and the surface of the epitaxial layer 18 with relatively small discontinuities. The shallow depth of the grooves 32 and the small discontinuities between the surface of the epitaxial layer 18 and the sidewalls 34 of the grooves 32 facilitate the metallization process, reducing process costs and increasing process productivity. will improve. Using a single heating step to simultaneously oxidize the surface of the semiconductor and drive the doping impurities in base regions 26 and 38 further into semiconductor 10 to their desired depth also improves process productivity. .

In another embodiment of the invention, after forming base region 26 and removing silicon dioxide layer 22 as described in connection with FIG.
A silicon dioxide layer 80, here 500 Å thick, is formed on base region 26 and surface 20 of epitaxial layer 18, as shown in FIG. 500Å
A layer 82 of silicon nitride (Si ₃ N ₄ ) with a thickness of ~2000 Å, preferably 2000 Å, is deposited on silicon dioxide by any conventional method, here chemical vapor deposition (or sputtering can also be used). Formed on layer 80. Silicon nitride layer 82 forms epitaxial layer 18
A relatively thin silicon dioxide layer 80 is placed between the epitaxial layer 18 and the silicon nitride layer 82 to prevent internal stresses from developing in the silicon nitride layer 82 that would typically occur if formed directly thereon.
is formed.

After forming relatively thin silicon dioxide layer 80 and silicon nitride layer 82, windows 30' are formed in these layers 80, 82 using conventional photolithography techniques. As is well known in the art, the silicon dioxide mask is first etched by using a solution of hydrofluoric acid (HF) and contacting it with the portions of the silicon dioxide layer 80 to be etched; Unwanted portions of silicon nitride layer 82 are removed using a hot phosphoric acid solution. Or
Unwanted portions of silicon nitride layer 82 are removed by conventional RF (radio frequency) plasma etching and photoresist. It can also be removed by a mask. First an anisotropic etchant and then an isotropic etchant are used to form grooves 3 in the silicon body 10 as described in connection with FIG.
2' is formed. That is, the window 30' exposes a portion of the surface 20 of the epitaxial layer 18 in which an isolation groove 32' is formed surrounding the active semiconductor device, here a transistor. Therefore, silicon dioxide layer 80 and nitride layer 8
2 serves as a corrosion-resistant mask for the formation of the separation groove 32'. That is, groove 32' initially introduces the anisotropic etchant into surface 2 exposed by window 30'.
epitaxial layer 1 by contacting with
8 to obtain a groove 32' having a trapezoidal cross-section with side walls 34' parallel to the <111> crystal planes of the wafer 12. Sidewall 34' thereby forms an acute angle with surface 20. Grooves 32' are then further etched by contacting an isotropic etchant with the silicon exposed by window 30'. The isotropic etchant etches under the oxide, nitride layers 80, 82 so that these layers 80, 82 form a roof or protection on the sidewall 34' and the window 32' is etched under the bottom wall 3.
6' should be exposed. The latter etching step is performed as described in connection with FIG.
It will be stopped before passing 4.

As explained in connection with Figure 3, shallow groove 3
To increase the degree of isolation provided by 2', a doping agent of P-type conductive particles is implanted in region 38' below bottom wall 36', as shown in FIG. The oxide, nitride layers 80, 82 serve as anti-corrosion masks during the formation of the grooves 30', as well as masks for the ion implantation process, since the layers 80, 82 are located on the sidewalls 34. ′ is protected from ions and the window 30′ is connected to the bottom wall 36′.
This is to make it possible to send ions to.
Further, the ion implantation process and the groove forming process are self-aligning processes, and the region 38' is aligned with the bottom wall 3 of the groove 32'.
6'.

After such an ion implantation step, silicon dioxide layer 80 and silicon nitride layer 82 are removed using a hydrofluoric acid (HF) solution to remove oxide layer 80 and nitride layer 82 in a conventional manner. The semiconductor 10 is stripped using a suitable hot phosphoric acid solution.
Also, to remove the oxide and nitride layers 80 and 82, LFE Corporation of Waltham, Massachusetts, USA, is used.
Plasma engravers, such as those manufactured by Waltham, Massatbusetts, may also be used. After removing said layers 80, 82, surface 2 is removed as described in connection with FIG.
0 is oxidized. This oxidation step forces the boron dopant into the base region 26 and the B ⁺ F ₂ ions further into the semiconductor 10 to the desired depth while simultaneously forming a new silicon dioxide layer. This new silicon dioxide layer is used in connection with the formation of the base, emitter and collector regions and subsequent metallization as described in connection with FIGS. 5 and 6.

In yet another embodiment of the invention, after the formation of epitaxial layer 18, a relatively thin silicon dioxide layer 80', here 500 Å thick, is deposited using conventional techniques as shown in FIG. is formed in the epitaxial layer 18. Silicon nitride layer 82'
is formed on the silicon dioxide layer 80' as described in connection with FIG. said layer 80',
A window 30'' is formed in 82' and a separation groove 3
2'' are formed in the epitaxial layer using the anisotropic-isotropic etching process described in connection with FIGS. The self-alignment process described in connection with FIG. 8 is used to implant the semiconductor 10 located below the bottom wall 36''. The semiconductor 10 is placed in an oxidizing atmosphere. Since the side walls 34'' and the bottom wall 36'' of the groove 32'' are made of silicon, they are oxidized in the atmosphere to form a silicon dioxide layer 90 on their surfaces. However, the silicon nitride layer 82' is not oxidized. , the groove 32'' is a layer 90 of silicon dioxide as shown in FIG.
covered with a thickness of m. During this heating step, the boron dopant region 38'' in the base region 26
The ions implanted into the semiconductor 10 are simultaneously forced into the semiconductor 10 as described in connection with FIG.

After silicon dioxide layer 90 is formed to cover trench 32'', silicon nitride layer 82' is removed using hot phosphoric acid. A solution of hydrofluoric acid (HF) is then contacted with semiconductor 10. Remove 250 Å of layer 80'. Note that since the protruding edges 95 of layer 80' are removed from the top and bottom by the acid, removal of 250 Å of layer 80' removes the protruding edges 95. Department
95 will be removed by 500 Å. The top surface of the semiconductor 10 is then covered in a conventional manner, here by a chemical vapor method, with a layer 92 of silicon dioxide, here 0.3-1.0 .mu.m thick. silicon dioxide layer 92
is base contact as explained in connection with FIG.
Emitter contact and collector contact areas 56, 52,
It is used as a mask during the formation of 54. Metal leads 58b, 58e, and 58c are formed as described in connection with FIG. I would like to note that
Since layer 92 is selectively formed in groove 32'',
The surface on which the leads passing through the grooves are formed is flatter than the surface shown in FIG.

Having thus far described preferred embodiments of the invention, it will be obvious that other embodiments of the invention may be used. for example,
The side walls are etched using the etching process.
Arrange the masks in an appropriate direction and press <331> or <113
>It may also be formed at other acute angles to the surface of the semiconductor by forming it parallel to the crystal plane.
Therefore, the invention should not be limited to the embodiments disclosed herein.

[Brief explanation of the drawing]

1-6 are diagrammatic cross-sectional views of a portion of an integrated circuit at various stages of formation to illustrate the formation method of an embodiment of the present invention. 7 and 8 are diagrammatic cross-sectional views of a portion of an integrated circuit at various stages of formation to illustrate a method of forming another embodiment of the present invention. 9 and 10 are diagrammatic cross-sectional views of a portion of an integrated circuit at various stages of formation to illustrate a method of forming yet another embodiment of the present invention. In these drawings, 10 is a semiconductor, 12 is a wafer, 14 is a surface, 18 is an epitaxial layer,
20 is a surface, 22 is a silicon dioxide layer, 24 is a window,
26 is a base region, 28 is a silicon dioxide layer, 30
32 is a window, 32 is an isolation groove, 34 is a side wall, 36 is a bottom wall, 38 is an ion implantation region (isolation region), and 42 is a silicon dioxide layer.

Claims (1)

[Claims] 1. (a) A corrosion-resistant mask having a window is disposed on the surface of a semiconductor substrate, and (b) an anisotropic corrosive agent is brought into contact with the surface portion exposed by the window. etching a groove in the substrate; (c) contacting the walls of the groove with an isotropic corrosive agent; and (d) implanting an impurity into the bottom of the groove using the corrosion-resistant mask as an ion implantation mask. (e) A method for forming an integrated circuit comprising steps in which the groove and the impurity implantation region are used as isolation regions. 2. (a) placing a corrosion-resistant mask with a window on the surface of a semiconductor substrate; (b) contacting an anisotropic corrosive agent with the portion of the surface exposed by the window so as to intersect the surface at an acute angle; forming a groove with side surfaces and etching a portion of the semiconductor substrate under the corrosion-resistant mask by contacting the walls of the formed groove with an isotropic etchant such that the mask covers the side portions of the groove; etching a groove extending beyond the groove, the bottom of the groove being disposed below the window, and the sides of the groove intersecting the surface at an acute angle; (c) using the corrosion-resistant mask as a mask for ion implantation; (d) using the groove and the impurity implanted region as a separation region. 3. The method of claim 2, wherein the corrosion-resistant mask is made of a non-oxidizable material, and when heating the surface of the semiconductor substrate and the corrosion-resistant mask, only the side and bottom surfaces of the grooves are oxidized. . 4 The etching step is <111>, <331>,
3. The method of claim 2, wherein the sides of the groove are formed parallel to a crystal plane of the substrate selected from the group consisting of <113> and <113> crystal planes.