JPS58121677A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield of a semiconductor device by converting a thin silicon oxidized film into a glass layer without removing the thin silicon oxidized film and forming a diffused region in a semiconductor substrate through the glass layer, thereby preventing the improper part from occurring due to an underetching part. CONSTITUTION:After silicon wirings 4 and an electrode 5 are formed, an impurity is immediately diffused at a high temperature without removing the thin silicon oxidized film 5. A thin silicon oxidized film 3 is converted into a glass layer 11 by setting the temperature of diffusing the impurity to a temperature higher than 900 deg.C, the impurity is diffused through the layer 11 into a silicon semiconductor substrate 1, and a source region 6 and a drain region 7 are formed with the silicon gate 5 as a mask. A silicon oxidized film 8 is then formed, as shown in Fig. 2B, by thermally oxidized or vapor phase growing method on the overall surface without removing the layer 11, a contacting hole is further opened, and aluminum wirings 9 are then performed, thereby forming a transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION Jin's invention relates to a semiconductor device having an element including a diffusion region, such as a transistor.

In the conventional diffusion technology for manufacturing semiconductor devices made of silicon semiconductors, before the thermal diffusion process, either all the thin silicon oxide film formed in the previous process is removed or a highly concentrated impurity glass layer is removed. They were either using it and spreading it. The latter method is technically more difficult than the former method because it involves vapor phase growth technology. Therefore, the former is generally used. However, with recent technology that uses polycrystalline silicon as wiring, for example in silicon gate insulated gate field effect transistors, it is possible to mask the silicon gate by forming the polycrystalline silicon gate in advance and then diffusing the source and drain regions. The mask alignment process can be omitted, and elements can be formed with high density. However, the lower side of the peripheral edge of the polycrystalline silicon formed during the removal of the oxide film before the source and drain diffusion is subject to so-called underetching, which has become an important problem. To explain this with reference to FIG. 1, as shown in FIG. 1A, a silicon semiconductor substrate l
A thick silicon oxide film 2 is provided thereon, a portion of which is selectively removed, and a thin silicon oxide M3 is formed in the removed portion. Furthermore, a crystalline silicon layer is grown over the entire surface, and a portion of it is selectively left to serve as wiring 4 and electrode 5. Thereafter, as shown in FIG. 1B, oxide film etching is performed to remove thin oxide film 3 using polycrystalline silicon layer 5 as a mask to form openings for source region 6 and drain region 7. At this time, the area below the periphery of the gate electrode 50 is also etched to form an under-etched region 10, and the thick oxide film 2 is also etched thinly to form an under-etched region 10 in a portion under the wiring 4. Next, impurity diffusion is performed to form a source region 6 and a drain region 7, and at the same time, polycrystalline silicon interconnection 4 and electrode 5, which have undergone impurity diffusion, are formed. Thereafter, the impurity glass layer is removed and a vapor phase grown silicon oxide film 8 is grown as shown in FIG. do. In this manufacturing method, the silicon gate 5 is used as a mask for source and drain diffusion.
This has the advantage that the mutual positions of the source region 6 and the drain region 7 can be exactly as designed. However, since no silicon oxide film is present in the under-etched portion IO, electrical short circuits between the polycrystalline silicon 5 and the source region 6 and drain region 7 are likely to occur.

In view of the above points, the present invention converts the thin silicon oxide film formed on the semiconductor substrate into a glass layer without removing the thin silicon oxide film, and forms a diffusion region on the semiconductor substrate through the glass layer. . When a silicon electrode and a dosing layer are formed on the thin silicon oxide film in this way, impurity diffusion can be performed using this as a mask, and since the thin silicon oxide film is not removed, under-etching is avoided. There are no defects caused by parts, and the yield is high.

Next, referring to FIG. 2, an example of a semiconductor device according to the present invention will be described in the case where it is applied to a device corresponding to the conventional device shown in FIG.

The steps up to the formation of the silicon wiring 4 and electrodes 5 described with reference to FIG. 1AK are the same as in the conventional method. After forming the silicon wiring and electrodes, in the present invention, impurity diffusion is immediately performed at high temperature without removing the thin silicon oxide film 5. Note that in order to reduce the resistance of the source and drain regions, the thickness of the thin silicon oxide film 3 is preferably 2000 Å or less.

By setting the impurity diffusion temperature to 900° C. or higher, the thin silicon oxide film 3 is converted into a glass layer 11 within two hours as shown in FIG. It is diffused into the substrate 1, and a source region 6 and a drain region 7 are formed using the silicon gate 5 as a mask. Without removing the impurity glass layer 11 formed at this time, the silicon oxide film 8 is then thermally oxidized or vapor-phase grown.
is formed over the entire surface as shown in FIG. 2B, contact holes are further opened, and then aluminum wiring 9 is formed to form a transistor.

According to the present invention described above, since the thin silicon oxide film 3 is not etched, no under-etched portion 10 is generated.In addition, the gate electrode 5 and the silicon wiring 4 are surrounded by the dense glass layer 11, and the bottle water etc. There is no electrical short circuit with wiring or source/drain regions.
Therefore, the yield is good. In the above, thin silicon oxide IM! Although the step of converting 3 into glass and the step of diffusing impurities through the glass are continuous, each step may be clearly separated.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an example of a conventional device manufacturing method, and FIG. 2 is a sectional view showing a semiconductor device according to the present invention according to an example of the manufacturing method. 1: Silicon semiconductor substrate, 3: Thin silicon oxide film, 6
, 7: Source and drain regions as diffusion regions, 1 impurity glass layer. Figure 1++1ノ)i;',':'l'! 7+ has no sad history)
1st No. 2 6/1 58.2.24 Director General of the Patent Office 1, Indication of the Case 1981 轡认语 No. i, t
ziu No. 2, Title of the invention: Semiconductor device 3, Relationship with the person making the amendment: Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent: 1 Amendment Date of order: January 25, 1981 (shipment date) Specification and drawing 7, Description of amendments and engraving of drawings

Claims (1)

[Claims] In a semiconductor device having a thick silicon oxide film provided on the whole surface of a semiconductor region and a silicon gate type field effect transistor in contact with the thick silicon oxide MKa,
A polycrystalline silicon wiring layer is provided on the thick silicon oxide film, and the surface of this wiring layer, the silicon gate, source region, and drain region of the transistor, and the surface of the thick silicon oxide film are covered with a glass layer. A semiconductor device characterized in that the glass layer is covered with a glass layer and an insulating film that is thicker than the glass layer is provided on the glass layer.