JPS5885529A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5885529A JPS5885529A JP18476781A JP18476781A JPS5885529A JP S5885529 A JPS5885529 A JP S5885529A JP 18476781 A JP18476781 A JP 18476781A JP 18476781 A JP18476781 A JP 18476781A JP S5885529 A JPS5885529 A JP S5885529A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- mask
- layers
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に下部導電層
と上部電極の接続用コンタクト開孔との間に2段構造電
極窓を形成する半導体集積回路装置の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor integrated circuit device in which a two-stage electrode window is formed between a lower conductive layer and a contact hole for connecting an upper electrode. .
第1図(a)乃至第1図(e)は従来の半導体基板のコ
ンタクト開孔方法を順次水している断面図である。FIGS. 1(a) to 1(e) are cross-sectional views sequentially illustrating a conventional method for forming contact holes in a semiconductor substrate.
この製造方法は第1図(a)に示すように、P型の導電
型を有するシリコン基板1の一主表面上に熱酸化法によ
シ酸化シリコン膜2を形成し、次にこの酸化シリコン膜
2を通して、イオン注入法によりシリコン基板1と反対
導電型を与える不純物をシリコン基板の主表面に導入し
て拡散層領域3を形成する。次に二酸化シリコン膜2−
ヒに気相成長法により、層間絶縁膜4を形成する。次に
第1図(b)に示すように、この層間絶縁膜4上にフォ
トレジスト膜5で、所定のパターンを形成し、その後湿
式でエツチングして層間絶縁膜4を、第1図(C)の様
に、所定の残膜までサイドエッチさせる。次に、フォト
レジスト膜5をマスクとして残りの層間絶縁膜4を異方
性プラズマエツチング装置でエッチングして、第1図(
d)の断面図に示した構造を得る。As shown in FIG. 1(a), this manufacturing method involves forming a silicon oxide film 2 by a thermal oxidation method on one main surface of a silicon substrate 1 having a P-type conductivity, and then An impurity having a conductivity type opposite to that of the silicon substrate 1 is introduced into the main surface of the silicon substrate through the film 2 by ion implantation to form a diffusion layer region 3. Next, silicon dioxide film 2-
First, an interlayer insulating film 4 is formed by vapor phase epitaxy. Next, as shown in FIG. 1(b), a predetermined pattern is formed using a photoresist film 5 on this interlayer insulating film 4, and then wet etching is performed to form the interlayer insulating film 4 as shown in FIG. ), perform side etching until a predetermined remaining film is reached. Next, using the photoresist film 5 as a mask, the remaining interlayer insulating film 4 is etched using an anisotropic plasma etching device, as shown in FIG.
The structure shown in the cross-sectional view d) is obtained.
次に、フォトレジスト膜5を除去後、高温雰囲気中で熱
処理して開孔後の層間絶縁膜4をタラしくなめらかにし
)、その後その上にアルミニュム電極を形成する。第1
図(elのように形成されたアルミニーム断線窓の構造
では、開孔部の層間絶縁膜4の傾斜が急勾配のため、そ
の部分でのアルミニーム電極6,61 間の断線が起き
易くなり、集積回路装置としての機能が失われてしまう
ことがある。Next, after removing the photoresist film 5, heat treatment is performed in a high temperature atmosphere to make the interlayer insulating film 4 evenly smooth after the opening), and then an aluminum electrode is formed thereon. 1st
In the structure of the aluminum disconnection window formed as shown in Figure (el), since the slope of the interlayer insulating film 4 at the opening is steep, disconnection between the aluminum electrodes 6 and 61 is likely to occur at that part. , the function as an integrated circuit device may be lost.
本発明の目的は、前述したような特にアルミニーム断線
の影響を少なくした半導体装置の製造方法を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the influence of aluminum wire breakage as described above is particularly reduced.
本発明は、−導電型の半導体領域上に順次第1及び第2
の絶縁膜を形成する工程と、前記第2の絶縁膜上に第1
の孔を有するフォトレジスト膜を形成する工程と、前記
フォトレジスト膜をマスクとして前記第2の絶縁膜に前
記第1の孔よりも大きい径を有する第2の孔を形成する
工程と、前記第2の絶縁膜をマスクとして前記第1の絶
縁膜に所定の深さの四部を形成する工程と、前記フォト
レジスト膜をマスクとして前記第1の絶縁膜の前記凹部
内に部分的に開孔を形成する工程と、少なくとも前記開
孔内に電極を形成する工程とを含む半導体装置の製造方
法にある。In the present invention, first and second
forming an insulating film on the second insulating film; and forming a first insulating film on the second insulating film.
forming a second hole having a diameter larger than the first hole in the second insulating film using the photoresist film as a mask; forming four portions of a predetermined depth in the first insulating film using the second insulating film as a mask; and partially forming an opening in the recess of the first insulating film using the photoresist film as a mask. The method of manufacturing a semiconductor device includes a step of forming an electrode, and a step of forming at least an electrode within the opening.
本発明の製造方法に従えば、電極窓の層間絶縁膜を2段
構造にすることによって、コンタクト部の傾斜を緩やか
にし、アルミニュム電極の断線の影響を少なく出来ると
いう効果が得られる。According to the manufacturing method of the present invention, by forming the interlayer insulating film of the electrode window into a two-stage structure, the inclination of the contact portion is made gentler, and the effect of disconnection of the aluminum electrode can be reduced.
次に本発明を図面を用いて詳細に説明する。第2図(a
)乃至第2図(e)は本発明の実施例を適用した半導体
基板の断面図である。Next, the present invention will be explained in detail using the drawings. Figure 2 (a
) to FIG. 2(e) are cross-sectional views of a semiconductor substrate to which an embodiment of the present invention is applied.
1ず第2図(a)で、P型巣結晶シリコン基板lの一生
表面上に熱酸化法による二酸化シリコン膜2を形成する
。次VC1二酸化シリコン膜2全通してイオン注入法に
よりシリコン基板1と反対導電型を与える不純物をシリ
コン基板の王宍面に導入して拡散層領域3を形)1ν、
する。次に、二酸化シリコン暎2上に気相成長法により
層間絶縁膜4を形成する。次に、第1の孔を有するフォ
トレジスト膜8をマスクとして層間絶縁膜4に対して選
択的にフォトレジストの第1の孔よりも広い径となるよ
うにサイドエッチさせる(第2図(b))だめの絶縁膜
7(ここでは、プラズマ気相成長法によるプラズマ窒化
膜を用いる)を層間絶縁膜4上に形成させる。このプラ
ズマ窒化膜7を、フォトレジスト8をマスクとして、等
方性プラズマエツチング装置で、第2図(b)のように
、選択的にサイドエツチングさせて第2の孔を設ける。1. First, as shown in FIG. 2(a), a silicon dioxide film 2 is formed on the surface of a P-type nested crystalline silicon substrate 1 by thermal oxidation. Next, an impurity that gives a conductivity type opposite to that of the silicon substrate 1 is introduced into the surface of the silicon substrate by ion implantation through the entire VC1 silicon dioxide film 2 to form a diffusion layer region 3)1ν,
do. Next, an interlayer insulating film 4 is formed on the silicon dioxide layer 2 by vapor phase growth. Next, using the photoresist film 8 having the first hole as a mask, the interlayer insulating film 4 is selectively side-etched so that the diameter becomes wider than the first hole in the photoresist (see FIG. 2(b). )) A second insulating film 7 (here, a plasma nitride film formed by plasma vapor deposition method is used) is formed on the interlayer insulating film 4. This plasma nitride film 7 is selectively side-etched using an isotropic plasma etching apparatus using the photoresist 8 as a mask, as shown in FIG. 2(b), to form second holes.
次に、サイドエツチングしたプラズマ窒化膜7をマスク
として、層間絶縁膜4をもとの膜厚の1/3以下まで湿
式でエツチングして第2図(C)のように、残膜4′
を形成する。即ち四部を設ける。次に、フォトレジス
ト8をマスクとして第2図(C)の残膜4′ の部分
並びにその直下の二酸化シリコン層2を異方性プラズマ
エツチング装置でエツチングして、第、2図(d)のよ
うな断面構造を形成する。こうして開孔を設ける。この
ようにして、層間絶縁膜の残膜4I の凹部の略平担
な底面を残すようないわゆる2段構造が出来る。次に、
上記マスクとしたフォトレジ−5=
スト8およびプラズマ窒化膜7を除去する。次に第2図
(e)に示すように高温雰囲気中で熱処理して開孔後の
層間絶縁膜をタラして(なめらかにして)その後導電配
線層を通常の方法で設ける。Next, using the side-etched plasma nitride film 7 as a mask, the interlayer insulating film 4 is wet-etched to 1/3 or less of the original film thickness, and the remaining film 4' is etched as shown in FIG. 2(C).
form. That is, there are four parts. Next, using the photoresist 8 as a mask, the remaining film 4' portion shown in FIG. 2(C) and the silicon dioxide layer 2 immediately below it are etched using an anisotropic plasma etching apparatus, and the remaining film 4' shown in FIG. 2(d) is etched using an anisotropic plasma etching apparatus. Form a cross-sectional structure like this. In this way, an opening is provided. In this way, a so-called two-stage structure is formed in which a substantially flat bottom surface of the recessed portion of the remaining film 4I of the interlayer insulating film remains. next,
The photoresist 5 as the mask 8 and the plasma nitride film 7 are removed. Next, as shown in FIG. 2(e), the interlayer insulating film after opening is smoothed (smoothed) by heat treatment in a high-temperature atmosphere, and then a conductive wiring layer is provided by a conventional method.
即ち、本実施例は、−導電型を有する半導体基板の一生
表面に第1の絶縁膜を被着する工程と、前記第1の絶縁
膜を通して前記−導電型と反対の導電型を与える不純物
を導入する工程と、前記第1の絶縁膜上に第2の絶縁膜
を破着する工程と、前記第2の絶縁膜上に第3の絶縁膜
を破着する工程(以上第2図(a)に相箔)と、前記第
3の絶縁e莫に開孔を設けるだめの孔を有するフォトレ
ジストパターンを被着する工程と、前記フォトレジスト
パターンをマスクとして前記第3の絶縁膜を選択的に前
記孔よりも広くサイドエッチして前記開孔を設ける工程
(第2図(b)に相当)と、前記第3の絶縁膜をマスク
として前記第2の絶縁、漢を選択的にもとの膜厚の1/
3以下捷でエツチングする工程(第2図(C)に相当)
と、前記フォトレジストパターンをマスクとして前記第
2の絶縁膜の選択的=6− 。That is, the present embodiment includes a step of depositing a first insulating film on the entire surface of a semiconductor substrate having a -conductivity type, and an impurity that provides a conductivity type opposite to the -conductivity type through the first insulating film. a step of rupturing a second insulating film on the first insulating film, and a step of rupturing a third insulating film on the second insulating film (see FIG. 2(a)). ), a step of depositing a photoresist pattern having holes for forming holes in the third insulating film, and selectively forming the third insulating film using the photoresist pattern as a mask. forming the opening by side-etching the hole to be wider than the hole (corresponding to FIG. 2(b)); and selectively forming the second insulating layer using the third insulating film as a mask. 1/ of the film thickness of
Etching process with 3 or less blades (corresponding to Figure 2 (C))
and selectively forming the second insulating film using the photoresist pattern as a mask.
に残された薄い部分をエツチングする工程(第2図(d
)に相当)と、前記第3の絶縁膜等を除去して電極を設
ける工程(第2図(e)に相当)とを含む。The process of etching the thin part left behind (see Figure 2 (d)
)) and a step of removing the third insulating film etc. to provide an electrode (corresponding to FIG. 2(e)).
特に前記第3の絶縁膜は窒化シリコン膜で形成されるこ
とが好ましい。In particular, it is preferable that the third insulating film is formed of a silicon nitride film.
このように、本発明によれば、下部4−を層と上部電極
の接続用コンタクトの開孔部との間に、2段構造電極窓
を形成することにより、コンタクト部のアルミニュム断
線を少なくすることができる。As described above, according to the present invention, a two-stage electrode window is formed between the lower layer 4- and the opening of the connection contact of the upper electrode, thereby reducing aluminum disconnection at the contact portion. be able to.
本発明は一実施例として、サイドエッチ絶縁膜をプラズ
マ窒化膜としたが、このかわりに多結晶シリコン膜等の
場合についても同様の効果がある。In one embodiment of the present invention, a plasma nitride film is used as the side-etched insulating film, but the same effect can be obtained by using a polycrystalline silicon film instead.
又、本発明けNチャンネルMO8集積回路装置の実施例
について説明したが、種々の半導体集積回路装置に適用
できる。Further, although the embodiment of the N-channel MO8 integrated circuit device according to the present invention has been described, the present invention can be applied to various semiconductor integrated circuit devices.
第1図(a)乃至第1図(e)は従来の半導体基板の製
造方法を順次示す断面図、第2図(a)乃至第2図fe
)け本発明の実施例のNチーン不ル型シリコンMO8集
積回路装置の製造方法を順次示す断面図である。
面図において、1・・・・・・P型巣結晶シリコン基板
、2・・・・・・二酸化シリコン膜、3・・・・・・不
純物拡散領域、4・・・・・・層間絶縁膜、41 ・
・・・・・層間絶縁膜の残膜、5.8・・・・・・フォ
トレジスト膜、6.6’、9・・・・・・アルミニュム
電極、7・・・・・・プラズマ窒化膜。 −井ZブFIGS. 1(a) to 1(e) are cross-sectional views sequentially showing a conventional method of manufacturing a semiconductor substrate, and FIGS. 2(a) to 2(e)
) are cross-sectional views sequentially illustrating a method of manufacturing an N-chain non-circular silicon MO8 integrated circuit device according to an embodiment of the present invention; In the plan view, 1... P-type nest crystal silicon substrate, 2... Silicon dioxide film, 3... Impurity diffusion region, 4... Interlayer insulating film. ,41・
... Remaining film of interlayer insulating film, 5.8 ... Photoresist film, 6.6', 9 ... Aluminum electrode, 7 ... Plasma nitride film . -I Zbu
Claims (1)
形成する工程と、前記第2の絶縁膜上に第1の孔を有す
るフォトレジスト膜を形成する工程と、前記フォトレジ
スト膜をマスクとして前記第2の絶縁膜に前記第1の孔
よりも大きい径を有する第2の孔を形成する工程と、前
記第2の絶縁膜をマスクとして前記第1の絶縁膜に所定
の深さの凹部を形成する工程と、前記フォトレジスト膜
をマスクとして前記第1の絶縁膜の前記凹部内に部分的
に開孔を形成する工程と、少なくとも前記開孔内に電極
を形成する工程とを含む半導体装置の製造方法。a step of sequentially forming a box 1 and a second insulating film on a semiconductor region of one conductivity type; a step of forming a photoresist film having a first hole on the second insulating film; and a step of forming a photoresist film having a first hole on the second insulating film. forming a second hole having a larger diameter than the first hole in the second insulating film using the mask as a mask; and forming a second hole in the first insulating film to a predetermined depth using the second insulating film as a mask. a step of forming an opening in the recess of the first insulating film using the photoresist film as a mask; and a step of forming an electrode in at least the opening. A method for manufacturing a semiconductor device including:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18476781A JPS5885529A (en) | 1981-11-18 | 1981-11-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18476781A JPS5885529A (en) | 1981-11-18 | 1981-11-18 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5885529A true JPS5885529A (en) | 1983-05-21 |
Family
ID=16158963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18476781A Pending JPS5885529A (en) | 1981-11-18 | 1981-11-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5885529A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63308956A (en) * | 1987-06-11 | 1988-12-16 | Nec Corp | Manufacture of semiconductor device |
CN115210154A (en) * | 2020-03-12 | 2022-10-18 | 大和制衡株式会社 | Sealing structure and metering device with same |
-
1981
- 1981-11-18 JP JP18476781A patent/JPS5885529A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63308956A (en) * | 1987-06-11 | 1988-12-16 | Nec Corp | Manufacture of semiconductor device |
CN115210154A (en) * | 2020-03-12 | 2022-10-18 | 大和制衡株式会社 | Sealing structure and metering device with same |
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