JP2794565B2 - Manufacturing method of groove type capacitor - Google Patents
Manufacturing method of groove type capacitorInfo
- Publication number
- JP2794565B2 JP2794565B2 JP62206740A JP20674087A JP2794565B2 JP 2794565 B2 JP2794565 B2 JP 2794565B2 JP 62206740 A JP62206740 A JP 62206740A JP 20674087 A JP20674087 A JP 20674087A JP 2794565 B2 JP2794565 B2 JP 2794565B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- silicon
- oxide film
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000003990 capacitor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、MOS形集積回路の一要素である溝形キャパ
シタの製造方法に関するものである。
（従来の技術）
従来、溝形キャパシタの製造方法は第２図に示すよう
な工程で行なわれていた。
まず、第２図（Ａ）に示したように、溝２を形成した
シリコン基板１上に、第２図（Ｂ）に示すように、酸化
シリコン膜３を成長させる。次に、第２図（Ｃ）のよう
に、この酸化シリコン膜３を除去することにより、溝形
成の際に溝２の内壁に生じた損傷部を除去する。その
後、第２図（Ｄ）に示したように、溝の内壁を含むシリ
コン基板１上にキャパシタ用の誘電体膜４を形成し、次
いでその誘電体膜４の上にキャパシタの一方の電極とな
る導電層５を形成する。以上の工程を経て溝形キャパシ
タが完成する。
（発明が解決しようとする問題点）
上記従来例の工程において、第２図（Ｂ）に示す酸化
シリコン膜３の形成は1000℃以下の低温で行なわれる
が、これは酸化温度を1100℃程度の高温にすると拡散領
域の不純物が再分布を起こすためである。しかし、溝の
内壁の損傷部を除去する工程を900℃〜1000℃程度の低
温で行なうと、溝の開口縁部2a付近の酸化シリコン膜中
にストレスが生ずるため、開口縁部2aが鋭角的に尖るホ
ーン現象が生じ、この部分のキャパシタ誘電体膜には電
界が集中してキャパシタの耐圧が劣化するという不都合
が生じる。さらに酸化膜形成方法として水蒸気酸化法を
用いると前記ホーン現象が顕著に現われるため、溝内壁
の損傷部を除去するための酸化工程には乾燥酸素による
酸化法が採用される。そこで所望の膜厚を得るために長
時間を要し、900℃〜1000℃の低温にもかかわらず拡散
領域の不純物の再分布が起こるという問題があった。
本発明は、不純物の再分布を最小限におさえながら溝
の開口縁部に丸みをもたせた微細なキャパシタを実現す
ることができる溝形キャパシタの製造方法を提供するこ
とを目的とするものである。
（問題点を解決するための手段）
上記目的を達成するために、本発明は、溝を有するシ
リコン基板上に膜厚が400Å程度の薄い第１の酸化シリ
コン膜と窒化シリコン膜から成る積層膜を形成した後、
溝の内壁部以外の前記窒化シリコン膜と第１の酸化シリ
コン膜を選択的に除去する工程と、前記溝を含むシリコ
ン基板を温度1000℃以下の水蒸気雰囲気中で酸化して溝
の内壁部以外のシリコン基板上に膜厚が1000〜2000Å程
度の比較的厚い第２の酸化シリコン膜を形成する工程
と、前記窒化シリコン膜と前記第１及び第２の酸化シリ
コン膜を除去する工程と、前記溝の内壁を含むシリコン
基板上にキャパシタ用の誘電体膜を形成する工程と、前
記誘電体膜上にキャパシタ用の一方の電極となる導電層
を形成する工程とからなるものである。
（作 用）
この製造方法によれば、第１の酸化シリコン膜を比較
的薄く、従って、短時間で形成し、かつ第２の酸化シリ
コン膜を1000℃以下の水蒸気雰囲気中で酸化して形成す
るので、拡散領域の不純物の再分布を最小限に抑えつ
つ、溝の開口縁部に丸みを持たせることができる。
（実施例）
以下、本発明の溝形キャパシタの製造方法の一実施例
を、第１図の工程順の断面図を参照して説明する。
まず、第１図（Ａ）に示したように、深さ４μm,開口
部１×３μm2の溝を有するシリコン基板１の上に、第１
の酸化シリコン膜６を400Å、窒化シリコン膜７を800Å
順次成長させて積層膜を形成する。
次に、図示しないフォトレジストを1.5μｍの厚さに
塗布した後、エッチバックを行ない平坦化を行なう。そ
の後溝内壁部以外の窒化シリコン膜７をドライエッチン
グ法により選択的に除去し、さらに酸化シリコン膜６を
緩衝弗素で除去した後、溝内部のレジストをプラズマ灰
化装置によ除去する｛第１図（Ｂ）｝。
次に前記積層膜をマスクとして950℃水蒸気雰囲気中
で選択酸化を行ない、膜厚1000〜2000Åの厚さの第２の
酸化シリコン膜８を形成する｛第１図（Ｃ）｝。このと
き、窒化シリコン膜７をマスクとして酸化しているた
め、溝の開口縁部付近の酸化膜は厚くなる。
この後、窒化シリコン膜７を熱リン酸で除去し、さら
に酸化シリコン膜6,8を緩衝弗酸で除去する｛第１図
（Ｄ）｝。この結果、溝の開口縁部2aは丸みをおびた形
状になる。
次に、溝２を含むシリコン基板１上に50〜150Åの厚
さの酸化シリコン膜を形成してキャパシタ用の誘電体膜
９とした後、キャパシタの一方の電極となる導電層10と
して多結晶シリコン膜を形成する｛第１図（Ｅ）｝。
尚、キャパシタの他方の電極はシリコン基板１である。
（発明の効果）
以上説明したように、本発明によれば、シリコン基板
に形成された溝の開口縁部に丸みをもたせることがで
き、その結果、微細でかつ高耐圧の溝形キャパシタを形
成することができる。Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a trench capacitor which is one element of a MOS integrated circuit. (Prior Art) Conventionally, a method of manufacturing a grooved capacitor has been performed in steps as shown in FIG. First, as shown in FIG. 2 (A), a silicon oxide film 3 is grown on the silicon substrate 1 on which the groove 2 has been formed, as shown in FIG. 2 (B). Next, as shown in FIG. 2 (C), by removing the silicon oxide film 3, a damaged portion generated on the inner wall of the groove 2 at the time of forming the groove is removed. Thereafter, as shown in FIG. 2 (D), a dielectric film 4 for the capacitor is formed on the silicon substrate 1 including the inner wall of the groove, and then one electrode of the capacitor is formed on the dielectric film 4. The conductive layer 5 is formed. Through the above steps, a trench capacitor is completed. (Problems to be Solved by the Invention) In the above-described conventional process, the formation of the silicon oxide film 3 shown in FIG. 2B is performed at a low temperature of 1000 ° C. or less. This is because if the temperature is increased, impurities in the diffusion region redistribute. However, if the step of removing the damaged portion of the inner wall of the groove is performed at a low temperature of about 900 ° C. to 1000 ° C., stress occurs in the silicon oxide film near the opening edge 2a of the groove, so that the opening edge 2a is sharp. A sharp horn phenomenon occurs, causing an inconvenience that an electric field is concentrated on the capacitor dielectric film in this portion and the withstand voltage of the capacitor deteriorates. Further, when the steam oxidation method is used as an oxide film forming method, the horn phenomenon is conspicuously manifested. Therefore, an oxidation method using dry oxygen is employed in an oxidation step for removing a damaged portion of the inner wall of the groove. Therefore, there is a problem that it takes a long time to obtain a desired film thickness, and redistribution of impurities in the diffusion region occurs despite the low temperature of 900 ° C. to 1000 ° C. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a trench capacitor which can realize a fine capacitor having a rounded opening edge portion while minimizing the redistribution of impurities. . (Means for Solving the Problems) In order to achieve the above object, the present invention provides a laminated film comprising a thin first silicon oxide film and a silicon nitride film having a thickness of about 400 ° on a silicon substrate having a groove. After forming
Selectively removing the silicon nitride film and the first silicon oxide film other than the inner wall portion of the groove, and oxidizing the silicon substrate including the groove in a water vapor atmosphere at a temperature of 1000 ° C. or less, excluding the inner wall portion of the groove. Forming a relatively thick second silicon oxide film having a thickness of about 1000 to 2000 ° on the silicon substrate, removing the silicon nitride film and the first and second silicon oxide films, The method comprises the steps of forming a dielectric film for a capacitor on a silicon substrate including the inner wall of a groove, and forming a conductive layer serving as one electrode for a capacitor on the dielectric film. (Operation) According to this manufacturing method, the first silicon oxide film is formed to be relatively thin, so that it is formed in a short time, and the second silicon oxide film is oxidized in a water vapor atmosphere at 1000 ° C. or lower. Therefore, it is possible to make the opening edge of the groove round while minimizing the redistribution of impurities in the diffusion region. (Embodiment) Hereinafter, an embodiment of a method of manufacturing a grooved capacitor according to the present invention will be described with reference to sectional views in the order of steps shown in FIG. First, as shown in FIG. 1 (A), a first substrate was formed on a silicon substrate 1 having a groove having a depth of 4 μm and an opening of 1 × 3 μm 2 .
400 mm of silicon oxide film 6 and 800 mm of silicon nitride film 7
The layers are sequentially grown to form a laminated film. Next, after a photoresist (not shown) is applied to a thickness of 1.5 μm, etch back is performed to perform flattening. Thereafter, the silicon nitride film 7 other than the inner wall of the groove is selectively removed by dry etching, the silicon oxide film 6 is further removed by buffer fluorine, and the resist inside the groove is removed by a plasma ashing apparatus. Figure (B)｝. Next, selective oxidation is performed in a 950 ° C. water vapor atmosphere using the laminated film as a mask to form a second silicon oxide film 8 having a thickness of 1000 to 2000 Å (FIG. 1C). At this time, since the silicon nitride film 7 is used as a mask for oxidation, the oxide film near the opening edge of the groove becomes thick. Thereafter, the silicon nitride film 7 is removed with hot phosphoric acid, and the silicon oxide films 6, 8 are further removed with buffered hydrofluoric acid (FIG. 1 (D)). As a result, the opening edge 2a of the groove has a rounded shape. Next, a silicon oxide film having a thickness of 50 to 150 ° is formed on the silicon substrate 1 including the groove 2 to form a dielectric film 9 for a capacitor. Forming a silicon film (FIG. 1E).
The other electrode of the capacitor is the silicon substrate 1. (Effect of the Invention) As described above, according to the present invention, the opening edge of the groove formed in the silicon substrate can be rounded, and as a result, a fine and high withstand voltage grooved capacitor is formed. can do.
【図面の簡単な説明】
第１図は、本発明の一実施例による溝形キャパシタの製
造方法を示す工程順の断面図、第２図は、従来の溝形キ
ャパシタの製造方法を示す工程順断面図である。
１……シリコン基板、２……溝、2a……溝の開口縁部、
6,8……酸化シリコン膜、７……窒化シリコン膜、９…
…誘電体膜、10……導電層。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a method of manufacturing a grooved capacitor according to an embodiment of the present invention in a process order, and FIG. 2 is a process order showing a conventional method of manufacturing a grooved capacitor. It is sectional drawing. 1 ... silicon substrate, 2 ... groove, 2a ... groove opening edge,
6, 8 ... silicon oxide film, 7 ... silicon nitride film, 9 ...
... dielectric film, 10 ... conductive layer.
Claims (1)
シリコン膜と窒化シリコン膜から成る積層膜を形成した
後、溝の内壁部以外の前記窒化シリコン膜と第１の酸化
シリコン膜を選択的に除去する工程と、前記溝を含むシ
リコン基板を水蒸気雰囲気中で酸化して溝の内壁部以外
のシリコン基板上に膜厚が比較的厚い第２の酸化シリコ
ン膜を形成する工程と、前記窒化シリコン膜と前記第１
及び第２の酸化シリコン膜を除去する工程と、前記溝の
内壁を含むシリコン基板上にキャパシタ用の誘電体膜を
形成する工程と、前記誘電体膜上にキャパシタ用の一方
の電極となる導電層を形成する工程とからなることを特
徴とする溝形キャパシタの製造方法。(57) [Claims] After forming a laminated film including a thin first silicon oxide film and a silicon nitride film on a silicon substrate having a groove, the silicon nitride film and the first silicon oxide film other than the inner wall portion of the groove are selectively formed. Forming a second silicon oxide film having a relatively large thickness on the silicon substrate other than the inner wall of the groove by oxidizing the silicon substrate including the groove in a water vapor atmosphere; Silicon film and the first
Removing the second silicon oxide film; forming a capacitor dielectric film on the silicon substrate including the inner wall of the trench; and forming a conductive film on the dielectric film to be one electrode for the capacitor. Forming a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206740A JP2794565B2 (en) | 1987-08-20 | 1987-08-20 | Manufacturing method of groove type capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206740A JP2794565B2 (en) | 1987-08-20 | 1987-08-20 | Manufacturing method of groove type capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6449251A JPS6449251A (en) | 1989-02-23 |
| JP2794565B2 true JP2794565B2 (en) | 1998-09-10 |
Family
ID=16528317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62206740A Expired - Fee Related JP2794565B2 (en) | 1987-08-20 | 1987-08-20 | Manufacturing method of groove type capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2794565B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6482701B1 (en) | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007144199A (en) * | 2006-12-18 | 2007-06-14 | Atsugi Color Genzosho:Kk | Sleep-time snore preventing device |
-
1987
- 1987-08-20 JP JP62206740A patent/JP2794565B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482701B1 (en) | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US7354829B2 (en) | 2000-01-14 | 2008-04-08 | Denso Corporation | Trench-gate transistor with ono gate dielectric and fabrication process therefor |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6449251A (en) | 1989-02-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |