JPS63308956A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent disconnection in a metallic interconnecting layer due to difference of levels, by performing a two-step etching process for forming an opening for Schottky barrier diode in a phosphorus-containing glass film, such that the glass film is isotropically etched until the thickness thereof is halved approximately in the first step and then the rest is etched anisotropically in the second step. CONSTITUTION:A semiconductor substrate 1 of one conductivity type is provided with a well 2 of the opposite conductivity type on a principal face thereof. A field oxide film 4 is formed selectively on the surface of the well 2 so as to isolate an element forming region from a contact region, and a first insulating film 3 is provided on the surface of the well 2 surrounded by the field oxide film 4. Then, a phosphorus- containing glass layer 8 is deposited all over the field oxide film 4 and the first insulating film 3. The phorophorus-containing glass layer 8 located on the element forming region is etched isotropically until its thickness is reduced to about a half. Subsequently, the rest of the phosphorus-containing glass layer 8 is removed by anisotropic etching to form an opening having a crateriform cross section. The first insulating film 3 exposed on the element forming region is removed by isotropic etching. In this manner, disconnection of a metallic interconnecting layer can be prevented effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a Schottky barrier diode circuit in an integrated circuit.

[Conventional technology]

Recently, with the development of applications such as IC cards, methods of supplying IC operating power to LSI chips and chips without directly connecting an external direct current source to an external DC source have been extensively studied.

For example, there is a method of rectifying AC power using a built-in diode bridge in a 5V silicon gate open O8 type LSI, which is advantageous for high integration and multifunctionality.

In this case, low forward rising voltage and steep reverse characteristics are required as diode characteristics with good rectification efficiency.

Therefore, Schottky barrier diode (SBD)
5Bi) has attracted attention, and a manufacturing technology has become necessary to add a 5Bi) circuit to a silicon game FMO8 type LSI.

FIGS. 2(a) to 2(d) are semiconductor chips shown in the order of steps to explain an example of a conventional method for manufacturing a semiconductor device.

FIG.

As shown in FIG. 2(a), phosphorus ions are implanted into the surface of a p-type semiconductor substrate 1, heat treated in nitrogen gas at a high temperature of 1200°C to form an n-well 2, and contacts are formed using the well-known LOCO8 technique. A field oxide film 4 with a thickness of about 1 μm is formed to partition the region and the SBD formation region, and a first oxide film with a thickness of about 20 nm is formed on the surface of the n-well 2 quadrupled on this field oxide film 4. A film 3 is formed.

Next, arsenic ions are implanted at an accelerating voltage of 70 keV and a dose of 1.0×1016/crA to form an n-well diffusion layer 5 that serves as an n-well power supply, and boron ions are implanted into the SBD formation region at an accelerating voltage of 50 keV and a dose of 1.0×1016/crA. Amount 1.0×10
A p-swelling diffusion layer 6 with a low impurity concentration and a p-domain diffusion layer 7 with a high impurity concentration are formed.

Next, a borophosphosilicate glass (NPSO) layer 8 with a thickness of about 1.2 μm is deposited on the entire surface by the CVD method, and then a BPSG film 8 is formed by steam treatment at about 900°C.
Flatten the surface of the stepped portion.

As shown in FIG. 2(b), in order to connect the n+i failure layer 5, etc., a contact opening 9' is formed by anisotropic etching in the contact forming region of the BPSG layer 8. As shown in FIG.

Next, a thin polycrystalline silicon layer 13 is grown over the entire surface.

As shown in FIG. 2(C)V, after removing the long crystal silicon layer 13 of the SBD formation region, isotropic etching is performed using a hydrofluoric acid solution so that the bottom portion is approximately half of the p+ dec-shaped diffusion layer. A dish-shaped SBD aperture 15 is formed to expose the SBD.

As shown in FIG. 2(d), aluminum is deposited on the entire surface of the semiconductor chip to form metal wiring layers 12 and 12', and then aluminum-silicon alloy treatment is performed in hydrogen gas to form a gold 14 wiring layer. A Schottky barrier junction 19 is formed between 12 and n-well 2.

FIG. 3 is a plan view corresponding to FIG. 2(d).

2 (di corresponds to the AA' line cross-sectional view of the semiconductor chip in FIG. 3. The metal wiring layer 12 is
The SG film 8 is deposited along the slope of the end of the opening, and has a constricted portion 17 where the thickness partially decreases above the corner portion 16 .

The reverse breakdown voltage of the SBD is determined by the junction between the p-decade diffusion layer 7, the p-swell diffusion layer 6, and the row well 2, and the p-swell diffusion layer 6 is not necessary in the SBD for low breakdown voltage.

Here, the reason why anisotropic dry etching is not used to form the opening 15 for SBD is that if anisotropic etching is performed, then heat treatment is required to smooth the edges of the opening. This may cause the corners to sag inward like an eave, causing the fingers to sag.

This is because the layer growth of the metal wiring layer becomes more critical, and if high-temperature heat treatment or oxidation treatment is not performed after dry etching, the surface of the n-well 2 in the SBD formation region will remain damaged and the remaining silicon will remain. This is because there is a problem that the reverse leakage current of the SBD increases.

[Problem that the invention seeks to solve]

In the conventional semiconductor device manufacturing method described above, when forming the 5iJD opening in the phosphorus-containing glass layer, the corner 16 is formed at the peripheral edge using only isotropic etching. There was a problem in that a wide constriction 17 was formed in the metal wiring layer, and one-stage breakage was likely to occur.

Furthermore, since the p-type diffusion layer is made large due to side etching by isotropic etching, there is a problem in that it is difficult to miniaturize the structure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that has a highly reliable metal wiring layer that does not cause disconnection and that can be miniaturized.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes: (A) forming a well of an opposite conductivity type on one main surface of a semiconductor substrate of one conductivity type, and selectively dividing the surface of the well into an element formation region and a contact portion; forming a field oxide film and forming a first insulating film on the surface of the well surrounded by the field oxide film; (B) coating the entire surface of the field oxide film and the first insulating film with phosphorus-containing glass; (C) isotropically etching the phosphorus-containing glass layer on the element formation region until its thickness is reduced to about half, and then anisotropically etching the remaining phosphorus-containing glass layer; (I) removing the first insulating film exposed on the element formation region by isotropic etching; a step of oxidizing the surface of the well of the opposite conductivity type exposed on the formation region with dry oxygen gas to form a second insulating film; middle) heat-treating the phosphorus-containing glass layer in nitrogen gas and reflowing; and (Q) a step of isotropically etching and removing a second insulating film on the surface of the element forming region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

The method for manufacturing the semiconductor chip shown in FIG. 1(a) is the same as the method for manufacturing the conventional semiconductor chip shown in FIG. 2(a).

As shown in FIG. 1(b), the contact formation area and 8B
Corresponding to the D forming region, the blanking BpsGJJ8 is isotropically etched to approximately half the film thickness to form an arcuate cross section.

Next, the remaining BPSG film 8 is anisotropically etched using, for example, a CF4-N2 gas, and the remaining thin oxide film 3 is isotropically etched using a 79-acid solution to form a cross-section. An SBD aperture part 9 and a contact aperture part 9' having a distorted part 10 are formed at the same time.

As shown in FIG. 1C, dry oxidation is performed in a high-temperature furnace at, for example, about 900° C. to form a second oxide film 12 in the 8BD opening and the contact opening 9'.

Subsequently, heat treatment is performed in nitrogen gas at the same temperature to smoothen the peripheral edges of the openings 9 and 9'.

Next, as shown in FIG. 1(d), the oxide film 12 on the SBD aperture 9 is left and the other contact aperture 9' is
After removing the second oxide film 12 by isotropic etching, a film thickness of 5 Qnm is deposited on the entire surface by low pressure CVD.
A polycrystalline silicon layer 13 of about 100 mL is grown.

Next, as shown in FIG. 1(e), the oxide film 12 of the SBD aperture 92 and the polycrystalline silicon layer 13 on the surface of the BPSG film 8 around it are treated with a CF4-O2 gas. Remove by directional etching.

Next, as shown in FIG. 1(f), the SBD aperture part 9
After removing the oxide film 12 of No. 2 by isotropic etching,
Aluminum is deposited to a thickness of about 1.0 μm over the entire surface by sputtering.

Next, the predetermined resist is patterned using the well-known IJ printing technique, for example, CC44-CF.
4-Aluminum is anisotropically dry etched using a BC43 gas to form metal interconnections 14 and 14'.

Next, an alloying process is performed in an atmosphere of N2-1-(2) at a temperature of about 450 DEG C. to form a symmetry barrier junction 19 between the aluminum layer and the n-well.

In this example, the reason why anisotropic dry etching can be used to form the SBD aperture part 9 is that the BPSG film 8 This is because the gentle slope 11 is formed by the heat treatment, so no constriction occurs in the metal wiring layer 14VC, and there is no risk of breakage.

Furthermore, even if the surface of the n-well 2 is damaged due to excessive dry etching, the damaged layer will be transferred to the second oxide film 12 by dry oxidation at about 900° C. and heat treatment in nitrogen gas in the post-process. , that part is removed by machining or ching.

〔Effect of the invention〕

As explained above, the present invention provides phosphorus-containing glass film with SB.
By using a two-step etching process to form the opening for D, isotropic for about half and then anisotropic for the remaining part, the cross section of the periphery of the opening becomes a cup-shaped part. The upper half of the step is made very smooth by subsequent heat treatment, so the metal wiring layer is highly reliable and has no step breakage, and can be made finer than by isotropic etching alone8.
There is an effect that a semiconductor device having a BD circuit can be manufactured.

[Brief explanation of drawings]

1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps to explain an example of a conventional method for manufacturing a semiconductor device;
The figure is a plan view corresponding to FIG. 2(d). 1... Semiconductor substrate, 2... N well,
3...First oxide film, 4...Field oxide film, 5...N+ type formation diffused layer 6...
・P- type scattering layer, 7..."p+ type scattering layer 8...
...BPSG film, 9... SBD aperture opening section'... Contact opening section, 10... Cup-shaped section, 11... Inclined part, 12...2nd
oxide film. Agent Patent Attorney Uchihara Whistle 1! Figure 7

Claims (1)

[Claims] (A) A well of an opposite conductivity type is formed on one principal surface of a semiconductor substrate of one conductivity type, and a field oxide film is selectively formed on the surface of the well to partition an element formation region and a contact portion. forming a first insulating film on the surface of the well surrounded by the field oxide film; (B) depositing a phosphorus-containing glass layer on the entire surface of the field oxide film and the first insulating film; Step (C) Isotropically etching the phosphorus-containing glass layer on the element forming region until its thickness is reduced to about half, and then removing the remaining phosphorus-containing glass layer by anisotropic etching to form a cross-section. (D) isotropically etching and removing the first insulating film exposed on the element formation region; (E) exposed on the element formation region; The surface of the well of the opposite conductivity type was oxidized with dry oxygen gas to form a second well.
(F) heat-treating the phosphorus-containing glass layer in nitrogen gas and reflowing it to smooth the periphery of the opening; (G) forming an insulating film on the surface of the element formation region; 2. A method for manufacturing a semiconductor device, comprising: removing the insulating film by isotropic etching.