JPS583272A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a semiconductor device of SOIS structure in a high performance by forming an insulating film on the bottom of a recess region formed on a semiconductor substrate, covering the overall surface of the substrate with a polycrystalline Si film, scanning and melting it with a laser beam and single crystallizing the Si film. CONSTITUTION:A nitrided Si film is formed on a single crystal Si substrate 11, and is etched to form a recess region 14 and a raised region 15. An SiO2 film 16 is formed by selectively thermal oxidation to be lower than the upper surface of the region 15 on the region 15. An Si3N4 film 12 is dissolved and removed on the region 15, and a P type polycrystaline Si layer 18 is deposited on the overall surface including the film 16. A laser beam 19 is scanned to sequentially melt and quench the layer 18, thereby single crytallizing to the bottom and forming a single crystal Si layer 21, and an MOSFET 25 is formed thereat. In this manner, the performance and the yield of the semiconductor device of SOIS structure can be improved.

Description

[Detailed description of the invention] The present invention is based on 5OIL (Silicon On Insul).
The present invention relates to a method of manufacturing a semiconductor device having a structure (ating8ubstrate), and particularly to a method of forming a single crystal silicon layer on an insulating film.

By completely separating the elements and reducing the capacitance between the substrate and the elements, the 808 (8i1ic) achieves faster element operation and lower power consumption.
There is a semiconductor device having an on (Jn 5apphire) structure. However, the cost of the sapphire substrate for the 808#s semiconductor device is 5 to 6 times that of the silicon substrate.
It is thought that 1IIci1 is very expensive due to its moderate quality, and because a single crystal silicon layer with excellent crystallinity cannot be formed on sapphire, the carrier mobility of semiconductor devices is small and leakage occurs. Because of the large size, problems often arise in that it is not suitable for forming a dynamic type memory element.

Therefore, in order to solve the problems in the SO8 structure as described above, a method has been proposed in which a single crystal silicon layer is grown on an insulating film (particularly a silicon dioxide film) provided on a silicon substrate, and the This is a semiconductor device manufactured by 80IS@ in which a semiconductor device is formed on a single crystal silicon layer.

However, in the conventional manufacturing method of a semiconductor device having an 80IS structure, as shown in FIG. A polycrystalline 84 layer 3 deposited on a crystalline silicon (Si) substrate 2 is exposed to an energy beam, for example, a laser fist beam 4.
(arrow 5 is the scanning direction), since the polycrystalline Si layer 3 on the Si film 1 had been single-crystallized, its upper position was 8i0. From the polycrystalline Si layer 3 in the region directly in contact with the single crystal Si substrate 2, which is located lower than the top surface of the film l, to 8i0, which is located at a higher position. [Single crystallization of the single crystal 81 having the same crystal orientation as the substrate 2 was progressing toward the polycrystalline St layer 3 on top of the polycrystalline St layer 3. Therefore, as shown in FIG. 1(b), 8i0. A cutout part 7 of the single crystal Si layer 6 is likely to be formed on the edge of the film l facing the laser beam scanning direction 5, and a single crystal with uniform crystal orientation is formed on each island of Sin and HXl. There is a problem in that it is difficult to form a crystalline Si layer, and the performance and manufacturing yield of semiconductor devices are reduced.

An object of the present invention is to provide a method for forming a single crystal silicon layer with excellent crystallinity and no defects on an insulating layer, and to eliminate the above-mentioned problems.

That is, the present invention provides a method for manufacturing a semiconductor device having a 5OI8 structure, in which a single silicon layer is laminated in an island shape on a lower single crystal silicon substrate with an insulating film interposed therebetween, and a semiconductor element is formed on the single crystal silicon layer. When forming the single crystal silicon layer, a concave region and a convex region are formed on the surface of the single crystal silicon substrate, and the upper surface is higher than the upper surface of the convex region on the concave region of the single crystal silicon base 14-@. selectively forming a low insulating film, forming a polycrystalline silicon layer covering the convex region and the insulating layer on the surface of the single crystal silicon substrate, scanning and melting the polycrystalline silicon layer with an energy beam, The method is characterized in that it includes a step of monocrystallizing the polycrystalline silicon layer from above the convex region of the single-crystal silicon substrate toward the insulating layer.

The present invention will be described below with reference to INIP+1, Figure 2 (a).
The process trend chart shown in (0) to (0) is used to complete the process in detail.

In order to form a semiconductor device with an 80I8 structure by the method of the present invention, as shown in FIG.
)) On the substrate 11, a thickness of about 1000 (X) from the conventional chemical vapor deposition (OVD) IC! After forming the F silicon nitride (8hN4) film 12', a plurality of 7-hole resist patterns 13 having a desired shape are formed in island shapes on the 8-molecular weight 12', as shown in FIG. is formed using a normal photo process, and then phosphoric acid (HsP04
81s N by wet etching method using %
4 Ml 2' was selectively etched, and then the JLI crystalline Si substrate 11° was selectively etched using a reactive ion etching type etching method using carbon dichloride difluoride (001°Fm). As shown in Figure (C), for example, 1 [μm
) is formed. In Figure 3, 8i, N, single crystal 84 substrate 1 under pattern 12
1 is referred to as a convex region 15. The single-crystal 8i substrate 11 may be etched by a wet etching method or a goodsma etching method, but when forming an insulating film only in the concave region 14 in a later step, the etching process may be performed on the sides of the convex region 15. In order to make the formed insulating film as thin as possible, the above-mentioned reactive ion zero etching is most preferable. Then, the edge where the photoresist notch 13 is removed is 8i as shown in No. 21g(d).
, N, using the turn 12 as a mask, the single crystal 81 substrate 11 surface is selectively thermally oxidized at a temperature of about 1000 (II') in a full III element (0,) to form a recessed portion of the substrate. A silicon dioxide (850) film 16 having a thickness of approximately 6000 to 7000 (X) is formed on the upper surface of the region 14 . At this time, the top surface of the #810s expansion 16 is approximately 3000 to 4000 (people) lower than the top surface of the convex region 15 of the deposited crystal S1 substrate 11, and the surface of the convex region 1511 of the single crystal 81 substrate 11 is also 2000 to 4000. Thin 8i0@[1
6' is formed. Then phosphoric acid (HI P Oa )
84 on the single crystal 81 substrate 11 convex region 15 using a
N, the pattern 12 is dissolved and removed, and a thin S on the side surface of the convex region 15 is etched using a high-temperature (HF) etching solution.
10yo [l! 16' is dissolved and removed to selectively leave the StO film 16 on the concave region 14 of the single crystal 8i substrate 11, as shown in FIG. 2(C). In addition, the above-mentioned hydrofluoric acid (HF
) system, the 8i0 on the recessed area 14
．． Since the film 16 is also etched by about 2,000 to 3,000 [l], the thickness of the Si film 16 is about 4,000 (A), and the upper surface of the SiO film 16 and the convex region 1 of the substrate are
5. The difference in level from the top surface is about 5,000 to 7,000 (A). In addition, since the etching process forms rounded corners 17 on the SiO film 16, when growing a polycrystalline Si layer on the SiO film 16 in a later step, Abnormal growth does not occur on the corner 17. Next, a second layer was formed by a conventional chemical vapor deposition (OVD) method using thermal decomposition of monosilane (84H4) + diborane (t3tL).
As shown in Figure (f), 8i0. membrane 16
P- with a thickness of about 3000 to 5000 (X) that covers the face
A type single crystal Si layer 18 is deposited. Then the single crystal 8
With the i-substrate 11 heated to, for example, about 500 to 700 (C), a 0W-coil with a melting area diameter of 50 (μmφ) and an output of 10 to 1a (W) degrees is applied to the surface of the P-fi polycrystalline Si layer 18. The Ar laser beam 19 is scanned at a speed of about 10 liters (arrow 20 indicates the scanning direction), and the P-type polycrystalline Si layer 1B is sequentially melted and then rapidly cooled as the beam moves to form the bottom part. As shown in FIG.
P-type single crystal Si layer 21 with a thickness of about 5000 (X)
form. Furthermore, Mukuro single crystallization is made into single crystal 8i1: t&i
8i0.11 with the convex region 15 as the core. jlli16 As the upper row progresses, the formed P-Kan single crystal 84 layer 2
1 becomes a high-quality single crystal layer having the same plane orientation as the single crystal 84 substrate 11, and the polycrystalline layer on the convex region 15 of 1 becomes a single crystal 81 substrate where the single crystallization is at a high position as described above. 8 i 0. located at a low position from the 81st layer. The 8i0. , 8i0., @16 High quality P-fi single crystal 81 layer 2 with uniform crystal orientation over the entire area
1 is formed. Next, as shown in FIG. 2) using a normal device forming method, a gate oxide film 22 and a gate electrode 2 are formed on the surface of the P-type single crystal 84 layer 21 on the Sin film 16.
3. Form N-channel MO8) run star 25 with N-type source-dray/region 24, then #E2 diagram (i
), the N-channel M08 transistor 25 is covered with a photoresist group 26, and the single-crystal Si layer 21 and the convex region 15 of the single-crystal 84 substrate 11 are selectively etched by a conventional method to form isolation #127. A P-type single crystal Si layer 21. is formed as shown in FIG. N-channel Moa transistor 2 consisting of gate oxide 111[22, gate electrode 11i23, and N-type source/drain region 24]
5 or Sin, j1115 via single crystal 8-group 1[11
A plurality of semiconductor elements of 80ISll structure are formed on the substrate, separated and arranged in an island shape. Although not shown, these semiconductor elements are connected by desired wiring to provide a semiconductor device with an 80I8 structure.In the above embodiment, the insulating film interposed between the semiconductor element and the crystal 84 substrate is Thermal oxidation 8 i 0. The wrinkle 840□ film was OV.
0VD-8 may be formed by the D method and is limited to fathers.
4.N4 film or 0VD-alumina (A'*Qa) film may also be used.

Further, when converting the polycrystalline 8-layer into a single crystal, energy beams other than electron beams or laser beams may be used.

Refreshingly, there is also an 80I 8-type conductor package* with a structure in which semiconductor elements are laminated in two or more layers with insulation S interposed therebetween by the method of the present invention.
It is also possible to form a convex region on the single crystal 81 layer, and then proceed with the process according to the above embodiment.

As explained above, according to the present invention, an insulating film with a constant plane orientation and crystalline ★
Uniformly shape the single crystal silicon layer

[Brief explanation of drawings]

111th! ! J(a) to Φ) are conventional monocrystalline silicon silicon on the insulating layer (i) T-line surface 1i/+
Tate Q &/l /+I TL filtration/il is a process sectional view of one embodiment of the method of the present invention. In the figure, 11 is a single crystal silicon substrate, 12' is a silicon nitride film, 12 is a silicon nitride turn, 13 and 26 are photoresist turns, 14 is a concave area, and 15 is a convex area. , 16 is a silicon dioxide film, 16' is a thin silicon dioxide film, 17 is a rounded corner, 18
is a P-type polycrystalline silicon layer, 19 is 0W-Arv-the
20 is a laser beam scanning direction, 21 is a P-hole single crystal silicon layer, 22 is a gate oxide film, 2 and 3 are gate electrodes, 24 is an N-type source/drain region, 25 is MO
S transistor, 27 indicates a separation trench. Akira 1 Figure 2 % 2 (21 Calculation 2 Figure

Claims (1)

[Claims] 80I8 (8iHconOn In) in which a single crystal silicon layer is laminated in an island shape on a lower single crystal silicon substrate via an insulating group, and a semiconductor element is formed on the single crystal silicon layer.
In the method for manufacturing a semiconductor device having a structure (sulating 8 substrate), when forming the single crystal silicon layer, a concave region and a convex region are formed on the surface of the single crystal silicon substrate, and a concave region on the surface of the single crystal silicon substrate is formed. selectively forming an insulating film whose upper surface is lower than the upper surface of the convex region, forming a polycrystalline silicon layer extending over the convex region and the insulating film on the surface of the single crystal silicon substrate; 1. A method for manufacturing a semiconductor device, comprising the steps of: scanning and melting a layer with an energy beam; and single-crystallizing the polycrystalline silicon layer from a convex region η) of a single-crystal silicon substrate toward an insulation stage.