JPS5873135A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent any corrosion of an Al wiring by a high-density PSG resulting from an incorrect alignment, by covering a part of the high-density PSG with a part of a connecting poly-Si layer. CONSTITUTION:A poly-Si gate layer 14 is provided on an insulating film 13 on an Si substrate 11, and an impurity-introducing layer 12 is provided. The whole surface is covered with a high-density PSG 15, and windows are opened therein. Then, corners are rounded on heating. Then, a P-doped connecting poly-Si layer 21 is selectively formed and subsequently, a low-density PSG 17 is overlaid thereon and rounded on heating. Next, windows 18 smaller than those in the layer 21 are opened in the layer 17. Then, an Al wiring 19 is formed which connects with the layer 21 through the windows 18, and is covered with a low- density PSG 20 to reach completion. By this constitution, if there should be an incorrect alignment, there will be no possiblity that the high-density PSG is exposed to corrode the Al wiring. Accordingly, the reliability is improved.

Description

[Detailed description of the invention] The present invention relates to a semiconductor device and a method for manufacturing the same.

Recent semiconductor devices have become increasingly multilayered, and the steps within the pattern have become extremely large. Furthermore, as the pattern becomes finer, the width of the wiring becomes narrower, and the disconnection of the wiring that crosses the step has a large impact on the yield.

To prevent this disconnection, generally an oxide film containing high #& phosphorus (hereinafter referred to as phosphorus glass) is grown as a pre-process of forming the interconnection/M, and then heat treated to fluidize the phosphorus glass. A method is used to eliminate the difference in height between the steps. This method eliminated the disconnection of the wiring, but this T#bm
Lin glass, which contains phosphorus, has the disadvantage of high water absorption. That is, it reacts with phosphorous glass L water containing a high concentration of phosphorus, converting into phosphoric acid, which corrodes aluminum, which is widely used as metal wiring in integrated circuits, and causes the wiring to break. When a semiconductor chip is assembled into a ceramic or metal case, there are fewer wiring problems, but when the chip is assembled into a glass case, water can easily pass through the glass case, so water that has seeped into the glass case may cause problems. ↓The cylinder glass will melt and corrode the aluminum wiring. Therefore, when using a phosphorus glass layer containing a high concentration of phosphorus, it is necessary to take measures against moisture resistance.

As a measure against moisture, plasma nitride film (8i, N4) is used.
Although the plasma nitride film has excellent moisture resistance, it has a large amount of unreacted water inside the film, which can be difficult to heat through heat treatment or the BT test (Bias Temperature Test).
On the other hand, from the viewpoint that the water resistance is good when the phosphorus concentration is small, the phosphorus glass layer and the gold maple wiring layer are A method of inserting a low-strength phosphorus glass layer between the two was developed as an excellent and stable method in terms of moisture resistance and properties.

FIGS. 1(a) to 1(e) are single-pole cross-sectional views for explaining an example of a conventional method of manufacturing a semiconductor device using phosphor glass.

First, as shown in w & 1 figure (a), a P warm body substrate 1
A gate oxide film 3 is formed, then a gate 4 is formed with polysilicon, a source/drain diffusion layer 2 is formed, and a phosphorous layer containing high-III phosphorus (hereinafter referred to as high A phosphorus glass layer) 5 is grown.

Next, as shown in 1-φ), a window 6 for taking out the wiring is opened in the layer 3 above the source/drain diffusion layer 2.

Next, as shown in No. 1 (6) (C), 900 to 100
Heat treatment is carried out at 0°C to fluidize the high-concentration phosphorus glass layer 5.
A layer I (referred to as a phosphor glass layer) 7 is formed.

Next, as shown in FIG. 1(d), a window 8 is opened in the low-temperature glass layer 7. This window 8 must be opened smaller than the window 6 shown in Figure Φ) of wIJ1. Be careful as the wrinkle linkage layer 5 will come out.

Next, as shown in #41 figure (e), the aluminum arrangement!
11119, and finally, link layer 10 in the lower stage.
nuclides and performs chip maintenance.

Even if the chip made in this way is placed in a TI7° plastic case, it has the same moisture resistance as Kanashi. However, a drawback of this method is that it is susceptible to misalignment during photoresist etching. In other words, the window 8 shown in FIG. 1(d) is smaller than the window 6 shown in FIG. If it is not sufficient, the glazing glass layer 5 will not be exposed to the window 8 due to misalignment of 1i, resulting in poor moisture resistance and, in turn, poor insulation.

The present invention eliminates the above-mentioned drawbacks, and provides a semiconductor device and a method for manufacturing the same, in which disconnection of the υ interconnection is reduced by improving moisture resistance, thereby improving reliability.

The semiconductor device of the present invention includes: - a semiconductor substrate having an impurity-introduced layer on its main surface; an insulator made of oxide or nitride that melts the main surface; a linker glass layer, a ringer 27 layer of #distribution 1 on the impurity introduction layer, a first window for connection provided in the insulator, and the first window and the first window. A connecting hole layer is soldered on the first link glass layer at the periphery, and a connecting layer is soldered on the first link glass layer and the connecting polysilicon layer, and a connecting layer is soldered on the connecting polysilicon layer. a second phosphorus glass layer doped with phosphorus;
A third layer of low-concentration phosphor 7 is provided on the link glass layer of the conductor wiring and the I# glue 1s2 and is connected to the connecting polysilicon dove. and a phosphorus glass layer.

The method for manufacturing a semiconductor device of the present invention also includes the steps of: - forming a thick layer of oxide or nitride on the main surface of a semiconductor substrate on which an impurity-introduced layer is formed; A step of forming a phosphor glass layer of the rug 1 of high pseudo-phosphorous doped ridges, a step of forming a window of the plane 1 on the insulator and the first phosphor glass layer on the impurity introduction layer, and heating. a heat treatment step for rounding the corners of the first phosphorus glass layer; and a step for selectively forming a phosphorus-doped connecting polysilicon layer that connects the first window and the first phosphorus glass layer at its periphery. , a step of forming a phosphorus glass layer doped with a low concentration of phosphorus to solder the previous Efi' connection polysilicon layer and the link glass layer 1, and a second phosphorus glass layer on the connection polysilicon layer. forming a second window with a smaller opening size than the connecting polysilicon layer; The method includes the steps of selectively forming a conductor wiring to be connected to the layer, and forming a third phosphorus glass layer doped with phosphorus at a low concentration on the conductor wiring and the second phosphorus glass layer.

Next, embodiments of the present invention will be explained using the drawings.

FIG. 2 is a sectional view of one embodiment of the semiconductor device of the present invention.

An insulator 13 made of a waste compound or nitride is provided on a semiconductor substrate 11 having an impurity-introduced layer 12 on one main surface, and this insulation!
#, silicon layer 14 for gate and wiring on top of 13
will be established. High 1 on top of this polysilicon pigeon 14 and insulator
1 is provided with a J-doped glass layer 15;
A first window 16 is provided by etching the first phosphor glass layer 15 and the insulator 13 on the impurity introduction layer 12. This first window 16 is treated and the first edge of the periphery of this first window 16 is
Polysilicon dove 2 for connection hovers over the phosphor glass layer 15 of
1 will be provided. Next, a low-concentration phosphorus-doped layer 18 that covers the first linker glass layer 15 and the connecting polysilicon layer 21 and has a second window 18 having a smaller opening size than the connecting polysilicon layer 21 is formed on the first silicon layer 21. A second phosphor glass layer is provided.

On the second glue/glass layer 15, a conductor wiring 19f is provided, which is continuous to the contact layer 21, and on the conductor wiring 19 thereon and on the second phosphor glass layer 15, a low concentration phosphorus doped layer 19f is provided. By providing the third linker glass layer 20, the semiconductor device of the base embodiment is constructed.

Next, a method for manufacturing a semiconductor device according to the present invention will be explained.

Figures 3(a) to 3(d) are process cross-sectional views for illustrating one embodiment of the semiconductor device of the present invention.

First, as shown in FIG. 93(e), an insulator 13 made of silicon or nitride is provided on a semiconductor substrate 11, and a first polysilicon layer 14 serving as a gate or wiring is formed thereon.
The impurity introduced layer 12 is formed by ion implantation or diffusion. Next, on the insulating film 13 and the polysilicon layer 14 for gate and wiring, 10 to 13 molar
A phosphorus glass layer 15 of phosphorus-doped Ml is formed. Then, a first window 16 is formed in the insulating film 13 and the first phosphor glass layer 15 above the impure four-person floor 12. When heated, the first phosphor glass layer 15 is brought into a fluid state and the peripheral edge and other corners of the first window 16 are rounded. Heat death
The temperature is 900-1000°C.

Next, a phosphorus-doped polysilicon layer 21 for connection is selectively formed so as to melt the window 16 of #p11 and the first phosphorus glass layer 15 at the edge of the sliding door.

Next, as shown in FIG. 3(b), a second link glass layer 17 of a low-temperature ring glass is formed by soldering the connecting polysilicon layer 21 and the link glass Nl 115 of the glass 1. Then, the corners of the link glass layer 170 are rounded by heat treatment at a temperature of 900 to 1 ooo'c.

Next, as shown in FIG. 3(C), a second window 18 having an opening size smaller than that of the connecting polysilicon layer 21 is formed in the second phosphor glass layer 17 on the connecting polysilicon layer 21. Open.

Next, as shown in FIG. 3(d), a conductor wiring 19 is selectively formed to be connected to the connecting polysilicon skin 21 through the second window 18 provided on the second linker layer 17. do. A third phosphorus glass layer 20 of a low* degree phosphorus glass layer 20 is formed on the conductor wiring 119 and the second phosphorus glass layer 17. In this way, the semiconductor device of the present invention is manufactured.

When a moisture resistance test was conducted using the semiconductor device tk prepared as described above, it was found that the moisture resistance was significantly improved compared to conventional products, indicating that the semiconductor device according to the present invention has extremely excellent moisture resistance. As described in detail, according to the present invention, a part of the polysilicon layer for threading is structured so that a part of the 11ib chain layer/it layer is arranged. Because of this, the wrinkled glass layer will not be exposed due to misalignment and the aluminum wiring will not be corroded, resulting in a highly reliable semiconductor device.

[Brief explanation of drawings]

FIGS. 2(a) to 2(e) show step i91 for explaining an example of a method for manufacturing a semiconductor device using conventional phosphor glass.
The mountain diagram and FIG. 2 are cross-section 1 of an embodiment of the semiconductor device of the present invention.
43 (a) to (d) are process cross-sectional views for explaining a fruitful example of the method for manufacturing a semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Four source/drain diffusion layers, 3...Oxide film, 4...Gate, 5...Highly conductive phosphor Glass layer, 6...Curved window, 7
Yori・Low m degree・Link glass layer, 8...Four windows, 9...Curved aluminum wiring, lO...Low fIIk degree Lin glass layer, 11...Semiconductor substrate, 12... ...
・Impurity introduced layer, 13...Insulating film, 14...Curved gate and wiring 11 River polysilicon layer, ■・5...
...First phosphor glass layer, 16... Window, 17
...Second link glass Ik, 1B...Window,
19...A/1 minium, 2o...Ringa 7 Sunoso of song #J3, 21...&Horishirico for stakes 71m. 1st direction B
1B Figure 2 Figure 3 Procedural amendment (method) % formula % 1. Indication of case 1981 Fraud application No. 1722
No. 25 No. 2, Title of the invention: Semiconductor device and its manufacturing method 3, Relationship with the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4; Agent address: 5 Sumitomo Sanda Building, 37-8 Shiba 5-chome, Minato-ku, Tokyo 108, Japan Date of amendment order February 23, 1980 (shipment date) 6. [Brief explanation of drawings] of the amended specification for the United States Column J, page 12 of the statement of contents of the amendment W! In line J9, [Figure 2 tal ~ (e
) is corrected as ``toru'' as [Fig. 1(a) to (el is]).

Claims (2)

[Claims] (1) - A skeleton of a semiconductor substrate having an impurity-introduced layer on its main surface; an oxide or nitride insulator extending over the main surface; and a first phosphorous glass layer doped with high at phosphorus that handles the insulating film;
the first glass layer above the impurity introduction layer and a #11 window for connection provided in the insulator;
#1 A connection polysilicon layer that extends over the window of #1 and extends over the first link glass layer at the periphery of the window of #1, and connects the first link glass layer and the connection polysilicon layer. and on the connecting polysilicon layer, a low am phosphorus doped 20th phosphor glass layer having a @2 window with a smaller opening size than the edge connecting polysilicon layer, and on the previous kJ second phosphor glass layer. a conductor wiring and a pongee conductor wiring provided on the connecting polysilicon layer and a third phosphorous glass layer provided on the second linkage layer; Semiconductor equipment with % mold. (2) - Sales of semiconductor substrates with impurity introduction J- formed in raw boxes - The process of forming an oxide or elongated insulator on the main surface, and the process of forming an oxide or elongated insulator on the main surface and stripes of highly concentrated phosphorous doped that solder the front cape insulation. a step of forming a phosphor glass layer, a step of forming an Ml window on the insulating film on the impurity layer and a first link glass layer, and heating a corner of the first phosphor glass layer to #. a step of selectively forming a phosphorus-doped connecting polysilicon layer for soldering the first window and a first link glass layer at its periphery; a step of forming a second phosphorus glass layer with low a-containing phosphorous doping, and a step of forming a second phosphorus glass layer on the connection polysilicon layer with a layer smaller than the second polysilicon layer; a step of opening a second window of one size; a step of selectively forming a conductor wiring to be connected to the connection polysilicon layer through the window of IrU card 2 provided on the link glass layer of j12; The conductor wiring and the w
and forming a $3 phosphorus glass layer with low *& phosphorous doping on the &2 phosphorus glass layer.