JPH05267476A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable easy control of adhesion with an interface without using an coating insulating film in a semiconductor device having a multilayer interconnection structure. CONSTITUTION:A first wiring 3 is formed on a semiconductor substrate 1 with a foundation insulating film 2 between and a silicon nitride film is formed on the first wiring 3 as a first layer wiring insulating film 41. After a TEOS+O2 plasma oxide film is formed thereon as a second layer wiring insulating film 42, a projecting part of the TEOS+O2 plasma oxide film is removed entirely. Then, a TEOS+O2 oxide film is formed as a third layer wiring insulating film 43 and a second wiring is formed thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a conventional semiconductor device having a multilayer wiring structure. In this figure, 1 is a semiconductor substrate of silicon or the like, 2 is a base insulating film, 3 is this base insulating film 2
The first wiring is formed on the upper wiring 6, the interwiring insulating film 6 is formed on the first wiring 3, and the second wiring is formed on the interwiring insulating film 6.

In the structure of the conventional semiconductor device shown in FIG. 5, the inter-wiring insulating film 6 deposited on the first wiring 3 improves the patternability of the second wiring 5 formed thereon, and Sufficient flatness is required to improve the reliability level of the wiring. Hereinafter, a conventional method for manufacturing a semiconductor device, including the method for forming the inter-wiring insulating film 6, will be described with reference to FIGS.

In FIG. 6, the first wiring 3 and the second wiring 5 include metal wiring such as aluminum refractory metal, refractory metal silicide wiring, and polycrystalline silicon wiring. The case where the wiring 3 and the second wiring 5 are aluminum wirings will be described. First, as shown in FIG. 6A, the first wiring 3 is formed on the semiconductor substrate 1 with the underlying insulating film 2 interposed therebetween. Then, as shown in FIG. 6B, the first wiring 3 is formed on the first wiring 3. , "Silicon oxide film deposited by plasma CVD method using gas containing organosilane and oxygen as main components"
(Hereinafter, TEOS (tetraethyl orthosilicate) +
An O ₂ type plasma oxide film) or “a silicon oxide film deposited by a thermal CVD method using a gas containing organosilane and ozone as main components” (hereinafter referred to as TEOS + O ₃ type thermal oxide film) 61 is etched back or the like. Done, 2000-30
Formed to a thickness of 00Å. Hereinafter, the silicon oxide film which is the inorganic coating insulating film is referred to as a first-layer inter-wiring insulating film 61. Next, as shown in FIG. 6C, on the first-layer inter-wiring insulating film 61, silanol Si (O
H) An inorganic coating insulating film containing ₄ or the like as a main component is applied, and then baked at a temperature of 400 ° C. or higher to flatten the surface. Next, as shown in FIG.
Similar to the step (b), a TEOS + O ₂ system plasma oxide film is formed to a thickness of about 5000 to 6000Å. Hereinafter, this will be referred to as a third-layer inter-wiring insulating film 63. Finally, for example, aluminum wiring is formed as the second wiring 5 on the inter-wiring insulating film 6 formed of the first-third layer inter-wiring insulating films 61 to 63 thus formed.

[0005]

In the conventional semiconductor device formed by the above method, the wettability and the adhesiveness of the coating insulating film, which is the second-layer inter-wiring insulating film 62 in the inter-wiring insulating film 6, are provided. Depends largely on the state of the surface of the first-layer inter-wiring insulating film 61, and the cavity 64 in the coating insulating film as shown in FIG.
Or, it was a cause of generation of the crack 65 as shown in FIG.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a method for manufacturing a semiconductor device in which no cavity or crack is generated.

[0007]

According to a method of manufacturing a semiconductor device according to the present invention, a silicon nitride film is formed by a plasma CVD method on the lowermost layer of an inter-wiring insulating film consisting of three layers, and then a thermal CVD method is applied thereon. Alternatively, a second-layer silicon oxide film is formed by a plasma CVD method, the second-layer silicon oxide film is etched to a predetermined thickness, and then a third-layer silicon oxide film is formed by a plasma CVD method. A film is formed, and then a second wiring is formed on the third-layer silicon oxide film.

[0008]

In the present invention, since the silicon nitride film formed by the plasma CVD method is formed in the lowermost layer of the inter-wiring insulating film, damage to the first wiring due to etch back or sputter etching can be prevented. Further, since this silicon nitride film functions as a stopper, it is possible to frequently use etch back or sputter etching to form an inter-wiring insulating film having good flatness.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device formed according to the present invention. In this figure, 1 is a semiconductor substrate made of silicon or the like, 2 is a base insulating film deposited on the semiconductor substrate 1, 3 is a first wiring formed on the base insulating film 2,
4 is an inter-wiring insulating film deposited on the first wiring 3,
It consists of three layers 41-43. That is, the first-layer inter-wiring insulating film 41 is a silicon nitride film formed by the plasma CVD method and has a thickness of about 500 to 2000 Å. The second-layer inter-wiring insulating film 42 is a TEOS-based silicon oxide film and has a heat
After being formed by the VD method or the plasma CVD method, the film is etched back and remains in the recess. The third-layer inter-wiring insulating film 43 is a TEOS + O ₂ -based silicon oxide film,
It is formed by the plasma CVD method. Reference numeral 5 is a second wiring formed on the third-layer inter-wiring insulating film 43.

A method of depositing the inter-wiring insulating film 4 in the semiconductor device according to the present invention shown in FIG. 1 will be described with reference to FIGS. As in the case of the description of the conventional technique, the case where the first wiring 3 and the second wiring 5 are aluminum wirings will be described below.

As shown in FIG. 2A, after forming up to the first wiring 3 as in FIG. 6A, 280 to 400 ° C. is formed on the first wiring 3 as shown in FIG. 2B. The silicon nitride film (hereinafter also referred to as 41) is used as the first-layer inter-wiring insulating film 41 by plasma CVD at the film deposition temperature of 500 to 2000Å
Form. The silicon nitride film 41 has good step coverage, and it is easy to control the etching selection ratio with respect to the silicon oxide film. Next, as shown in FIG. 2C, a TEOS + O ₂ -based plasma CVD silicon oxide film (hereinafter, also referred to as TEOS + O ₂ -based plasma oxide film 42) is used as the second-layer inter-wiring insulating film 42 by using TEOS and O _2. 0.2 to 2.0 μm is formed. Next, FIG. 2 (d)
As described above, etching is performed by using etch back or sputter etching using an etching gas having a large selection ratio between the silicon nitride film 41 and the TEOS + O ₂ system plasma oxide film 42. At this time, the film thickness of the TEOS + O ₂ system plasma oxide film 42 is etched by etch back or sputter etching. As a result, the TEOS + O ₂ based plasma oxide film 42 on the convex portion is removed, but the TEOS + O ₂ based plasma oxide film 42 on the concave portion remains. In this case, the silicon nitride film 41
Protects the first wiring 3 from etching damage. Next, as shown in FIG. 2E, as the third-layer inter-wiring insulating film 43, for example, a TEOS + O ₂ -based plasma oxide film of 0.8 to
Form 1.0 μm.

In the above embodiment, the TEOS + O ₂ type plasma oxide film using TEOS and O ₂ was formed as the second-layer inter-layer insulating film 42, but as another embodiment, O _{3 is used.}
A TEOS + O ₃ -based thermal CVD silicon oxide film (hereinafter referred to as TEOS + O ₃ -based thermal oxide film) that can be formed even in a low temperature range of 350 to 450 ° C. using (ozone) and TEOS may be formed. Also at this time, a TEOS + O ₃ -based thermal oxide film is formed in a thickness of 0.2 to 2.0 μm.

Further, in the above embodiment, the TEOS + O ₂ type oxide film or TEOS is used as the second-layer interlevel insulating film 42.
An example of a single layer of + O ₃ -based thermal oxide film is shown, but TEOS +
The O ₂ -based oxide film and the TEOS + O ₃ -based thermal oxide film may be formed, for example, 0.2 μm each a plurality of times. This embodiment will be specifically described with reference to FIGS. 3A to 3D and FIGS. 4A to 4C. As shown in FIGS. 3A and 3B, as shown in FIG.
After forming a silicon nitride film as the first-layer inter-wiring insulating film 41 on the first wiring 3 in the same manner as in (a) and (b), FIG.
As shown in (c), the TEOS + O ₂ -based oxide film 71 is
For example, 0.2 μm is formed. Then, on top of this, see FIG.
As shown in, the TEOS + O ₃ based thermal oxide film 72 is formed to a thickness of 0.2 μm, for example. As shown in FIG. 4A, the TEOS + O ₂ -based oxide film 71 and the TEOS + O ₃ -based thermal oxide film 72 are repeatedly formed a plurality of times, for example, a few times, to form a plurality of layers alternately. Next, as shown in FIG. 4B, the silicon nitride film 41, the TEOS + O ₂ -based oxide film 71 and the TE
Etching back is performed using an etching gas having a large selection ratio of the composite film of the OS + O ₃ system thermal oxide film 72. At this time, the TEO formed in FIGS. 3C and 3D to FIG.
S + O ₂ system oxide film 71 and TEOS + O ₃ system thermal oxide film 72
The film thickness of is etched. As a result, the film on the convex portion is removed, but the film on the concave portion remains. At this time, the silicon nitride film 41 of FIG. 4B protects the first wiring 3 from damage due to etching. Next, as shown in FIG. 4C, a TEOS + O ₂ -based oxide film, for example, having a thickness of 0.8 to 1.0 μm is formed as the third-layer inter-layer insulating film 43.

[0014]

As described above, according to the present invention,
By forming the silicon nitride film as the lowermost layer of the inter-wiring insulating film composed of a plurality of layers, the first wiring can be protected from damage due to etch back. Further, since it is possible to use the etch back abundantly and it is unnecessary to use the coating insulating film which has been used conventionally, it is possible to provide a manufacturing method capable of obtaining a semiconductor device with a high yield in a stable process state.

[Brief description of drawings]

FIG. 1 is a sectional side view showing a semiconductor device according to an embodiment of the present invention.

2A to 2D are process cross-sectional views showing an embodiment of a method of manufacturing the semiconductor device shown in FIG.

FIG. 3 is a process sectional view showing another embodiment of the present invention.

FIG. 4 is a process sectional view subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing a conventional semiconductor device having a multilayer wiring structure.

FIG. 6 is a process cross-sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 7 is a cross-sectional side view of a semiconductor device showing a problem of a conventional insulating film forming method.

FIG. 8 is a sectional side view of a semiconductor device showing another problem of the conventional insulating film forming method.

[Explanation of symbols]

1 Semiconductor Substrate 2 Base Insulating Film 3 First Wiring 4 Interwiring Insulation Film 5 Second Wiring 41 Silicon Nitride Film (First Layer Interwiring Insulation Film) 42 TEOS + O ₂ System Plasma Oxide Film (Second Layer Interwiring Insulation Film) ) 43 TEOS + O ₂ type plasma oxide film (third layer inter-wiring insulating film)

Claims (1)

[Claims] 1. A first substrate formed on a semiconductor substrate via a base insulating film.
The step of forming the wiring, the step of patterning the first wiring, and the step of forming the first-layer silicon nitride film forming the inter-wiring insulating film by the plasma CVD method, and the step of forming the wiring on the silicon nitride film. A step of forming a second-layer silicon oxide film forming an inter-wiring insulating film by a thermal CVD method or a plasma CVD method, and a step of forming a thickness of the second-layer silicon oxide film by the first-layer silicon nitride film. A step of etching under an etching condition having a large selection ratio with respect to the film, a step of forming a third layer silicon oxide film forming the inter-wiring insulating film by a plasma CVD method, and a step of forming the third layer silicon oxide. And a step of forming a second wiring on the film.