JPH0689893A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0689893A JPH0689893A JP1044892A JP1044892A JPH0689893A JP H0689893 A JPH0689893 A JP H0689893A JP 1044892 A JP1044892 A JP 1044892A JP 1044892 A JP1044892 A JP 1044892A JP H0689893 A JPH0689893 A JP H0689893A
- Authority
- JP
- Japan
- Prior art keywords
- film
- stress
- semiconductor device
- layer electrode
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の構造に関
し、特に層間絶縁膜の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device, and more particularly to the structure of an interlayer insulating film.
【0002】[0002]
【従来の技術】半導体装置では、配線に必要な面積を減
少させ高集積度化高密度化を実現するために二層または
それ以上の電極を形成している。各層の電極の間には酸
化珪素膜(以下SiO2 膜と称する)等が形成されてお
り絶縁分離されている。この層間絶縁膜には以下の特性
が要求される。2. Description of the Related Art In a semiconductor device, two or more layers of electrodes are formed in order to reduce the area required for wiring and realize high integration and high density. A silicon oxide film (hereinafter referred to as a SiO 2 film) or the like is formed between the electrodes of each layer and is insulated and separated. The interlayer insulating film is required to have the following characteristics.
【0003】1.ステップカバレージが良いこと。1. Good step coverage.
【0004】2.電極との密着性のよいこと。2. Good adhesion with the electrode.
【0005】3.耐クラック性のよいこと。3. Good crack resistance.
【0006】4.耐圧の高いこと。 以上の要件を満たし、 1.低温で形成できる。4. High pressure resistance. Meet the above requirements, It can be formed at low temperature.
【0007】2.外界からの水分やナトリウムなどの不
純物の侵入を妨げる役割が顕著である。 という特長のあるプラズマCVD法により形成された窒
化珪素膜(以下プラズマ窒化膜と略す)が主に層間絶縁
膜として使われている。2. The role of preventing the invasion of impurities such as water and sodium from the outside is remarkable. A silicon nitride film (hereinafter abbreviated as plasma nitride film) formed by the plasma CVD method, which has the feature that is mainly used as an interlayer insulating film.
【0008】図3は層間絶縁膜にプラズマ窒化膜が用い
られている代表的な例である。表面がシリコン酸化膜等
でおおわれ、内部に半導体素子が形成されたシリコン基
板1上に第一層電極2が形成されており、この上にプラ
ズマ窒化膜3および第二層電極4が形成されている。第
一層電極2と第二層電極4とはプラズマ窒化膜3をエッ
チングして作られたスルーホールにより電気的に接続さ
れている。FIG. 3 shows a typical example in which a plasma nitride film is used as an interlayer insulating film. A first layer electrode 2 is formed on a silicon substrate 1 whose surface is covered with a silicon oxide film and a semiconductor element is formed inside, and a plasma nitride film 3 and a second layer electrode 4 are formed on this. There is. The first layer electrode 2 and the second layer electrode 4 are electrically connected by a through hole formed by etching the plasma nitride film 3.
【0009】[0009]
【発明が解決しようとする課題】近年、半導体装置の集
積化が進みパターン幅が狭くなり、しかもパターン幅と
膜厚との比(以後これをアスペクト比と称する)が大き
くなった。このため層間絶縁膜の平坦性を良くするよう
にプラズマ窒化膜の膜厚を厚することが必要となってき
た。ところがプラズマ窒化膜の膜厚を大きくすると内部
応力が大きくなり、このためにプラズマ窒化膜に亀裂が
入り外部からの不純物の侵入が容易になるという問題点
があった。In recent years, the integration of semiconductor devices has advanced, the pattern width has become narrower, and the ratio between the pattern width and the film thickness (hereinafter referred to as the aspect ratio) has increased. Therefore, it has become necessary to increase the thickness of the plasma nitride film so as to improve the flatness of the interlayer insulating film. However, when the thickness of the plasma nitride film is increased, the internal stress is increased, which causes a crack in the plasma nitride film, which facilitates the intrusion of impurities from the outside.
【0010】[0010]
【課題を解決するための手段】本発明によれば、層間絶
縁膜として内部応力が引張り応力と圧縮応力のかかる方
向の異なる2種類の絶縁物を用い、互いに積層した絶縁
膜を用いた半導体装置を得る。According to the present invention, as an interlayer insulating film, two kinds of insulators having different internal stresses in directions in which tensile stress and compressive stress are applied are used, and a semiconductor device using insulating films laminated on each other is used. To get
【0011】[0011]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0012】図1は本発明の一実施例を示す半導体装置
の電極部の断面図である。内部に半導体素子が形成さ
れ、表面が接続用開口のある絶縁膜(例えば、SiO2
膜)でおおわれたシリコン基板11上に厚さ0.5μm
の第一層電極12が形成されている。その上に厚さ1.
0μmのプラズマ窒化膜13が成長され、さらにこの上
に1.0μmの常圧CVD法で形成されたSiO2 膜1
5が成長され、層間絶縁膜を形成している。第一層電極
12と第二層電極14とは層間絶縁膜の所定の場所をエ
ッチングすることによりできたコンタクトホールの部分
で電気的に接続されている。FIG. 1 is a sectional view of an electrode portion of a semiconductor device showing an embodiment of the present invention. An insulating film (for example, SiO 2) having a semiconductor element formed inside and a surface having an opening for connection is formed.
0.5 μm thick on a silicon substrate 11 covered with a film)
1st layer electrode 12 of is formed. On top of that 1.
A plasma nitride film 13 having a thickness of 0 μm is grown, and a SiO 2 film 1 having a thickness of 1.0 μm and formed by a normal pressure CVD method is further formed thereon.
5 is grown to form an interlayer insulating film. The first layer electrode 12 and the second layer electrode 14 are electrically connected to each other at a contact hole portion formed by etching a predetermined place of the interlayer insulating film.
【0013】ここでプラズマ窒化膜3の内部応力は圧縮
圧力でありその大きさは4×109dyn/cm2 であ
る。一方SiO2 膜5の内部応力は引張り応力でその大
きさは6〜8×108 dyn/cm2 で2つの膜の内部
応力はほぼ打ち消される。Here, the internal stress of the plasma nitride film 3 is a compressive pressure and its magnitude is 4 × 10 9 dyn / cm 2 . On the other hand, the internal stress of the SiO 2 film 5 is tensile stress and its magnitude is 6 to 8 × 10 8 dyn / cm 2 , and the internal stresses of the two films are almost canceled.
【0014】同様な効果がSiO2 膜の代りにリンシリ
ケートガラス膜(Phospho−Silicate
Glass)を用いても得られる。A similar effect is obtained by using a phosphosilicate glass film (Phospho-Silicate) instead of the SiO 2 film.
It can also be obtained by using Glass).
【0015】図2は本発明の他の実施例を示す半導体装
置の電極部の断面図である。内部に半導体素子が形成さ
れ、表面がSiO2 膜等で電極接続部を除いておおわれ
たシリコン基板21上に厚さ2.0μm、電極幅1.0
μmアスペクト比が2の第一層電極22が形成されてい
る。その上に厚さ1.5〜2.0μmのプラズマ窒化膜
23が形成されている。その上にさらに1.5〜2.0
μmのSiO2 膜25および0.5〜2.0μmのプラ
ズマ窒化膜26が形成されて、3層の層間絶縁膜を形成
している。第一層電極22と第二層電極24は層間絶縁
膜の所定の場所をエッチングすることによってできたコ
ンタクトホールの部分で電気的に接続されている。FIG. 2 is a sectional view of an electrode portion of a semiconductor device showing another embodiment of the present invention. A semiconductor element is formed inside, and the surface is covered with a SiO 2 film or the like except for the electrode connection portion. The thickness is 2.0 μm and the electrode width is 1.0 μm on the silicon substrate 21.
A first layer electrode 22 having a μm aspect ratio of 2 is formed. A plasma nitride film 23 having a thickness of 1.5 to 2.0 μm is formed thereon. 1.5-2.0 on top of it
A SiO 2 film 25 having a thickness of 0.5 μm and a plasma nitride film 26 having a thickness of 0.5 to 2.0 μm are formed to form a three-layer interlayer insulating film. The first layer electrode 22 and the second layer electrode 24 are electrically connected to each other through a contact hole formed by etching a predetermined place of the interlayer insulating film.
【0016】ここでプラズマ窒化膜の内部応力は圧縮応
力であり、その大きさは4×109dyn/cm2 であ
る。一方SiO2 膜の内部応力は引張り応力でその大き
さは6〜8×108 dyn/cm2 である。よってこの
2つの膜の内部応力はほぼ打ち消される。Here, the internal stress of the plasma nitride film is a compressive stress, and its magnitude is 4 × 10 9 dyn / cm 2 . On the other hand, the internal stress of the SiO 2 film is tensile stress and its magnitude is 6 to 8 × 10 8 dyn / cm 2 . Therefore, the internal stress of these two films is almost canceled.
【0017】またリン・シリケート・ガラス膜(以下P
SG膜と称す)も引張り応力を持っているので、同様な
効果がSiO2 膜の代りにPSG膜を用いても得られ
る。Further, a phosphorus silicate glass film (hereinafter P
Since a SG film) also has a tensile stress, the same effect can be obtained by using a PSG film instead of the SiO 2 film.
【0018】[0018]
【発明の効果】以上説明したように本発明は、プラズマ
窒化膜と内部応力の違うSiO2 膜やPSG膜をプラズ
マ窒化膜層上に成長させているので、内部応力が低減で
き平坦度が高くなるまで十分層間絶縁膜の膜厚を厚くす
ることができる。As described above, according to the present invention, since the SiO 2 film or the PSG film having a different internal stress from the plasma nitride film is grown on the plasma nitride film layer, the internal stress can be reduced and the flatness can be improved. Until then, the thickness of the interlayer insulating film can be increased sufficiently.
【図1】本発明の一実施例による半導体装置の電極部の
断面図FIG. 1 is a sectional view of an electrode portion of a semiconductor device according to an embodiment of the present invention.
【図2】本発明の他の実施例による半導体装置の電極部
の断面図FIG. 2 is a sectional view of an electrode portion of a semiconductor device according to another embodiment of the present invention.
【図3】従来の半導体装置の電極部の断面図FIG. 3 is a sectional view of an electrode portion of a conventional semiconductor device.
1,11,21 シリコン基板 2,12,22 第一層電極 3,13,23,26 プラズマ窒化膜 4,14,24 第二層電極 5,15,25 SiO2 膜1,11,21 Silicon substrate 2,12,22 First layer electrode 3,13,23,26 Plasma nitride film 4,14,24 Second layer electrode 5,15,25 SiO 2 film
Claims (4)
縮応力の応力のかかる方向の異なる2種類の絶縁物を用
いたことを特徴とする半導体装置1. A semiconductor device characterized in that, as the insulating film, two kinds of insulators having different internal stresses in different directions in which tensile stress and compressive stress are applied are used.
化物とシリコン酸化物であることを特徴とする請求項1
記載の半導体装置2. The two different types of insulators are plasma nitride and silicon oxide.
Described semiconductor device
れていることを特徴とする請求項1記載の半導体装置3. The semiconductor device according to claim 1, wherein the insulating film is composed of three or more insulating films.
類の絶縁物の一方を他方がはさむように積層されている
ことを特徴とする請求項3記載の半導体装置4. The semiconductor device according to claim 3, wherein the three or more insulating films are laminated such that one of the two different kinds of insulators is sandwiched by the other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1044892A JPH0689893A (en) | 1991-11-11 | 1992-01-24 | Semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29466391 | 1991-11-11 | ||
JP3-294663 | 1991-11-11 | ||
JP1044892A JPH0689893A (en) | 1991-11-11 | 1992-01-24 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0689893A true JPH0689893A (en) | 1994-03-29 |
Family
ID=26345722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1044892A Pending JPH0689893A (en) | 1991-11-11 | 1992-01-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0689893A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998052227A1 (en) * | 1997-05-13 | 1998-11-19 | Mitsubishi Denki Kabushiki Kaisha | Dielectric thin film element and method for manufacturing the same |
US5897376A (en) * | 1993-09-20 | 1999-04-27 | Seiko Instruments Inc. | Method of manufacturing a semiconductor device having a reflection reducing film |
WO2003012859A1 (en) * | 2001-07-30 | 2003-02-13 | Mitsubishi Denki Kabushiki Kaisha | Electrode structure, and method for manufacturing thin-film structure |
JP2010074173A (en) * | 2009-10-08 | 2010-04-02 | Mitsubishi Electric Corp | Electrode structure |
WO2011125928A1 (en) * | 2010-04-01 | 2011-10-13 | ローム株式会社 | Semiconductor device and method for manufacturing same |
EP3046146A1 (en) * | 2015-01-14 | 2016-07-20 | Fuji Electric Co. Ltd. | High breakdown voltage passive element and high breakdown voltage passive element manufacturing method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61154133A (en) * | 1984-12-21 | 1986-07-12 | ドイチエ・アイテイーテイー・インダストリーズ・ゲゼルシヤフト・ミト・ベシユレンクタ・ハフツンク | Plastic capsule sealed semiconductor device |
JPS61279132A (en) * | 1985-06-05 | 1986-12-09 | Sony Corp | Semiconductor device |
JPS62137855A (en) * | 1985-12-12 | 1987-06-20 | Sumitomo Electric Ind Ltd | Semiconductor device having multilayer interconnection structure |
JPH01207932A (en) * | 1988-02-16 | 1989-08-21 | Fuji Electric Co Ltd | Semiconductor device |
-
1992
- 1992-01-24 JP JP1044892A patent/JPH0689893A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61154133A (en) * | 1984-12-21 | 1986-07-12 | ドイチエ・アイテイーテイー・インダストリーズ・ゲゼルシヤフト・ミト・ベシユレンクタ・ハフツンク | Plastic capsule sealed semiconductor device |
JPS61279132A (en) * | 1985-06-05 | 1986-12-09 | Sony Corp | Semiconductor device |
JPS62137855A (en) * | 1985-12-12 | 1987-06-20 | Sumitomo Electric Ind Ltd | Semiconductor device having multilayer interconnection structure |
JPH01207932A (en) * | 1988-02-16 | 1989-08-21 | Fuji Electric Co Ltd | Semiconductor device |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5897376A (en) * | 1993-09-20 | 1999-04-27 | Seiko Instruments Inc. | Method of manufacturing a semiconductor device having a reflection reducing film |
WO1998052227A1 (en) * | 1997-05-13 | 1998-11-19 | Mitsubishi Denki Kabushiki Kaisha | Dielectric thin film element and method for manufacturing the same |
JP4540983B2 (en) * | 2001-07-30 | 2010-09-08 | 三菱電機株式会社 | Method for manufacturing electrode structure and thin film structure |
WO2003012859A1 (en) * | 2001-07-30 | 2003-02-13 | Mitsubishi Denki Kabushiki Kaisha | Electrode structure, and method for manufacturing thin-film structure |
US6812568B2 (en) | 2001-07-30 | 2004-11-02 | Mitsubishi Denki Kabushiki Kaisha | Electrode structure, and method for manufacturing thin-film structure |
JPWO2003012859A1 (en) * | 2001-07-30 | 2004-11-25 | 三菱電機株式会社 | Method for manufacturing electrode structure and thin film structure |
CN100355057C (en) * | 2001-07-30 | 2007-12-12 | 三菱电机株式会社 | Electrode structure, and method for manufacturing thin-film structure |
JP2010074173A (en) * | 2009-10-08 | 2010-04-02 | Mitsubishi Electric Corp | Electrode structure |
WO2011125928A1 (en) * | 2010-04-01 | 2011-10-13 | ローム株式会社 | Semiconductor device and method for manufacturing same |
US9425147B2 (en) | 2010-04-01 | 2016-08-23 | Rohm Co., Ltd. | Semiconductor device |
EP3046146A1 (en) * | 2015-01-14 | 2016-07-20 | Fuji Electric Co. Ltd. | High breakdown voltage passive element and high breakdown voltage passive element manufacturing method |
US10224390B2 (en) | 2015-01-14 | 2019-03-05 | Fuji Electric Co., Ltd. | High breakdown voltage passive element and high breakdown voltage passive element manufacturing method |
US10566410B2 (en) | 2015-01-14 | 2020-02-18 | Fuji Electric Co., Ltd. | High breakdown voltage passive element |
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Legal Events
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A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980707 |